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25#ifndef S390X_CPU_H
26#define S390X_CPU_H
27
28#include "cpu-qom.h"
29#include "cpu_models.h"
30#include "exec/cpu-defs.h"
31
32#define ELF_MACHINE_UNAME "S390X"
33
34
35#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
36
37#define TARGET_INSN_START_EXTRA_WORDS 2
38
39#define MMU_MODE0_SUFFIX _primary
40#define MMU_MODE1_SUFFIX _secondary
41#define MMU_MODE2_SUFFIX _home
42#define MMU_MODE3_SUFFIX _real
43
44#define MMU_USER_IDX 0
45
46#define S390_MAX_CPUS 248
47
48typedef struct PSW {
49 uint64_t mask;
50 uint64_t addr;
51} PSW;
52
53struct CPUS390XState {
54 uint64_t regs[16];
55
56
57
58
59 uint64_t vregs[32][2] QEMU_ALIGNED(16);
60 uint32_t aregs[16];
61 uint8_t riccb[64];
62 uint64_t gscb[4];
63 uint64_t etoken;
64 uint64_t etoken_extension;
65
66
67 struct {} start_initial_reset_fields;
68
69 uint32_t fpc;
70 uint32_t cc_op;
71 bool bpbc;
72
73 float_status fpu_status;
74
75
76 uint64_t retxl;
77
78 PSW psw;
79
80 S390CrashReason crash_reason;
81
82 uint64_t cc_src;
83 uint64_t cc_dst;
84 uint64_t cc_vr;
85
86 uint64_t ex_value;
87
88 uint64_t __excp_addr;
89 uint64_t psa;
90
91 uint32_t int_pgm_code;
92 uint32_t int_pgm_ilen;
93
94 uint32_t int_svc_code;
95 uint32_t int_svc_ilen;
96
97 uint64_t per_address;
98 uint16_t per_perc_atmid;
99
100 uint64_t cregs[16];
101
102 int pending_int;
103 uint16_t external_call_addr;
104 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS);
105
106 uint64_t ckc;
107 uint64_t cputm;
108 uint32_t todpr;
109
110 uint64_t pfault_token;
111 uint64_t pfault_compare;
112 uint64_t pfault_select;
113
114 uint64_t gbea;
115 uint64_t pp;
116
117
118 struct {} end_reset_fields;
119
120#if !defined(CONFIG_USER_ONLY)
121 uint32_t core_id;
122 uint64_t cpuid;
123#endif
124
125 QEMUTimer *tod_timer;
126
127 QEMUTimer *cpu_timer;
128
129
130
131
132
133
134
135
136
137 uint8_t cpu_state;
138
139
140 uint8_t sigp_order;
141
142};
143
144static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
145{
146 return &cs->vregs[nr][0];
147}
148
149
150
151
152
153
154
155struct S390CPU {
156
157 CPUState parent_obj;
158
159
160 CPUNegativeOffsetState neg;
161 CPUS390XState env;
162 S390CPUModel *model;
163
164 void *irqstate;
165 uint32_t irqstate_saved_size;
166};
167
168
169#ifndef CONFIG_USER_ONLY
170extern const VMStateDescription vmstate_s390_cpu;
171#endif
172
173
174#define HIGH_ORDER_BIT 0x80000000
175
176
177
178#define PGM_OPERATION 0x0001
179#define PGM_PRIVILEGED 0x0002
180#define PGM_EXECUTE 0x0003
181#define PGM_PROTECTION 0x0004
182#define PGM_ADDRESSING 0x0005
183#define PGM_SPECIFICATION 0x0006
184#define PGM_DATA 0x0007
185#define PGM_FIXPT_OVERFLOW 0x0008
186#define PGM_FIXPT_DIVIDE 0x0009
187#define PGM_DEC_OVERFLOW 0x000a
188#define PGM_DEC_DIVIDE 0x000b
189#define PGM_HFP_EXP_OVERFLOW 0x000c
190#define PGM_HFP_EXP_UNDERFLOW 0x000d
191#define PGM_HFP_SIGNIFICANCE 0x000e
192#define PGM_HFP_DIVIDE 0x000f
193#define PGM_SEGMENT_TRANS 0x0010
194#define PGM_PAGE_TRANS 0x0011
195#define PGM_TRANS_SPEC 0x0012
196#define PGM_SPECIAL_OP 0x0013
197#define PGM_OPERAND 0x0015
198#define PGM_TRACE_TABLE 0x0016
199#define PGM_VECTOR_PROCESSING 0x001b
200#define PGM_SPACE_SWITCH 0x001c
201#define PGM_HFP_SQRT 0x001d
202#define PGM_PC_TRANS_SPEC 0x001f
203#define PGM_AFX_TRANS 0x0020
204#define PGM_ASX_TRANS 0x0021
205#define PGM_LX_TRANS 0x0022
206#define PGM_EX_TRANS 0x0023
207#define PGM_PRIM_AUTH 0x0024
208#define PGM_SEC_AUTH 0x0025
209#define PGM_ALET_SPEC 0x0028
210#define PGM_ALEN_SPEC 0x0029
211#define PGM_ALE_SEQ 0x002a
212#define PGM_ASTE_VALID 0x002b
213#define PGM_ASTE_SEQ 0x002c
214#define PGM_EXT_AUTH 0x002d
215#define PGM_STACK_FULL 0x0030
216#define PGM_STACK_EMPTY 0x0031
217#define PGM_STACK_SPEC 0x0032
218#define PGM_STACK_TYPE 0x0033
219#define PGM_STACK_OP 0x0034
220#define PGM_ASCE_TYPE 0x0038
221#define PGM_REG_FIRST_TRANS 0x0039
222#define PGM_REG_SEC_TRANS 0x003a
223#define PGM_REG_THIRD_TRANS 0x003b
224#define PGM_MONITOR 0x0040
225#define PGM_PER 0x0080
226#define PGM_CRYPTO 0x0119
227
228
229#define EXT_INTERRUPT_KEY 0x0040
230#define EXT_CLOCK_COMP 0x1004
231#define EXT_CPU_TIMER 0x1005
232#define EXT_MALFUNCTION 0x1200
233#define EXT_EMERGENCY 0x1201
234#define EXT_EXTERNAL_CALL 0x1202
235#define EXT_ETR 0x1406
236#define EXT_SERVICE 0x2401
237#define EXT_VIRTIO 0x2603
238
239
240#undef PSW_MASK_PER
241#undef PSW_MASK_UNUSED_2
242#undef PSW_MASK_UNUSED_3
243#undef PSW_MASK_DAT
244#undef PSW_MASK_IO
245#undef PSW_MASK_EXT
246#undef PSW_MASK_KEY
247#undef PSW_SHIFT_KEY
248#undef PSW_MASK_MCHECK
249#undef PSW_MASK_WAIT
250#undef PSW_MASK_PSTATE
251#undef PSW_MASK_ASC
252#undef PSW_SHIFT_ASC
253#undef PSW_MASK_CC
254#undef PSW_MASK_PM
255#undef PSW_SHIFT_MASK_PM
256#undef PSW_MASK_64
257#undef PSW_MASK_32
258#undef PSW_MASK_ESA_ADDR
259
260#define PSW_MASK_PER 0x4000000000000000ULL
261#define PSW_MASK_UNUSED_2 0x2000000000000000ULL
262#define PSW_MASK_UNUSED_3 0x1000000000000000ULL
263#define PSW_MASK_DAT 0x0400000000000000ULL
264#define PSW_MASK_IO 0x0200000000000000ULL
265#define PSW_MASK_EXT 0x0100000000000000ULL
266#define PSW_MASK_KEY 0x00F0000000000000ULL
267#define PSW_SHIFT_KEY 52
268#define PSW_MASK_MCHECK 0x0004000000000000ULL
269#define PSW_MASK_WAIT 0x0002000000000000ULL
270#define PSW_MASK_PSTATE 0x0001000000000000ULL
271#define PSW_MASK_ASC 0x0000C00000000000ULL
272#define PSW_SHIFT_ASC 46
273#define PSW_MASK_CC 0x0000300000000000ULL
274#define PSW_MASK_PM 0x00000F0000000000ULL
275#define PSW_SHIFT_MASK_PM 40
276#define PSW_MASK_64 0x0000000100000000ULL
277#define PSW_MASK_32 0x0000000080000000ULL
278#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
279
280#undef PSW_ASC_PRIMARY
281#undef PSW_ASC_ACCREG
282#undef PSW_ASC_SECONDARY
283#undef PSW_ASC_HOME
284
285#define PSW_ASC_PRIMARY 0x0000000000000000ULL
286#define PSW_ASC_ACCREG 0x0000400000000000ULL
287#define PSW_ASC_SECONDARY 0x0000800000000000ULL
288#define PSW_ASC_HOME 0x0000C00000000000ULL
289
290
291#define AS_PRIMARY 0
292#define AS_ACCREG 1
293#define AS_SECONDARY 2
294#define AS_HOME 3
295
296
297
298#define FLAG_MASK_PSW_SHIFT 31
299#define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
300#define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT)
301#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
302#define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
303#define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
304#define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
305#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \
306 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
307
308
309#define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT)
310#define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT)
311
312
313#define CR0_LOWPROT 0x0000000010000000ULL
314#define CR0_SECONDARY 0x0000000004000000ULL
315#define CR0_EDAT 0x0000000000800000ULL
316#define CR0_AFP 0x0000000000040000ULL
317#define CR0_VECTOR 0x0000000000020000ULL
318#define CR0_IEP 0x0000000000100000ULL
319#define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
320#define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL
321#define CR0_CKC_SC 0x0000000000000800ULL
322#define CR0_CPU_TIMER_SC 0x0000000000000400ULL
323#define CR0_SERVICE_SC 0x0000000000000200ULL
324
325
326#define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL
327
328
329#define MMU_PRIMARY_IDX 0
330#define MMU_SECONDARY_IDX 1
331#define MMU_HOME_IDX 2
332#define MMU_REAL_IDX 3
333
334static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
335{
336#ifdef CONFIG_USER_ONLY
337 return MMU_USER_IDX;
338#else
339 if (!(env->psw.mask & PSW_MASK_DAT)) {
340 return MMU_REAL_IDX;
341 }
342
343 if (ifetch) {
344 if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) {
345 return MMU_HOME_IDX;
346 }
347 return MMU_PRIMARY_IDX;
348 }
349
350 switch (env->psw.mask & PSW_MASK_ASC) {
351 case PSW_ASC_PRIMARY:
352 return MMU_PRIMARY_IDX;
353 case PSW_ASC_SECONDARY:
354 return MMU_SECONDARY_IDX;
355 case PSW_ASC_HOME:
356 return MMU_HOME_IDX;
357 case PSW_ASC_ACCREG:
358
359 default:
360 abort();
361 }
362#endif
363}
364
365static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
366 target_ulong *cs_base, uint32_t *flags)
367{
368 *pc = env->psw.addr;
369 *cs_base = env->ex_value;
370 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
371 if (env->cregs[0] & CR0_AFP) {
372 *flags |= FLAG_MASK_AFP;
373 }
374 if (env->cregs[0] & CR0_VECTOR) {
375 *flags |= FLAG_MASK_VECTOR;
376 }
377}
378
379
380#define PER_CR9_EVENT_BRANCH 0x80000000
381#define PER_CR9_EVENT_IFETCH 0x40000000
382#define PER_CR9_EVENT_STORE 0x20000000
383#define PER_CR9_EVENT_STORE_REAL 0x08000000
384#define PER_CR9_EVENT_NULLIFICATION 0x01000000
385#define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
386#define PER_CR9_CONTROL_ALTERATION 0x00200000
387
388
389#define PER_CODE_EVENT_BRANCH 0x8000
390#define PER_CODE_EVENT_IFETCH 0x4000
391#define PER_CODE_EVENT_STORE 0x2000
392#define PER_CODE_EVENT_STORE_REAL 0x0800
393#define PER_CODE_EVENT_NULLIFICATION 0x0100
394
395#define EXCP_EXT 1
396#define EXCP_SVC 2
397#define EXCP_PGM 3
398#define EXCP_RESTART 4
399#define EXCP_STOP 5
400#define EXCP_IO 7
401#define EXCP_MCHK 8
402
403#define INTERRUPT_EXT_CPU_TIMER (1 << 3)
404#define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4)
405#define INTERRUPT_EXTERNAL_CALL (1 << 5)
406#define INTERRUPT_EMERGENCY_SIGNAL (1 << 6)
407#define INTERRUPT_RESTART (1 << 7)
408#define INTERRUPT_STOP (1 << 8)
409
410
411#define S390_PSWM_REGNUM 0
412#define S390_PSWA_REGNUM 1
413
414#define S390_R0_REGNUM 2
415#define S390_R1_REGNUM 3
416#define S390_R2_REGNUM 4
417#define S390_R3_REGNUM 5
418#define S390_R4_REGNUM 6
419#define S390_R5_REGNUM 7
420#define S390_R6_REGNUM 8
421#define S390_R7_REGNUM 9
422#define S390_R8_REGNUM 10
423#define S390_R9_REGNUM 11
424#define S390_R10_REGNUM 12
425#define S390_R11_REGNUM 13
426#define S390_R12_REGNUM 14
427#define S390_R13_REGNUM 15
428#define S390_R14_REGNUM 16
429#define S390_R15_REGNUM 17
430
431#define S390_NUM_CORE_REGS 18
432
433static inline void setcc(S390CPU *cpu, uint64_t cc)
434{
435 CPUS390XState *env = &cpu->env;
436
437 env->psw.mask &= ~(3ull << 44);
438 env->psw.mask |= (cc & 3) << 44;
439 env->cc_op = cc;
440}
441
442
443#define STSI_R0_FC_MASK 0x00000000f0000000ULL
444#define STSI_R0_FC_CURRENT 0x0000000000000000ULL
445#define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL
446#define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL
447#define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL
448#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
449#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
450#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
451#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
452
453
454typedef struct SysIB_111 {
455 uint8_t res1[32];
456 uint8_t manuf[16];
457 uint8_t type[4];
458 uint8_t res2[12];
459 uint8_t model[16];
460 uint8_t sequence[16];
461 uint8_t plant[4];
462 uint8_t res3[3996];
463} SysIB_111;
464QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096);
465
466
467typedef struct SysIB_121 {
468 uint8_t res1[80];
469 uint8_t sequence[16];
470 uint8_t plant[4];
471 uint8_t res2[2];
472 uint16_t cpu_addr;
473 uint8_t res3[3992];
474} SysIB_121;
475QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096);
476
477
478typedef struct SysIB_122 {
479 uint8_t res1[32];
480 uint32_t capability;
481 uint16_t total_cpus;
482 uint16_t conf_cpus;
483 uint16_t standby_cpus;
484 uint16_t reserved_cpus;
485 uint16_t adjustments[2026];
486} SysIB_122;
487QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096);
488
489
490typedef struct SysIB_221 {
491 uint8_t res1[80];
492 uint8_t sequence[16];
493 uint8_t plant[4];
494 uint16_t cpu_id;
495 uint16_t cpu_addr;
496 uint8_t res3[3992];
497} SysIB_221;
498QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096);
499
500
501typedef struct SysIB_222 {
502 uint8_t res1[32];
503 uint16_t lpar_num;
504 uint8_t res2;
505 uint8_t lcpuc;
506 uint16_t total_cpus;
507 uint16_t conf_cpus;
508 uint16_t standby_cpus;
509 uint16_t reserved_cpus;
510 uint8_t name[8];
511 uint32_t caf;
512 uint8_t res3[16];
513 uint16_t dedicated_cpus;
514 uint16_t shared_cpus;
515 uint8_t res4[4020];
516} SysIB_222;
517QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096);
518
519
520typedef struct SysIB_322 {
521 uint8_t res1[31];
522 uint8_t count;
523 struct {
524 uint8_t res2[4];
525 uint16_t total_cpus;
526 uint16_t conf_cpus;
527 uint16_t standby_cpus;
528 uint16_t reserved_cpus;
529 uint8_t name[8];
530 uint32_t caf;
531 uint8_t cpi[16];
532 uint8_t res5[3];
533 uint8_t ext_name_encoding;
534 uint32_t res3;
535 uint8_t uuid[16];
536 } vm[8];
537 uint8_t res4[1504];
538 uint8_t ext_names[8][256];
539} SysIB_322;
540QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096);
541
542typedef union SysIB {
543 SysIB_111 sysib_111;
544 SysIB_121 sysib_121;
545 SysIB_122 sysib_122;
546 SysIB_221 sysib_221;
547 SysIB_222 sysib_222;
548 SysIB_322 sysib_322;
549} SysIB;
550QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096);
551
552
553#define ASCE_ORIGIN (~0xfffULL)
554#define ASCE_SUBSPACE 0x200
555#define ASCE_PRIVATE_SPACE 0x100
556#define ASCE_ALT_EVENT 0x80
557#define ASCE_SPACE_SWITCH 0x40
558#define ASCE_REAL_SPACE 0x20
559#define ASCE_TYPE_MASK 0x0c
560#define ASCE_TYPE_REGION1 0x0c
561#define ASCE_TYPE_REGION2 0x08
562#define ASCE_TYPE_REGION3 0x04
563#define ASCE_TYPE_SEGMENT 0x00
564#define ASCE_TABLE_LENGTH 0x03
565
566#define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL
567#define REGION_ENTRY_P 0x0000000000000200ULL
568#define REGION_ENTRY_TF 0x00000000000000c0ULL
569#define REGION_ENTRY_I 0x0000000000000020ULL
570#define REGION_ENTRY_TT 0x000000000000000cULL
571#define REGION_ENTRY_TL 0x0000000000000003ULL
572
573#define REGION_ENTRY_TT_REGION1 0x000000000000000cULL
574#define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL
575#define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL
576
577#define REGION3_ENTRY_RFAA 0xffffffff80000000ULL
578#define REGION3_ENTRY_AV 0x0000000000010000ULL
579#define REGION3_ENTRY_ACC 0x000000000000f000ULL
580#define REGION3_ENTRY_F 0x0000000000000800ULL
581#define REGION3_ENTRY_FC 0x0000000000000400ULL
582#define REGION3_ENTRY_IEP 0x0000000000000100ULL
583#define REGION3_ENTRY_CR 0x0000000000000010ULL
584
585#define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL
586#define SEGMENT_ENTRY_SFAA 0xfffffffffff00000ULL
587#define SEGMENT_ENTRY_AV 0x0000000000010000ULL
588#define SEGMENT_ENTRY_ACC 0x000000000000f000ULL
589#define SEGMENT_ENTRY_F 0x0000000000000800ULL
590#define SEGMENT_ENTRY_FC 0x0000000000000400ULL
591#define SEGMENT_ENTRY_P 0x0000000000000200ULL
592#define SEGMENT_ENTRY_IEP 0x0000000000000100ULL
593#define SEGMENT_ENTRY_I 0x0000000000000020ULL
594#define SEGMENT_ENTRY_CS 0x0000000000000010ULL
595#define SEGMENT_ENTRY_TT 0x000000000000000cULL
596
597#define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL
598
599#define PAGE_ENTRY_0 0x0000000000000800ULL
600#define PAGE_ENTRY_I 0x0000000000000400ULL
601#define PAGE_ENTRY_P 0x0000000000000200ULL
602#define PAGE_ENTRY_IEP 0x0000000000000100ULL
603
604#define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL
605#define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL
606#define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL
607#define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL
608#define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL
609
610#define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> 53)
611#define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> 42)
612#define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> 31)
613#define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20)
614#define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12)
615
616#define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> 62)
617#define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> 51)
618#define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> 40)
619#define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> 29)
620
621#define SK_C (0x1 << 1)
622#define SK_R (0x1 << 2)
623#define SK_F (0x1 << 3)
624#define SK_ACC_MASK (0xf << 4)
625
626
627#define SIGP_SENSE 0x01
628#define SIGP_EXTERNAL_CALL 0x02
629#define SIGP_EMERGENCY 0x03
630#define SIGP_START 0x04
631#define SIGP_STOP 0x05
632#define SIGP_RESTART 0x06
633#define SIGP_STOP_STORE_STATUS 0x09
634#define SIGP_INITIAL_CPU_RESET 0x0b
635#define SIGP_CPU_RESET 0x0c
636#define SIGP_SET_PREFIX 0x0d
637#define SIGP_STORE_STATUS_ADDR 0x0e
638#define SIGP_SET_ARCH 0x12
639#define SIGP_COND_EMERGENCY 0x13
640#define SIGP_SENSE_RUNNING 0x15
641#define SIGP_STORE_ADTL_STATUS 0x17
642
643
644#define SIGP_CC_ORDER_CODE_ACCEPTED 0
645#define SIGP_CC_STATUS_STORED 1
646#define SIGP_CC_BUSY 2
647#define SIGP_CC_NOT_OPERATIONAL 3
648
649
650#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
651#define SIGP_STAT_NOT_RUNNING 0x00000400UL
652#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
653#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
654#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
655#define SIGP_STAT_STOPPED 0x00000040UL
656#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
657#define SIGP_STAT_CHECK_STOP 0x00000010UL
658#define SIGP_STAT_INOPERATIVE 0x00000004UL
659#define SIGP_STAT_INVALID_ORDER 0x00000002UL
660#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
661
662
663#define SIGP_MODE_ESA_S390 0
664#define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
665#define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
666
667
668#define SIGP_ORDER_MASK 0x000000ff
669
670
671
672
673#define MCIC_SC_SD 0x8000000000000000ULL
674#define MCIC_SC_PD 0x4000000000000000ULL
675#define MCIC_SC_SR 0x2000000000000000ULL
676#define MCIC_SC_CD 0x0800000000000000ULL
677#define MCIC_SC_ED 0x0400000000000000ULL
678#define MCIC_SC_DG 0x0100000000000000ULL
679#define MCIC_SC_W 0x0080000000000000ULL
680#define MCIC_SC_CP 0x0040000000000000ULL
681#define MCIC_SC_SP 0x0020000000000000ULL
682#define MCIC_SC_CK 0x0010000000000000ULL
683
684
685#define MCIC_SCM_B 0x0002000000000000ULL
686#define MCIC_SCM_DA 0x0000000020000000ULL
687#define MCIC_SCM_AP 0x0000000000080000ULL
688
689
690#define MCIC_SE_SE 0x0000800000000000ULL
691#define MCIC_SE_SC 0x0000400000000000ULL
692#define MCIC_SE_KE 0x0000200000000000ULL
693#define MCIC_SE_DS 0x0000100000000000ULL
694#define MCIC_SE_IE 0x0000000080000000ULL
695
696
697#define MCIC_VB_WP 0x0000080000000000ULL
698#define MCIC_VB_MS 0x0000040000000000ULL
699#define MCIC_VB_PM 0x0000020000000000ULL
700#define MCIC_VB_IA 0x0000010000000000ULL
701#define MCIC_VB_FA 0x0000008000000000ULL
702#define MCIC_VB_VR 0x0000004000000000ULL
703#define MCIC_VB_EC 0x0000002000000000ULL
704#define MCIC_VB_FP 0x0000001000000000ULL
705#define MCIC_VB_GR 0x0000000800000000ULL
706#define MCIC_VB_CR 0x0000000400000000ULL
707#define MCIC_VB_ST 0x0000000100000000ULL
708#define MCIC_VB_AR 0x0000000040000000ULL
709#define MCIC_VB_GS 0x0000000008000000ULL
710#define MCIC_VB_PR 0x0000000000200000ULL
711#define MCIC_VB_FC 0x0000000000100000ULL
712#define MCIC_VB_CT 0x0000000000020000ULL
713#define MCIC_VB_CC 0x0000000000010000ULL
714
715static inline uint64_t s390_build_validity_mcic(void)
716{
717 uint64_t mcic;
718
719
720
721
722
723 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP |
724 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR |
725 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC;
726 if (s390_has_feat(S390_FEAT_VECTOR)) {
727 mcic |= MCIC_VB_VR;
728 }
729 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) {
730 mcic |= MCIC_VB_GS;
731 }
732 return mcic;
733}
734
735static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg)
736{
737 cpu_reset(cs);
738}
739
740static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg)
741{
742 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
743
744 scc->cpu_reset(cs);
745}
746
747static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg)
748{
749 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
750
751 scc->initial_cpu_reset(cs);
752}
753
754static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg)
755{
756 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
757
758 scc->load_normal(cs);
759}
760
761
762
763void s390_crypto_reset(void);
764int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit);
765void s390_set_max_pagesize(uint64_t pagesize, Error **errp);
766void s390_cmma_reset(void);
767void s390_enable_css_support(S390CPU *cpu);
768int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
769 int vq, bool assign);
770#ifndef CONFIG_USER_ONLY
771unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
772#else
773static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
774{
775 return 0;
776}
777#endif
778static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
779{
780 return cpu->env.cpu_state;
781}
782
783
784
785void s390_cpu_list(void);
786#define cpu_list s390_cpu_list
787void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
788 const S390FeatInit feat_init);
789
790
791
792#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
793#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
794#define CPU_RESOLVING_TYPE TYPE_S390_CPU
795
796
797
798
799int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc);
800#define cpu_signal_handler cpu_s390x_signal_handler
801
802
803
804void s390_crw_mchk(void);
805void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
806 uint32_t io_int_parm, uint32_t io_int_word);
807#define RA_IGNORED 0
808void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra);
809
810void s390_sclp_extint(uint32_t parm);
811
812
813int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
814 int len, bool is_write);
815#define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
816 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
817#define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
818 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
819#define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \
820 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
821#define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
822 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
823void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra);
824
825
826
827int s390_cpu_restart(S390CPU *cpu);
828void s390_init_sigp(void);
829
830
831
832S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
833
834typedef CPUS390XState CPUArchState;
835typedef S390CPU ArchCPU;
836
837#include "exec/cpu-all.h"
838
839#endif
840