1#ifndef SPARC_CPU_H
2#define SPARC_CPU_H
3
4#include "qemu/bswap.h"
5#include "cpu-qom.h"
6#include "exec/cpu-defs.h"
7
8#if !defined(TARGET_SPARC64)
9#define TARGET_DPREGS 16
10#else
11#define TARGET_DPREGS 32
12#endif
13
14
15
16
17enum {
18 WREG_O0,
19 WREG_O1,
20 WREG_O2,
21 WREG_O3,
22 WREG_O4,
23 WREG_O5,
24 WREG_O6,
25 WREG_O7,
26
27 WREG_L0,
28 WREG_L1,
29 WREG_L2,
30 WREG_L3,
31 WREG_L4,
32 WREG_L5,
33 WREG_L6,
34 WREG_L7,
35
36 WREG_I0,
37 WREG_I1,
38 WREG_I2,
39 WREG_I3,
40 WREG_I4,
41 WREG_I5,
42 WREG_I6,
43 WREG_I7,
44
45 WREG_SP = WREG_O6,
46 WREG_FP = WREG_I6,
47};
48
49
50#ifndef TARGET_SPARC64
51#define TT_TFAULT 0x01
52#define TT_ILL_INSN 0x02
53#define TT_PRIV_INSN 0x03
54#define TT_NFPU_INSN 0x04
55#define TT_WIN_OVF 0x05
56#define TT_WIN_UNF 0x06
57#define TT_UNALIGNED 0x07
58#define TT_FP_EXCP 0x08
59#define TT_DFAULT 0x09
60#define TT_TOVF 0x0a
61#define TT_EXTINT 0x10
62#define TT_CODE_ACCESS 0x21
63#define TT_UNIMP_FLUSH 0x25
64#define TT_DATA_ACCESS 0x29
65#define TT_DIV_ZERO 0x2a
66#define TT_NCP_INSN 0x24
67#define TT_TRAP 0x80
68#else
69#define TT_POWER_ON_RESET 0x01
70#define TT_TFAULT 0x08
71#define TT_CODE_ACCESS 0x0a
72#define TT_ILL_INSN 0x10
73#define TT_UNIMP_FLUSH TT_ILL_INSN
74#define TT_PRIV_INSN 0x11
75#define TT_NFPU_INSN 0x20
76#define TT_FP_EXCP 0x21
77#define TT_TOVF 0x23
78#define TT_CLRWIN 0x24
79#define TT_DIV_ZERO 0x28
80#define TT_DFAULT 0x30
81#define TT_DATA_ACCESS 0x32
82#define TT_UNALIGNED 0x34
83#define TT_PRIV_ACT 0x37
84#define TT_INSN_REAL_TRANSLATION_MISS 0x3e
85#define TT_DATA_REAL_TRANSLATION_MISS 0x3f
86#define TT_EXTINT 0x40
87#define TT_IVEC 0x60
88#define TT_TMISS 0x64
89#define TT_DMISS 0x68
90#define TT_DPROT 0x6c
91#define TT_SPILL 0x80
92#define TT_FILL 0xc0
93#define TT_WOTHER (1 << 5)
94#define TT_TRAP 0x100
95#define TT_HTRAP 0x180
96#endif
97
98#define PSR_NEG_SHIFT 23
99#define PSR_NEG (1 << PSR_NEG_SHIFT)
100#define PSR_ZERO_SHIFT 22
101#define PSR_ZERO (1 << PSR_ZERO_SHIFT)
102#define PSR_OVF_SHIFT 21
103#define PSR_OVF (1 << PSR_OVF_SHIFT)
104#define PSR_CARRY_SHIFT 20
105#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
106#define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
107#if !defined(TARGET_SPARC64)
108#define PSR_EF (1<<12)
109#define PSR_PIL 0xf00
110#define PSR_S (1<<7)
111#define PSR_PS (1<<6)
112#define PSR_ET (1<<5)
113#define PSR_CWP 0x1f
114#endif
115
116#define CC_SRC (env->cc_src)
117#define CC_SRC2 (env->cc_src2)
118#define CC_DST (env->cc_dst)
119#define CC_OP (env->cc_op)
120
121
122
123
124
125
126enum {
127 CC_OP_DYNAMIC,
128 CC_OP_FLAGS,
129 CC_OP_DIV,
130 CC_OP_ADD,
131 CC_OP_ADDX,
132 CC_OP_TADD,
133 CC_OP_TADDTV,
134 CC_OP_SUB,
135 CC_OP_SUBX,
136 CC_OP_TSUB,
137 CC_OP_TSUBTV,
138 CC_OP_LOGIC,
139 CC_OP_NB,
140};
141
142
143#define TBR_BASE_MASK 0xfffff000
144
145#if defined(TARGET_SPARC64)
146#define PS_TCT (1<<12)
147#define PS_IG (1<<11)
148#define PS_MG (1<<10)
149#define PS_CLE (1<<9)
150#define PS_TLE (1<<8)
151#define PS_RMO (1<<7)
152#define PS_RED (1<<5)
153#define PS_PEF (1<<4)
154#define PS_AM (1<<3)
155#define PS_PRIV (1<<2)
156#define PS_IE (1<<1)
157#define PS_AG (1<<0)
158
159#define FPRS_FEF (1<<2)
160
161#define HS_PRIV (1<<2)
162#endif
163
164
165#define FSR_RD1 (1ULL << 31)
166#define FSR_RD0 (1ULL << 30)
167#define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
168#define FSR_RD_NEAREST 0
169#define FSR_RD_ZERO FSR_RD0
170#define FSR_RD_POS FSR_RD1
171#define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
172
173#define FSR_NVM (1ULL << 27)
174#define FSR_OFM (1ULL << 26)
175#define FSR_UFM (1ULL << 25)
176#define FSR_DZM (1ULL << 24)
177#define FSR_NXM (1ULL << 23)
178#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
179
180#define FSR_NVA (1ULL << 9)
181#define FSR_OFA (1ULL << 8)
182#define FSR_UFA (1ULL << 7)
183#define FSR_DZA (1ULL << 6)
184#define FSR_NXA (1ULL << 5)
185#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
186
187#define FSR_NVC (1ULL << 4)
188#define FSR_OFC (1ULL << 3)
189#define FSR_UFC (1ULL << 2)
190#define FSR_DZC (1ULL << 1)
191#define FSR_NXC (1ULL << 0)
192#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
193
194#define FSR_FTT2 (1ULL << 16)
195#define FSR_FTT1 (1ULL << 15)
196#define FSR_FTT0 (1ULL << 14)
197
198
199#ifdef TARGET_SPARC64
200#define FSR_FTT_NMASK 0xfffffffffffe3fffULL
201#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
202#define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL
203#define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL
204#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
205#else
206#define FSR_FTT_NMASK 0xfffe3fffULL
207#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
208#define FSR_LDFSR_OLDMASK 0x000fc000ULL
209#endif
210#define FSR_LDFSR_MASK 0xcfc00fffULL
211#define FSR_FTT_IEEE_EXCP (1ULL << 14)
212#define FSR_FTT_UNIMPFPOP (3ULL << 14)
213#define FSR_FTT_SEQ_ERROR (4ULL << 14)
214#define FSR_FTT_INVAL_FPR (6ULL << 14)
215
216#define FSR_FCC1_SHIFT 11
217#define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT)
218#define FSR_FCC0_SHIFT 10
219#define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT)
220
221
222#define MMU_E (1<<0)
223#define MMU_NF (1<<1)
224
225#define PTE_ENTRYTYPE_MASK 3
226#define PTE_ACCESS_MASK 0x1c
227#define PTE_ACCESS_SHIFT 2
228#define PTE_PPN_SHIFT 7
229#define PTE_ADDR_MASK 0xffffff00
230
231#define PG_ACCESSED_BIT 5
232#define PG_MODIFIED_BIT 6
233#define PG_CACHE_BIT 7
234
235#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
236#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
237#define PG_CACHE_MASK (1 << PG_CACHE_BIT)
238
239
240#define MIN_NWINDOWS 3
241#define MAX_NWINDOWS 32
242
243#ifdef TARGET_SPARC64
244typedef struct trap_state {
245 uint64_t tpc;
246 uint64_t tnpc;
247 uint64_t tstate;
248 uint32_t tt;
249} trap_state;
250#endif
251#define TARGET_INSN_START_EXTRA_WORDS 1
252
253struct sparc_def_t {
254 const char *name;
255 target_ulong iu_version;
256 uint32_t fpu_version;
257 uint32_t mmu_version;
258 uint32_t mmu_bm;
259 uint32_t mmu_ctpr_mask;
260 uint32_t mmu_cxr_mask;
261 uint32_t mmu_sfsr_mask;
262 uint32_t mmu_trcr_mask;
263 uint32_t mxcc_version;
264 uint32_t features;
265 uint32_t nwindows;
266 uint32_t maxtl;
267};
268
269#define CPU_FEATURE_FLOAT (1 << 0)
270#define CPU_FEATURE_FLOAT128 (1 << 1)
271#define CPU_FEATURE_SWAP (1 << 2)
272#define CPU_FEATURE_MUL (1 << 3)
273#define CPU_FEATURE_DIV (1 << 4)
274#define CPU_FEATURE_FLUSH (1 << 5)
275#define CPU_FEATURE_FSQRT (1 << 6)
276#define CPU_FEATURE_FMUL (1 << 7)
277#define CPU_FEATURE_VIS1 (1 << 8)
278#define CPU_FEATURE_VIS2 (1 << 9)
279#define CPU_FEATURE_FSMULD (1 << 10)
280#define CPU_FEATURE_HYPV (1 << 11)
281#define CPU_FEATURE_CMT (1 << 12)
282#define CPU_FEATURE_GL (1 << 13)
283#define CPU_FEATURE_TA0_SHUTDOWN (1 << 14)
284#define CPU_FEATURE_ASR17 (1 << 15)
285#define CPU_FEATURE_CACHE_CTRL (1 << 16)
286#define CPU_FEATURE_POWERDOWN (1 << 17)
287#define CPU_FEATURE_CASA (1 << 18)
288
289#ifndef TARGET_SPARC64
290#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
291 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
292 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
293 CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
294#else
295#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
296 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
297 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
298 CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
299 CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \
300 CPU_FEATURE_CASA)
301enum {
302 mmu_us_12,
303 mmu_us_3,
304 mmu_us_4,
305 mmu_sun4v,
306};
307#endif
308
309#define TTE_VALID_BIT (1ULL << 63)
310#define TTE_NFO_BIT (1ULL << 60)
311#define TTE_IE_BIT (1ULL << 59)
312#define TTE_USED_BIT (1ULL << 41)
313#define TTE_LOCKED_BIT (1ULL << 6)
314#define TTE_SIDEEFFECT_BIT (1ULL << 3)
315#define TTE_PRIV_BIT (1ULL << 2)
316#define TTE_W_OK_BIT (1ULL << 1)
317#define TTE_GLOBAL_BIT (1ULL << 0)
318
319#define TTE_NFO_BIT_UA2005 (1ULL << 62)
320#define TTE_USED_BIT_UA2005 (1ULL << 47)
321#define TTE_LOCKED_BIT_UA2005 (1ULL << 61)
322#define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11)
323#define TTE_PRIV_BIT_UA2005 (1ULL << 8)
324#define TTE_W_OK_BIT_UA2005 (1ULL << 6)
325
326#define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
327#define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT)
328#define TTE_IS_IE(tte) ((tte) & TTE_IE_BIT)
329#define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
330#define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
331#define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
332#define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005)
333#define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT)
334#define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT)
335
336#define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005)
337#define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005)
338#define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005)
339#define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005)
340#define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005)
341#define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005)
342
343#define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
344
345#define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT)
346#define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
347
348#define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL)
349#define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL)
350#define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL)
351
352
353#define TLB_UST1_IS_REAL_BIT (1ULL << 9)
354#define TLB_UST1_IS_SUN4V_BIT (1ULL << 10)
355
356#define SFSR_NF_BIT (1ULL << 24)
357#define SFSR_TM_BIT (1ULL << 15)
358#define SFSR_FT_VA_IMMU_BIT (1ULL << 13)
359#define SFSR_FT_VA_DMMU_BIT (1ULL << 12)
360#define SFSR_FT_NFO_BIT (1ULL << 11)
361#define SFSR_FT_ILL_BIT (1ULL << 10)
362#define SFSR_FT_ATOMIC_BIT (1ULL << 9)
363#define SFSR_FT_NF_E_BIT (1ULL << 8)
364#define SFSR_FT_PRIV_BIT (1ULL << 7)
365#define SFSR_PR_BIT (1ULL << 3)
366#define SFSR_WRITE_BIT (1ULL << 2)
367#define SFSR_OW_BIT (1ULL << 1)
368#define SFSR_VALID_BIT (1ULL << 0)
369
370#define SFSR_ASI_SHIFT 16
371#define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT)
372#define SFSR_CT_PRIMARY (0ULL << 4)
373#define SFSR_CT_SECONDARY (1ULL << 4)
374#define SFSR_CT_NUCLEUS (2ULL << 4)
375#define SFSR_CT_NOTRANS (3ULL << 4)
376#define SFSR_CT_MASK (3ULL << 4)
377
378
379
380
381
382
383#define CACHE_STATE_MASK 0x3
384#define CACHE_DISABLED 0x0
385#define CACHE_FROZEN 0x1
386#define CACHE_ENABLED 0x3
387
388
389
390#define CACHE_CTRL_IF (1 << 4)
391#define CACHE_CTRL_DF (1 << 5)
392#define CACHE_CTRL_DP (1 << 14)
393#define CACHE_CTRL_IP (1 << 15)
394#define CACHE_CTRL_IB (1 << 16)
395#define CACHE_CTRL_FI (1 << 21)
396#define CACHE_CTRL_FD (1 << 22)
397#define CACHE_CTRL_DS (1 << 23)
398
399#define CONVERT_BIT(X, SRC, DST) \
400 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
401
402typedef struct SparcTLBEntry {
403 uint64_t tag;
404 uint64_t tte;
405} SparcTLBEntry;
406
407struct CPUTimer
408{
409 const char *name;
410 uint32_t frequency;
411 uint32_t disabled;
412 uint64_t disabled_mask;
413 uint32_t npt;
414 uint64_t npt_mask;
415 int64_t clock_offset;
416 QEMUTimer *qtimer;
417};
418
419typedef struct CPUTimer CPUTimer;
420
421typedef struct CPUSPARCState CPUSPARCState;
422#if defined(TARGET_SPARC64)
423typedef union {
424 uint64_t mmuregs[16];
425 struct {
426 uint64_t tsb_tag_target;
427 uint64_t mmu_primary_context;
428 uint64_t mmu_secondary_context;
429 uint64_t sfsr;
430 uint64_t sfar;
431 uint64_t tsb;
432 uint64_t tag_access;
433 uint64_t virtual_watchpoint;
434 uint64_t physical_watchpoint;
435 uint64_t sun4v_ctx_config[2];
436 uint64_t sun4v_tsb_pointers[4];
437 };
438} SparcV9MMU;
439#endif
440struct CPUSPARCState {
441 target_ulong gregs[8];
442 target_ulong *regwptr;
443 target_ulong pc;
444 target_ulong npc;
445 target_ulong y;
446
447
448 target_ulong cc_src, cc_src2;
449 target_ulong cc_dst;
450 uint32_t cc_op;
451
452 target_ulong cond;
453
454
455 uint32_t psr;
456 target_ulong fsr;
457 CPU_DoubleU fpr[TARGET_DPREGS];
458 uint32_t cwp;
459
460#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
461 uint32_t wim;
462#endif
463 target_ulong tbr;
464#if !defined(TARGET_SPARC64)
465 int psrs;
466 int psrps;
467 int psret;
468#endif
469 uint32_t psrpil;
470 uint32_t pil_in;
471#if !defined(TARGET_SPARC64)
472 int psref;
473#endif
474 int interrupt_index;
475
476 target_ulong regbase[MAX_NWINDOWS * 16 + 8];
477
478
479 struct {} end_reset_fields;
480
481
482 target_ulong version;
483 uint32_t nwindows;
484
485
486#if defined(TARGET_SPARC64)
487 uint64_t lsu;
488#define DMMU_E 0x8
489#define IMMU_E 0x4
490 SparcV9MMU immu;
491 SparcV9MMU dmmu;
492 SparcTLBEntry itlb[64];
493 SparcTLBEntry dtlb[64];
494 uint32_t mmu_version;
495#else
496 uint32_t mmuregs[32];
497 uint64_t mxccdata[4];
498 uint64_t mxccregs[8];
499 uint32_t mmubpctrv, mmubpctrc, mmubpctrs;
500 uint64_t mmubpaction;
501 uint64_t mmubpregs[4];
502 uint64_t prom_addr;
503#endif
504
505 float128 qt0, qt1;
506 float_status fp_status;
507#if defined(TARGET_SPARC64)
508#define MAXTL_MAX 8
509#define MAXTL_MASK (MAXTL_MAX - 1)
510 trap_state ts[MAXTL_MAX];
511 uint32_t xcc;
512 uint32_t asi;
513 uint32_t pstate;
514 uint32_t tl;
515 uint32_t maxtl;
516 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
517 uint64_t agregs[8];
518 uint64_t bgregs[8];
519 uint64_t igregs[8];
520 uint64_t mgregs[8];
521 uint64_t glregs[8 * MAXTL_MAX];
522 uint64_t fprs;
523 uint64_t tick_cmpr, stick_cmpr;
524 CPUTimer *tick, *stick;
525#define TICK_NPT_MASK 0x8000000000000000ULL
526#define TICK_INT_DIS 0x8000000000000000ULL
527 uint64_t gsr;
528 uint32_t gl;
529
530 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
531 uint64_t scratch[8];
532 CPUTimer *hstick;
533
534 uint64_t ivec_status;
535 uint64_t ivec_data[3];
536 uint32_t softint;
537#define SOFTINT_TIMER 1
538#define SOFTINT_STIMER (1 << 16)
539#define SOFTINT_INTRMASK (0xFFFE)
540#define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
541#endif
542 sparc_def_t def;
543
544 void *irq_manager;
545 void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno);
546
547
548 uint32_t cache_control;
549};
550
551
552
553
554
555
556
557struct SPARCCPU {
558
559 CPUState parent_obj;
560
561
562 CPUNegativeOffsetState neg;
563 CPUSPARCState env;
564};
565
566
567#ifndef CONFIG_USER_ONLY
568extern const VMStateDescription vmstate_sparc_cpu;
569#endif
570
571void sparc_cpu_do_interrupt(CPUState *cpu);
572void sparc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
573hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
574int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
575int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
576void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
577 MMUAccessType access_type,
578 int mmu_idx,
579 uintptr_t retaddr);
580void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN;
581
582#ifndef NO_CPU_IO_DEFS
583
584void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
585void sparc_cpu_list(void);
586
587bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
588 MMUAccessType access_type, int mmu_idx,
589 bool probe, uintptr_t retaddr);
590target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
591void dump_mmu(CPUSPARCState *env);
592
593#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
594int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
595 uint8_t *buf, int len, bool is_write);
596#endif
597
598
599
600void sparc_tcg_init(void);
601
602
603
604
605target_ulong cpu_get_psr(CPUSPARCState *env1);
606void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
607void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val);
608#ifdef TARGET_SPARC64
609target_ulong cpu_get_ccr(CPUSPARCState *env1);
610void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
611target_ulong cpu_get_cwp64(CPUSPARCState *env1);
612void cpu_put_cwp64(CPUSPARCState *env1, int cwp);
613void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate);
614void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl);
615#endif
616int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
617int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
618void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
619
620
621void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno);
622
623
624void cpu_check_irqs(CPUSPARCState *env);
625
626
627void leon3_irq_ack(void *irq_manager, int intno);
628
629#if defined (TARGET_SPARC64)
630
631static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
632{
633 return (x & mask) == (y & mask);
634}
635
636#define MMU_CONTEXT_BITS 13
637#define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
638
639static inline int tlb_compare_context(const SparcTLBEntry *tlb,
640 uint64_t context)
641{
642 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
643}
644
645#endif
646#endif
647
648
649#if !defined(CONFIG_USER_ONLY)
650void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
651 vaddr addr, unsigned size,
652 MMUAccessType access_type,
653 int mmu_idx, MemTxAttrs attrs,
654 MemTxResult response, uintptr_t retaddr);
655#if defined(TARGET_SPARC64)
656hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
657 int mmu_idx);
658#endif
659#endif
660int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
661
662#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
663#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
664#define CPU_RESOLVING_TYPE TYPE_SPARC_CPU
665
666#define cpu_signal_handler cpu_sparc_signal_handler
667#define cpu_list sparc_cpu_list
668
669
670#if defined (TARGET_SPARC64)
671#define MMU_USER_IDX 0
672#define MMU_USER_SECONDARY_IDX 1
673#define MMU_KERNEL_IDX 2
674#define MMU_KERNEL_SECONDARY_IDX 3
675#define MMU_NUCLEUS_IDX 4
676#define MMU_PHYS_IDX 5
677#else
678#define MMU_USER_IDX 0
679#define MMU_KERNEL_IDX 1
680#define MMU_PHYS_IDX 2
681#endif
682
683#if defined (TARGET_SPARC64)
684static inline int cpu_has_hypervisor(CPUSPARCState *env1)
685{
686 return env1->def.features & CPU_FEATURE_HYPV;
687}
688
689static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
690{
691 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
692}
693
694static inline int cpu_supervisor_mode(CPUSPARCState *env1)
695{
696 return env1->pstate & PS_PRIV;
697}
698#else
699static inline int cpu_supervisor_mode(CPUSPARCState *env1)
700{
701 return env1->psrs;
702}
703#endif
704
705static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
706{
707#if defined(CONFIG_USER_ONLY)
708 return MMU_USER_IDX;
709#elif !defined(TARGET_SPARC64)
710 if ((env->mmuregs[0] & MMU_E) == 0) {
711 return MMU_PHYS_IDX;
712 } else {
713 return env->psrs;
714 }
715#else
716
717 if (ifetch
718 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
719 : (env->lsu & DMMU_E) == 0) {
720 return MMU_PHYS_IDX;
721 } else if (cpu_hypervisor_mode(env)) {
722 return MMU_PHYS_IDX;
723 } else if (env->tl > 0) {
724 return MMU_NUCLEUS_IDX;
725 } else if (cpu_supervisor_mode(env)) {
726 return MMU_KERNEL_IDX;
727 } else {
728 return MMU_USER_IDX;
729 }
730#endif
731}
732
733static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
734{
735#if !defined (TARGET_SPARC64)
736 if (env1->psret != 0)
737 return 1;
738#else
739 if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) {
740 return 1;
741 }
742#endif
743
744 return 0;
745}
746
747static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
748{
749#if !defined(TARGET_SPARC64)
750
751 return pil == 15 || pil > env1->psrpil;
752#else
753 return pil > env1->psrpil;
754#endif
755}
756
757typedef CPUSPARCState CPUArchState;
758typedef SPARCCPU ArchCPU;
759
760#include "exec/cpu-all.h"
761
762#ifdef TARGET_SPARC64
763
764void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
765uint64_t cpu_tick_get_count(CPUTimer *timer);
766void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
767trap_state* cpu_tsptr(CPUSPARCState* env);
768#endif
769
770#define TB_FLAG_MMU_MASK 7
771#define TB_FLAG_FPU_ENABLED (1 << 4)
772#define TB_FLAG_AM_ENABLED (1 << 5)
773#define TB_FLAG_SUPER (1 << 6)
774#define TB_FLAG_HYPER (1 << 7)
775#define TB_FLAG_ASI_SHIFT 24
776
777static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
778 target_ulong *cs_base, uint32_t *pflags)
779{
780 uint32_t flags;
781 *pc = env->pc;
782 *cs_base = env->npc;
783 flags = cpu_mmu_index(env, false);
784#ifndef CONFIG_USER_ONLY
785 if (cpu_supervisor_mode(env)) {
786 flags |= TB_FLAG_SUPER;
787 }
788#endif
789#ifdef TARGET_SPARC64
790#ifndef CONFIG_USER_ONLY
791 if (cpu_hypervisor_mode(env)) {
792 flags |= TB_FLAG_HYPER;
793 }
794#endif
795 if (env->pstate & PS_AM) {
796 flags |= TB_FLAG_AM_ENABLED;
797 }
798 if ((env->def.features & CPU_FEATURE_FLOAT)
799 && (env->pstate & PS_PEF)
800 && (env->fprs & FPRS_FEF)) {
801 flags |= TB_FLAG_FPU_ENABLED;
802 }
803 flags |= env->asi << TB_FLAG_ASI_SHIFT;
804#else
805 if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) {
806 flags |= TB_FLAG_FPU_ENABLED;
807 }
808#endif
809 *pflags = flags;
810}
811
812static inline bool tb_fpu_enabled(int tb_flags)
813{
814#if defined(CONFIG_USER_ONLY)
815 return true;
816#else
817 return tb_flags & TB_FLAG_FPU_ENABLED;
818#endif
819}
820
821static inline bool tb_am_enabled(int tb_flags)
822{
823#ifndef TARGET_SPARC64
824 return false;
825#else
826 return tb_flags & TB_FLAG_AM_ENABLED;
827#endif
828}
829
830#endif
831