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20#ifndef TILEGX_CPU_H
21#define TILEGX_CPU_H
22
23#include "exec/cpu-defs.h"
24
25
26#define TILEGX_R_RE 0
27#define TILEGX_R_ERR 1
28#define TILEGX_R_NR 10
29#define TILEGX_R_BP 52
30#define TILEGX_R_TP 53
31#define TILEGX_R_SP 54
32#define TILEGX_R_LR 55
33#define TILEGX_R_COUNT 56
34#define TILEGX_R_SN 56
35#define TILEGX_R_IDN0 57
36#define TILEGX_R_IDN1 58
37#define TILEGX_R_UDN0 59
38#define TILEGX_R_UDN1 60
39#define TILEGX_R_UDN2 61
40#define TILEGX_R_UDN3 62
41#define TILEGX_R_ZERO 63
42#define TILEGX_R_NOREG 255
43
44
45enum {
46 TILEGX_SPR_CMPEXCH = 0,
47 TILEGX_SPR_CRITICAL_SEC = 1,
48 TILEGX_SPR_SIM_CONTROL = 2,
49 TILEGX_SPR_EX_CONTEXT_0_0 = 3,
50 TILEGX_SPR_EX_CONTEXT_0_1 = 4,
51 TILEGX_SPR_COUNT
52};
53
54
55typedef enum {
56 TILEGX_EXCP_NONE = 0,
57 TILEGX_EXCP_SYSCALL = 1,
58 TILEGX_EXCP_SIGNAL = 2,
59 TILEGX_EXCP_OPCODE_UNKNOWN = 0x101,
60 TILEGX_EXCP_OPCODE_UNIMPLEMENTED = 0x102,
61 TILEGX_EXCP_OPCODE_CMPEXCH = 0x103,
62 TILEGX_EXCP_OPCODE_CMPEXCH4 = 0x104,
63 TILEGX_EXCP_OPCODE_EXCH = 0x105,
64 TILEGX_EXCP_OPCODE_EXCH4 = 0x106,
65 TILEGX_EXCP_OPCODE_FETCHADD = 0x107,
66 TILEGX_EXCP_OPCODE_FETCHADD4 = 0x108,
67 TILEGX_EXCP_OPCODE_FETCHADDGEZ = 0x109,
68 TILEGX_EXCP_OPCODE_FETCHADDGEZ4 = 0x10a,
69 TILEGX_EXCP_OPCODE_FETCHAND = 0x10b,
70 TILEGX_EXCP_OPCODE_FETCHAND4 = 0x10c,
71 TILEGX_EXCP_OPCODE_FETCHOR = 0x10d,
72 TILEGX_EXCP_OPCODE_FETCHOR4 = 0x10e,
73 TILEGX_EXCP_REG_IDN_ACCESS = 0x181,
74 TILEGX_EXCP_REG_UDN_ACCESS = 0x182,
75 TILEGX_EXCP_UNALIGNMENT = 0x201,
76 TILEGX_EXCP_DBUG_BREAK = 0x301
77} TileExcp;
78
79typedef struct CPUTLGState {
80 uint64_t regs[TILEGX_R_COUNT];
81 uint64_t spregs[TILEGX_SPR_COUNT];
82 uint64_t pc;
83
84#if defined(CONFIG_USER_ONLY)
85 uint64_t excaddr;
86 uint64_t atomic_srca;
87 uint64_t atomic_srcb;
88 uint32_t atomic_dstr;
89 uint32_t signo;
90 uint32_t sigcode;
91#endif
92
93
94 struct {} end_reset_fields;
95} CPUTLGState;
96
97#include "hw/core/cpu.h"
98
99#define TYPE_TILEGX_CPU "tilegx-cpu"
100
101#define TILEGX_CPU_CLASS(klass) \
102 OBJECT_CLASS_CHECK(TileGXCPUClass, (klass), TYPE_TILEGX_CPU)
103#define TILEGX_CPU(obj) \
104 OBJECT_CHECK(TileGXCPU, (obj), TYPE_TILEGX_CPU)
105#define TILEGX_CPU_GET_CLASS(obj) \
106 OBJECT_GET_CLASS(TileGXCPUClass, (obj), TYPE_TILEGX_CPU)
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115typedef struct TileGXCPUClass {
116
117 CPUClass parent_class;
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120 DeviceRealize parent_realize;
121 void (*parent_reset)(CPUState *cpu);
122} TileGXCPUClass;
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129
130typedef struct TileGXCPU {
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132 CPUState parent_obj;
133
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135 CPUNegativeOffsetState neg;
136 CPUTLGState env;
137} TileGXCPU;
138
139
140
141#define MMU_USER_IDX 0
142
143typedef CPUTLGState CPUArchState;
144typedef TileGXCPU ArchCPU;
145
146#include "exec/cpu-all.h"
147
148void tilegx_tcg_init(void);
149int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc);
150
151#define CPU_RESOLVING_TYPE TYPE_TILEGX_CPU
152
153#define cpu_signal_handler cpu_tilegx_signal_handler
154
155static inline void cpu_get_tb_cpu_state(CPUTLGState *env, target_ulong *pc,
156 target_ulong *cs_base, uint32_t *flags)
157{
158 *pc = env->pc;
159 *cs_base = 0;
160 *flags = 0;
161}
162
163#endif
164