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29#include "qemu/osdep.h"
30#include "hw/dma/xlnx-zdma.h"
31#include "hw/irq.h"
32#include "hw/qdev-properties.h"
33#include "migration/vmstate.h"
34#include "qemu/bitops.h"
35#include "qemu/log.h"
36#include "qemu/module.h"
37#include "qapi/error.h"
38
39#ifndef XLNX_ZDMA_ERR_DEBUG
40#define XLNX_ZDMA_ERR_DEBUG 0
41#endif
42
43REG32(ZDMA_ERR_CTRL, 0x0)
44 FIELD(ZDMA_ERR_CTRL, APB_ERR_RES, 0, 1)
45REG32(ZDMA_CH_ISR, 0x100)
46 FIELD(ZDMA_CH_ISR, DMA_PAUSE, 11, 1)
47 FIELD(ZDMA_CH_ISR, DMA_DONE, 10, 1)
48 FIELD(ZDMA_CH_ISR, AXI_WR_DATA, 9, 1)
49 FIELD(ZDMA_CH_ISR, AXI_RD_DATA, 8, 1)
50 FIELD(ZDMA_CH_ISR, AXI_RD_DST_DSCR, 7, 1)
51 FIELD(ZDMA_CH_ISR, AXI_RD_SRC_DSCR, 6, 1)
52 FIELD(ZDMA_CH_ISR, IRQ_DST_ACCT_ERR, 5, 1)
53 FIELD(ZDMA_CH_ISR, IRQ_SRC_ACCT_ERR, 4, 1)
54 FIELD(ZDMA_CH_ISR, BYTE_CNT_OVRFL, 3, 1)
55 FIELD(ZDMA_CH_ISR, DST_DSCR_DONE, 2, 1)
56 FIELD(ZDMA_CH_ISR, SRC_DSCR_DONE, 1, 1)
57 FIELD(ZDMA_CH_ISR, INV_APB, 0, 1)
58REG32(ZDMA_CH_IMR, 0x104)
59 FIELD(ZDMA_CH_IMR, DMA_PAUSE, 11, 1)
60 FIELD(ZDMA_CH_IMR, DMA_DONE, 10, 1)
61 FIELD(ZDMA_CH_IMR, AXI_WR_DATA, 9, 1)
62 FIELD(ZDMA_CH_IMR, AXI_RD_DATA, 8, 1)
63 FIELD(ZDMA_CH_IMR, AXI_RD_DST_DSCR, 7, 1)
64 FIELD(ZDMA_CH_IMR, AXI_RD_SRC_DSCR, 6, 1)
65 FIELD(ZDMA_CH_IMR, IRQ_DST_ACCT_ERR, 5, 1)
66 FIELD(ZDMA_CH_IMR, IRQ_SRC_ACCT_ERR, 4, 1)
67 FIELD(ZDMA_CH_IMR, BYTE_CNT_OVRFL, 3, 1)
68 FIELD(ZDMA_CH_IMR, DST_DSCR_DONE, 2, 1)
69 FIELD(ZDMA_CH_IMR, SRC_DSCR_DONE, 1, 1)
70 FIELD(ZDMA_CH_IMR, INV_APB, 0, 1)
71REG32(ZDMA_CH_IEN, 0x108)
72 FIELD(ZDMA_CH_IEN, DMA_PAUSE, 11, 1)
73 FIELD(ZDMA_CH_IEN, DMA_DONE, 10, 1)
74 FIELD(ZDMA_CH_IEN, AXI_WR_DATA, 9, 1)
75 FIELD(ZDMA_CH_IEN, AXI_RD_DATA, 8, 1)
76 FIELD(ZDMA_CH_IEN, AXI_RD_DST_DSCR, 7, 1)
77 FIELD(ZDMA_CH_IEN, AXI_RD_SRC_DSCR, 6, 1)
78 FIELD(ZDMA_CH_IEN, IRQ_DST_ACCT_ERR, 5, 1)
79 FIELD(ZDMA_CH_IEN, IRQ_SRC_ACCT_ERR, 4, 1)
80 FIELD(ZDMA_CH_IEN, BYTE_CNT_OVRFL, 3, 1)
81 FIELD(ZDMA_CH_IEN, DST_DSCR_DONE, 2, 1)
82 FIELD(ZDMA_CH_IEN, SRC_DSCR_DONE, 1, 1)
83 FIELD(ZDMA_CH_IEN, INV_APB, 0, 1)
84REG32(ZDMA_CH_IDS, 0x10c)
85 FIELD(ZDMA_CH_IDS, DMA_PAUSE, 11, 1)
86 FIELD(ZDMA_CH_IDS, DMA_DONE, 10, 1)
87 FIELD(ZDMA_CH_IDS, AXI_WR_DATA, 9, 1)
88 FIELD(ZDMA_CH_IDS, AXI_RD_DATA, 8, 1)
89 FIELD(ZDMA_CH_IDS, AXI_RD_DST_DSCR, 7, 1)
90 FIELD(ZDMA_CH_IDS, AXI_RD_SRC_DSCR, 6, 1)
91 FIELD(ZDMA_CH_IDS, IRQ_DST_ACCT_ERR, 5, 1)
92 FIELD(ZDMA_CH_IDS, IRQ_SRC_ACCT_ERR, 4, 1)
93 FIELD(ZDMA_CH_IDS, BYTE_CNT_OVRFL, 3, 1)
94 FIELD(ZDMA_CH_IDS, DST_DSCR_DONE, 2, 1)
95 FIELD(ZDMA_CH_IDS, SRC_DSCR_DONE, 1, 1)
96 FIELD(ZDMA_CH_IDS, INV_APB, 0, 1)
97REG32(ZDMA_CH_CTRL0, 0x110)
98 FIELD(ZDMA_CH_CTRL0, OVR_FETCH, 7, 1)
99 FIELD(ZDMA_CH_CTRL0, POINT_TYPE, 6, 1)
100 FIELD(ZDMA_CH_CTRL0, MODE, 4, 2)
101 FIELD(ZDMA_CH_CTRL0, RATE_CTRL, 3, 1)
102 FIELD(ZDMA_CH_CTRL0, CONT_ADDR, 2, 1)
103 FIELD(ZDMA_CH_CTRL0, CONT, 1, 1)
104REG32(ZDMA_CH_CTRL1, 0x114)
105 FIELD(ZDMA_CH_CTRL1, DST_ISSUE, 5, 5)
106 FIELD(ZDMA_CH_CTRL1, SRC_ISSUE, 0, 5)
107REG32(ZDMA_CH_FCI, 0x118)
108 FIELD(ZDMA_CH_FCI, PROG_CELL_CNT, 2, 2)
109 FIELD(ZDMA_CH_FCI, SIDE, 1, 1)
110 FIELD(ZDMA_CH_FCI, EN, 0, 1)
111REG32(ZDMA_CH_STATUS, 0x11c)
112 FIELD(ZDMA_CH_STATUS, STATE, 0, 2)
113REG32(ZDMA_CH_DATA_ATTR, 0x120)
114 FIELD(ZDMA_CH_DATA_ATTR, ARBURST, 26, 2)
115 FIELD(ZDMA_CH_DATA_ATTR, ARCACHE, 22, 4)
116 FIELD(ZDMA_CH_DATA_ATTR, ARQOS, 18, 4)
117 FIELD(ZDMA_CH_DATA_ATTR, ARLEN, 14, 4)
118 FIELD(ZDMA_CH_DATA_ATTR, AWBURST, 12, 2)
119 FIELD(ZDMA_CH_DATA_ATTR, AWCACHE, 8, 4)
120 FIELD(ZDMA_CH_DATA_ATTR, AWQOS, 4, 4)
121 FIELD(ZDMA_CH_DATA_ATTR, AWLEN, 0, 4)
122REG32(ZDMA_CH_DSCR_ATTR, 0x124)
123 FIELD(ZDMA_CH_DSCR_ATTR, AXCOHRNT, 8, 1)
124 FIELD(ZDMA_CH_DSCR_ATTR, AXCACHE, 4, 4)
125 FIELD(ZDMA_CH_DSCR_ATTR, AXQOS, 0, 4)
126REG32(ZDMA_CH_SRC_DSCR_WORD0, 0x128)
127REG32(ZDMA_CH_SRC_DSCR_WORD1, 0x12c)
128 FIELD(ZDMA_CH_SRC_DSCR_WORD1, MSB, 0, 17)
129REG32(ZDMA_CH_SRC_DSCR_WORD2, 0x130)
130 FIELD(ZDMA_CH_SRC_DSCR_WORD2, SIZE, 0, 30)
131REG32(ZDMA_CH_SRC_DSCR_WORD3, 0x134)
132 FIELD(ZDMA_CH_SRC_DSCR_WORD3, CMD, 3, 2)
133 FIELD(ZDMA_CH_SRC_DSCR_WORD3, INTR, 2, 1)
134 FIELD(ZDMA_CH_SRC_DSCR_WORD3, TYPE, 1, 1)
135 FIELD(ZDMA_CH_SRC_DSCR_WORD3, COHRNT, 0, 1)
136REG32(ZDMA_CH_DST_DSCR_WORD0, 0x138)
137REG32(ZDMA_CH_DST_DSCR_WORD1, 0x13c)
138 FIELD(ZDMA_CH_DST_DSCR_WORD1, MSB, 0, 17)
139REG32(ZDMA_CH_DST_DSCR_WORD2, 0x140)
140 FIELD(ZDMA_CH_DST_DSCR_WORD2, SIZE, 0, 30)
141REG32(ZDMA_CH_DST_DSCR_WORD3, 0x144)
142 FIELD(ZDMA_CH_DST_DSCR_WORD3, INTR, 2, 1)
143 FIELD(ZDMA_CH_DST_DSCR_WORD3, TYPE, 1, 1)
144 FIELD(ZDMA_CH_DST_DSCR_WORD3, COHRNT, 0, 1)
145REG32(ZDMA_CH_WR_ONLY_WORD0, 0x148)
146REG32(ZDMA_CH_WR_ONLY_WORD1, 0x14c)
147REG32(ZDMA_CH_WR_ONLY_WORD2, 0x150)
148REG32(ZDMA_CH_WR_ONLY_WORD3, 0x154)
149REG32(ZDMA_CH_SRC_START_LSB, 0x158)
150REG32(ZDMA_CH_SRC_START_MSB, 0x15c)
151 FIELD(ZDMA_CH_SRC_START_MSB, ADDR, 0, 17)
152REG32(ZDMA_CH_DST_START_LSB, 0x160)
153REG32(ZDMA_CH_DST_START_MSB, 0x164)
154 FIELD(ZDMA_CH_DST_START_MSB, ADDR, 0, 17)
155REG32(ZDMA_CH_RATE_CTRL, 0x18c)
156 FIELD(ZDMA_CH_RATE_CTRL, CNT, 0, 12)
157REG32(ZDMA_CH_SRC_CUR_PYLD_LSB, 0x168)
158REG32(ZDMA_CH_SRC_CUR_PYLD_MSB, 0x16c)
159 FIELD(ZDMA_CH_SRC_CUR_PYLD_MSB, ADDR, 0, 17)
160REG32(ZDMA_CH_DST_CUR_PYLD_LSB, 0x170)
161REG32(ZDMA_CH_DST_CUR_PYLD_MSB, 0x174)
162 FIELD(ZDMA_CH_DST_CUR_PYLD_MSB, ADDR, 0, 17)
163REG32(ZDMA_CH_SRC_CUR_DSCR_LSB, 0x178)
164REG32(ZDMA_CH_SRC_CUR_DSCR_MSB, 0x17c)
165 FIELD(ZDMA_CH_SRC_CUR_DSCR_MSB, ADDR, 0, 17)
166REG32(ZDMA_CH_DST_CUR_DSCR_LSB, 0x180)
167REG32(ZDMA_CH_DST_CUR_DSCR_MSB, 0x184)
168 FIELD(ZDMA_CH_DST_CUR_DSCR_MSB, ADDR, 0, 17)
169REG32(ZDMA_CH_TOTAL_BYTE, 0x188)
170REG32(ZDMA_CH_RATE_CNTL, 0x18c)
171 FIELD(ZDMA_CH_RATE_CNTL, CNT, 0, 12)
172REG32(ZDMA_CH_IRQ_SRC_ACCT, 0x190)
173 FIELD(ZDMA_CH_IRQ_SRC_ACCT, CNT, 0, 8)
174REG32(ZDMA_CH_IRQ_DST_ACCT, 0x194)
175 FIELD(ZDMA_CH_IRQ_DST_ACCT, CNT, 0, 8)
176REG32(ZDMA_CH_DBG0, 0x198)
177 FIELD(ZDMA_CH_DBG0, CMN_BUF_FREE, 0, 9)
178REG32(ZDMA_CH_DBG1, 0x19c)
179 FIELD(ZDMA_CH_DBG1, CMN_BUF_OCC, 0, 9)
180REG32(ZDMA_CH_CTRL2, 0x200)
181 FIELD(ZDMA_CH_CTRL2, EN, 0, 1)
182
183enum {
184 PT_REG = 0,
185 PT_MEM = 1,
186};
187
188enum {
189 CMD_HALT = 1,
190 CMD_STOP = 2,
191};
192
193enum {
194 RW_MODE_RW = 0,
195 RW_MODE_WO = 1,
196 RW_MODE_RO = 2,
197};
198
199enum {
200 DTYPE_LINEAR = 0,
201 DTYPE_LINKED = 1,
202};
203
204enum {
205 AXI_BURST_FIXED = 0,
206 AXI_BURST_INCR = 1,
207};
208
209static void zdma_ch_imr_update_irq(XlnxZDMA *s)
210{
211 bool pending;
212
213 pending = s->regs[R_ZDMA_CH_ISR] & ~s->regs[R_ZDMA_CH_IMR];
214
215 qemu_set_irq(s->irq_zdma_ch_imr, pending);
216}
217
218static void zdma_ch_isr_postw(RegisterInfo *reg, uint64_t val64)
219{
220 XlnxZDMA *s = XLNX_ZDMA(reg->opaque);
221 zdma_ch_imr_update_irq(s);
222}
223
224static uint64_t zdma_ch_ien_prew(RegisterInfo *reg, uint64_t val64)
225{
226 XlnxZDMA *s = XLNX_ZDMA(reg->opaque);
227 uint32_t val = val64;
228
229 s->regs[R_ZDMA_CH_IMR] &= ~val;
230 zdma_ch_imr_update_irq(s);
231 return 0;
232}
233
234static uint64_t zdma_ch_ids_prew(RegisterInfo *reg, uint64_t val64)
235{
236 XlnxZDMA *s = XLNX_ZDMA(reg->opaque);
237 uint32_t val = val64;
238
239 s->regs[R_ZDMA_CH_IMR] |= val;
240 zdma_ch_imr_update_irq(s);
241 return 0;
242}
243
244static void zdma_set_state(XlnxZDMA *s, XlnxZDMAState state)
245{
246 s->state = state;
247 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_STATUS, STATE, state);
248
249
250 if (s->error) {
251 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_STATUS, STATE, 3);
252 }
253}
254
255static void zdma_src_done(XlnxZDMA *s)
256{
257 unsigned int cnt;
258 cnt = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT);
259 cnt++;
260 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT, cnt);
261 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, SRC_DSCR_DONE, true);
262
263
264 if (cnt != ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT)) {
265 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, IRQ_SRC_ACCT_ERR, true);
266 }
267 zdma_ch_imr_update_irq(s);
268}
269
270static void zdma_dst_done(XlnxZDMA *s)
271{
272 unsigned int cnt;
273 cnt = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT);
274 cnt++;
275 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT, cnt);
276 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DST_DSCR_DONE, true);
277
278
279 if (cnt != ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT)) {
280 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, IRQ_DST_ACCT_ERR, true);
281 }
282 zdma_ch_imr_update_irq(s);
283}
284
285static uint64_t zdma_get_regaddr64(XlnxZDMA *s, unsigned int basereg)
286{
287 uint64_t addr;
288
289 addr = s->regs[basereg + 1];
290 addr <<= 32;
291 addr |= s->regs[basereg];
292
293 return addr;
294}
295
296static void zdma_put_regaddr64(XlnxZDMA *s, unsigned int basereg, uint64_t addr)
297{
298 s->regs[basereg] = addr;
299 s->regs[basereg + 1] = addr >> 32;
300}
301
302static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
303{
304
305 if (addr % sizeof(XlnxZDMADescr)) {
306 qemu_log_mask(LOG_GUEST_ERROR,
307 "zdma: unaligned descriptor at %" PRIx64,
308 addr);
309 memset(buf, 0x0, sizeof(XlnxZDMADescr));
310 s->error = true;
311 return false;
312 }
313
314 address_space_read(s->dma_as, addr, s->attr, buf, sizeof(XlnxZDMADescr));
315 return true;
316}
317
318static void zdma_load_src_descriptor(XlnxZDMA *s)
319{
320 uint64_t src_addr;
321 unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE);
322
323 if (ptype == PT_REG) {
324 memcpy(&s->dsc_src, &s->regs[R_ZDMA_CH_SRC_DSCR_WORD0],
325 sizeof(s->dsc_src));
326 return;
327 }
328
329 src_addr = zdma_get_regaddr64(s, R_ZDMA_CH_SRC_CUR_DSCR_LSB);
330
331 if (!zdma_load_descriptor(s, src_addr, &s->dsc_src)) {
332 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, AXI_RD_SRC_DSCR, true);
333 }
334}
335
336static void zdma_update_descr_addr(XlnxZDMA *s, bool type,
337 unsigned int basereg)
338{
339 uint64_t addr, next;
340
341 if (type == DTYPE_LINEAR) {
342 addr = zdma_get_regaddr64(s, basereg);
343 next = addr + sizeof(s->dsc_dst);
344 } else {
345 addr = zdma_get_regaddr64(s, basereg);
346 addr += sizeof(s->dsc_dst);
347 address_space_read(s->dma_as, addr, s->attr, (void *) &next, 8);
348 }
349
350 zdma_put_regaddr64(s, basereg, next);
351}
352
353static void zdma_load_dst_descriptor(XlnxZDMA *s)
354{
355 uint64_t dst_addr;
356 unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE);
357 bool dst_type;
358
359 if (ptype == PT_REG) {
360 memcpy(&s->dsc_dst, &s->regs[R_ZDMA_CH_DST_DSCR_WORD0],
361 sizeof(s->dsc_dst));
362 return;
363 }
364
365 dst_addr = zdma_get_regaddr64(s, R_ZDMA_CH_DST_CUR_DSCR_LSB);
366
367 if (!zdma_load_descriptor(s, dst_addr, &s->dsc_dst)) {
368 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, AXI_RD_DST_DSCR, true);
369 }
370
371
372 dst_type = FIELD_EX32(s->dsc_dst.words[3], ZDMA_CH_DST_DSCR_WORD3, TYPE);
373 zdma_update_descr_addr(s, dst_type, R_ZDMA_CH_DST_CUR_DSCR_LSB);
374}
375
376static void zdma_write_dst(XlnxZDMA *s, uint8_t *buf, uint32_t len)
377{
378 uint32_t dst_size, dlen;
379 bool dst_intr;
380 unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE);
381 unsigned int rw_mode = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, MODE);
382 unsigned int burst_type = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_DATA_ATTR,
383 AWBURST);
384
385
386 if (ptype != PT_REG) {
387 burst_type = AXI_BURST_INCR;
388 }
389
390 while (len) {
391 dst_size = FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD2,
392 SIZE);
393 if (dst_size == 0 && ptype == PT_MEM) {
394 zdma_load_dst_descriptor(s);
395 dst_size = FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD2,
396 SIZE);
397 }
398
399
400
401 if (ptype == PT_REG && rw_mode != RW_MODE_WO) {
402 dst_size = len;
403 }
404
405 dst_intr = FIELD_EX32(s->dsc_dst.words[3], ZDMA_CH_DST_DSCR_WORD3,
406 INTR);
407
408 dlen = len > dst_size ? dst_size : len;
409 if (burst_type == AXI_BURST_FIXED) {
410 if (dlen > (s->cfg.bus_width / 8)) {
411 dlen = s->cfg.bus_width / 8;
412 }
413 }
414
415 address_space_write(s->dma_as, s->dsc_dst.addr, s->attr, buf, dlen);
416 if (burst_type == AXI_BURST_INCR) {
417 s->dsc_dst.addr += dlen;
418 }
419 dst_size -= dlen;
420 buf += dlen;
421 len -= dlen;
422
423 if (dst_size == 0 && dst_intr) {
424 zdma_dst_done(s);
425 }
426
427
428 s->dsc_dst.words[2] = FIELD_DP32(s->dsc_dst.words[2],
429 ZDMA_CH_DST_DSCR_WORD2,
430 SIZE,
431 dst_size);
432 }
433}
434
435static void zdma_process_descr(XlnxZDMA *s)
436{
437 uint64_t src_addr;
438 uint32_t src_size, len;
439 unsigned int src_cmd;
440 bool src_intr, src_type;
441 unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE);
442 unsigned int rw_mode = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, MODE);
443 unsigned int burst_type = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_DATA_ATTR,
444 ARBURST);
445
446 src_addr = s->dsc_src.addr;
447 src_size = FIELD_EX32(s->dsc_src.words[2], ZDMA_CH_SRC_DSCR_WORD2, SIZE);
448 src_cmd = FIELD_EX32(s->dsc_src.words[3], ZDMA_CH_SRC_DSCR_WORD3, CMD);
449 src_type = FIELD_EX32(s->dsc_src.words[3], ZDMA_CH_SRC_DSCR_WORD3, TYPE);
450 src_intr = FIELD_EX32(s->dsc_src.words[3], ZDMA_CH_SRC_DSCR_WORD3, INTR);
451
452
453
454
455 if (ptype != PT_REG) {
456 if (rw_mode != RW_MODE_RW) {
457 qemu_log_mask(LOG_GUEST_ERROR,
458 "zDMA: rw-mode=%d but not simple DMA mode.\n",
459 rw_mode);
460 }
461 if (burst_type != AXI_BURST_INCR) {
462 qemu_log_mask(LOG_GUEST_ERROR,
463 "zDMA: burst_type=%d but not simple DMA mode.\n",
464 burst_type);
465 }
466 burst_type = AXI_BURST_INCR;
467 rw_mode = RW_MODE_RW;
468 }
469
470 if (rw_mode == RW_MODE_WO) {
471
472
473 src_size = FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD2,
474 SIZE);
475 memcpy(s->buf, &s->regs[R_ZDMA_CH_WR_ONLY_WORD0], s->cfg.bus_width / 8);
476 }
477
478 while (src_size) {
479 len = src_size > ARRAY_SIZE(s->buf) ? ARRAY_SIZE(s->buf) : src_size;
480 if (burst_type == AXI_BURST_FIXED) {
481 if (len > (s->cfg.bus_width / 8)) {
482 len = s->cfg.bus_width / 8;
483 }
484 }
485
486 if (rw_mode == RW_MODE_WO) {
487 if (len > s->cfg.bus_width / 8) {
488 len = s->cfg.bus_width / 8;
489 }
490 } else {
491 address_space_read(s->dma_as, src_addr, s->attr, s->buf, len);
492 if (burst_type == AXI_BURST_INCR) {
493 src_addr += len;
494 }
495 }
496
497 if (rw_mode != RW_MODE_RO) {
498 zdma_write_dst(s, s->buf, len);
499 }
500
501 s->regs[R_ZDMA_CH_TOTAL_BYTE] += len;
502 src_size -= len;
503 }
504
505 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_DONE, true);
506
507 if (src_intr) {
508 zdma_src_done(s);
509 }
510
511 if (ptype == PT_REG || src_cmd == CMD_STOP) {
512 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_CTRL2, EN, 0);
513 zdma_set_state(s, DISABLED);
514 }
515
516 if (src_cmd == CMD_HALT) {
517 zdma_set_state(s, PAUSED);
518 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_PAUSE, 1);
519 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_DONE, false);
520 zdma_ch_imr_update_irq(s);
521 return;
522 }
523
524 zdma_update_descr_addr(s, src_type, R_ZDMA_CH_SRC_CUR_DSCR_LSB);
525}
526
527static void zdma_run(XlnxZDMA *s)
528{
529 while (s->state == ENABLED && !s->error) {
530 zdma_load_src_descriptor(s);
531
532 if (s->error) {
533 zdma_set_state(s, DISABLED);
534 } else {
535 zdma_process_descr(s);
536 }
537 }
538
539 zdma_ch_imr_update_irq(s);
540}
541
542static void zdma_update_descr_addr_from_start(XlnxZDMA *s)
543{
544 uint64_t src_addr, dst_addr;
545
546 src_addr = zdma_get_regaddr64(s, R_ZDMA_CH_SRC_START_LSB);
547 zdma_put_regaddr64(s, R_ZDMA_CH_SRC_CUR_DSCR_LSB, src_addr);
548 dst_addr = zdma_get_regaddr64(s, R_ZDMA_CH_DST_START_LSB);
549 zdma_put_regaddr64(s, R_ZDMA_CH_DST_CUR_DSCR_LSB, dst_addr);
550 zdma_load_dst_descriptor(s);
551}
552
553static void zdma_ch_ctrlx_postw(RegisterInfo *reg, uint64_t val64)
554{
555 XlnxZDMA *s = XLNX_ZDMA(reg->opaque);
556
557 if (ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL2, EN)) {
558 s->error = false;
559
560 if (s->state == PAUSED &&
561 ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, CONT)) {
562 if (ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, CONT_ADDR) == 1) {
563 zdma_update_descr_addr_from_start(s);
564 } else {
565 bool src_type = FIELD_EX32(s->dsc_src.words[3],
566 ZDMA_CH_SRC_DSCR_WORD3, TYPE);
567 zdma_update_descr_addr(s, src_type,
568 R_ZDMA_CH_SRC_CUR_DSCR_LSB);
569 }
570 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_CTRL0, CONT, false);
571 zdma_set_state(s, ENABLED);
572 } else if (s->state == DISABLED) {
573 zdma_update_descr_addr_from_start(s);
574 zdma_set_state(s, ENABLED);
575 }
576 } else {
577
578 if (s->state == PAUSED &&
579 ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, CONT)) {
580 zdma_set_state(s, DISABLED);
581 }
582 }
583
584 zdma_run(s);
585}
586
587static RegisterAccessInfo zdma_regs_info[] = {
588 { .name = "ZDMA_ERR_CTRL", .addr = A_ZDMA_ERR_CTRL,
589 .rsvd = 0xfffffffe,
590 },{ .name = "ZDMA_CH_ISR", .addr = A_ZDMA_CH_ISR,
591 .rsvd = 0xfffff000,
592 .w1c = 0xfff,
593 .post_write = zdma_ch_isr_postw,
594 },{ .name = "ZDMA_CH_IMR", .addr = A_ZDMA_CH_IMR,
595 .reset = 0xfff,
596 .rsvd = 0xfffff000,
597 .ro = 0xfff,
598 },{ .name = "ZDMA_CH_IEN", .addr = A_ZDMA_CH_IEN,
599 .rsvd = 0xfffff000,
600 .pre_write = zdma_ch_ien_prew,
601 },{ .name = "ZDMA_CH_IDS", .addr = A_ZDMA_CH_IDS,
602 .rsvd = 0xfffff000,
603 .pre_write = zdma_ch_ids_prew,
604 },{ .name = "ZDMA_CH_CTRL0", .addr = A_ZDMA_CH_CTRL0,
605 .reset = 0x80,
606 .rsvd = 0xffffff01,
607 .post_write = zdma_ch_ctrlx_postw,
608 },{ .name = "ZDMA_CH_CTRL1", .addr = A_ZDMA_CH_CTRL1,
609 .reset = 0x3ff,
610 .rsvd = 0xfffffc00,
611 },{ .name = "ZDMA_CH_FCI", .addr = A_ZDMA_CH_FCI,
612 .rsvd = 0xffffffc0,
613 },{ .name = "ZDMA_CH_STATUS", .addr = A_ZDMA_CH_STATUS,
614 .rsvd = 0xfffffffc,
615 .ro = 0x3,
616 },{ .name = "ZDMA_CH_DATA_ATTR", .addr = A_ZDMA_CH_DATA_ATTR,
617 .reset = 0x483d20f,
618 .rsvd = 0xf0000000,
619 },{ .name = "ZDMA_CH_DSCR_ATTR", .addr = A_ZDMA_CH_DSCR_ATTR,
620 .rsvd = 0xfffffe00,
621 },{ .name = "ZDMA_CH_SRC_DSCR_WORD0", .addr = A_ZDMA_CH_SRC_DSCR_WORD0,
622 },{ .name = "ZDMA_CH_SRC_DSCR_WORD1", .addr = A_ZDMA_CH_SRC_DSCR_WORD1,
623 .rsvd = 0xfffe0000,
624 },{ .name = "ZDMA_CH_SRC_DSCR_WORD2", .addr = A_ZDMA_CH_SRC_DSCR_WORD2,
625 .rsvd = 0xc0000000,
626 },{ .name = "ZDMA_CH_SRC_DSCR_WORD3", .addr = A_ZDMA_CH_SRC_DSCR_WORD3,
627 .rsvd = 0xffffffe0,
628 },{ .name = "ZDMA_CH_DST_DSCR_WORD0", .addr = A_ZDMA_CH_DST_DSCR_WORD0,
629 },{ .name = "ZDMA_CH_DST_DSCR_WORD1", .addr = A_ZDMA_CH_DST_DSCR_WORD1,
630 .rsvd = 0xfffe0000,
631 },{ .name = "ZDMA_CH_DST_DSCR_WORD2", .addr = A_ZDMA_CH_DST_DSCR_WORD2,
632 .rsvd = 0xc0000000,
633 },{ .name = "ZDMA_CH_DST_DSCR_WORD3", .addr = A_ZDMA_CH_DST_DSCR_WORD3,
634 .rsvd = 0xfffffffa,
635 },{ .name = "ZDMA_CH_WR_ONLY_WORD0", .addr = A_ZDMA_CH_WR_ONLY_WORD0,
636 },{ .name = "ZDMA_CH_WR_ONLY_WORD1", .addr = A_ZDMA_CH_WR_ONLY_WORD1,
637 },{ .name = "ZDMA_CH_WR_ONLY_WORD2", .addr = A_ZDMA_CH_WR_ONLY_WORD2,
638 },{ .name = "ZDMA_CH_WR_ONLY_WORD3", .addr = A_ZDMA_CH_WR_ONLY_WORD3,
639 },{ .name = "ZDMA_CH_SRC_START_LSB", .addr = A_ZDMA_CH_SRC_START_LSB,
640 },{ .name = "ZDMA_CH_SRC_START_MSB", .addr = A_ZDMA_CH_SRC_START_MSB,
641 .rsvd = 0xfffe0000,
642 },{ .name = "ZDMA_CH_DST_START_LSB", .addr = A_ZDMA_CH_DST_START_LSB,
643 },{ .name = "ZDMA_CH_DST_START_MSB", .addr = A_ZDMA_CH_DST_START_MSB,
644 .rsvd = 0xfffe0000,
645 },{ .name = "ZDMA_CH_SRC_CUR_PYLD_LSB", .addr = A_ZDMA_CH_SRC_CUR_PYLD_LSB,
646 .ro = 0xffffffff,
647 },{ .name = "ZDMA_CH_SRC_CUR_PYLD_MSB", .addr = A_ZDMA_CH_SRC_CUR_PYLD_MSB,
648 .rsvd = 0xfffe0000,
649 .ro = 0x1ffff,
650 },{ .name = "ZDMA_CH_DST_CUR_PYLD_LSB", .addr = A_ZDMA_CH_DST_CUR_PYLD_LSB,
651 .ro = 0xffffffff,
652 },{ .name = "ZDMA_CH_DST_CUR_PYLD_MSB", .addr = A_ZDMA_CH_DST_CUR_PYLD_MSB,
653 .rsvd = 0xfffe0000,
654 .ro = 0x1ffff,
655 },{ .name = "ZDMA_CH_SRC_CUR_DSCR_LSB", .addr = A_ZDMA_CH_SRC_CUR_DSCR_LSB,
656 .ro = 0xffffffff,
657 },{ .name = "ZDMA_CH_SRC_CUR_DSCR_MSB", .addr = A_ZDMA_CH_SRC_CUR_DSCR_MSB,
658 .rsvd = 0xfffe0000,
659 .ro = 0x1ffff,
660 },{ .name = "ZDMA_CH_DST_CUR_DSCR_LSB", .addr = A_ZDMA_CH_DST_CUR_DSCR_LSB,
661 .ro = 0xffffffff,
662 },{ .name = "ZDMA_CH_DST_CUR_DSCR_MSB", .addr = A_ZDMA_CH_DST_CUR_DSCR_MSB,
663 .rsvd = 0xfffe0000,
664 .ro = 0x1ffff,
665 },{ .name = "ZDMA_CH_TOTAL_BYTE", .addr = A_ZDMA_CH_TOTAL_BYTE,
666 .w1c = 0xffffffff,
667 },{ .name = "ZDMA_CH_RATE_CNTL", .addr = A_ZDMA_CH_RATE_CNTL,
668 .rsvd = 0xfffff000,
669 },{ .name = "ZDMA_CH_IRQ_SRC_ACCT", .addr = A_ZDMA_CH_IRQ_SRC_ACCT,
670 .rsvd = 0xffffff00,
671 .ro = 0xff,
672 .cor = 0xff,
673 },{ .name = "ZDMA_CH_IRQ_DST_ACCT", .addr = A_ZDMA_CH_IRQ_DST_ACCT,
674 .rsvd = 0xffffff00,
675 .ro = 0xff,
676 .cor = 0xff,
677 },{ .name = "ZDMA_CH_DBG0", .addr = A_ZDMA_CH_DBG0,
678 .rsvd = 0xfffffe00,
679 .ro = 0x1ff,
680
681
682
683
684
685 .reset = 0x100
686 },{ .name = "ZDMA_CH_DBG1", .addr = A_ZDMA_CH_DBG1,
687 .rsvd = 0xfffffe00,
688 .ro = 0x1ff,
689 },{ .name = "ZDMA_CH_CTRL2", .addr = A_ZDMA_CH_CTRL2,
690 .rsvd = 0xfffffffe,
691 .post_write = zdma_ch_ctrlx_postw,
692 }
693};
694
695static void zdma_reset(DeviceState *dev)
696{
697 XlnxZDMA *s = XLNX_ZDMA(dev);
698 unsigned int i;
699
700 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
701 register_reset(&s->regs_info[i]);
702 }
703
704 zdma_ch_imr_update_irq(s);
705}
706
707static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
708{
709 XlnxZDMA *s = XLNX_ZDMA(opaque);
710 RegisterInfo *r = &s->regs_info[addr / 4];
711
712 if (!r->data) {
713 gchar *path = object_get_canonical_path(OBJECT(s));
714 qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
715 path,
716 addr);
717 g_free(path);
718 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
719 zdma_ch_imr_update_irq(s);
720 return 0;
721 }
722 return register_read(r, ~0, NULL, false);
723}
724
725static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
726 unsigned size)
727{
728 XlnxZDMA *s = XLNX_ZDMA(opaque);
729 RegisterInfo *r = &s->regs_info[addr / 4];
730
731 if (!r->data) {
732 gchar *path = object_get_canonical_path(OBJECT(s));
733 qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
734 path,
735 addr, value);
736 g_free(path);
737 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
738 zdma_ch_imr_update_irq(s);
739 return;
740 }
741 register_write(r, value, ~0, NULL, false);
742}
743
744static const MemoryRegionOps zdma_ops = {
745 .read = zdma_read,
746 .write = zdma_write,
747 .endianness = DEVICE_LITTLE_ENDIAN,
748 .valid = {
749 .min_access_size = 4,
750 .max_access_size = 4,
751 },
752};
753
754static void zdma_realize(DeviceState *dev, Error **errp)
755{
756 XlnxZDMA *s = XLNX_ZDMA(dev);
757 unsigned int i;
758
759 for (i = 0; i < ARRAY_SIZE(zdma_regs_info); ++i) {
760 RegisterInfo *r = &s->regs_info[zdma_regs_info[i].addr / 4];
761
762 *r = (RegisterInfo) {
763 .data = (uint8_t *)&s->regs[
764 zdma_regs_info[i].addr / 4],
765 .data_size = sizeof(uint32_t),
766 .access = &zdma_regs_info[i],
767 .opaque = s,
768 };
769 }
770
771 if (s->dma_mr) {
772 s->dma_as = g_malloc0(sizeof(AddressSpace));
773 address_space_init(s->dma_as, s->dma_mr, NULL);
774 } else {
775 s->dma_as = &address_space_memory;
776 }
777 s->attr = MEMTXATTRS_UNSPECIFIED;
778}
779
780static void zdma_init(Object *obj)
781{
782 XlnxZDMA *s = XLNX_ZDMA(obj);
783 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
784
785 memory_region_init_io(&s->iomem, obj, &zdma_ops, s,
786 TYPE_XLNX_ZDMA, ZDMA_R_MAX * 4);
787 sysbus_init_mmio(sbd, &s->iomem);
788 sysbus_init_irq(sbd, &s->irq_zdma_ch_imr);
789
790 object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
791 (Object **)&s->dma_mr,
792 qdev_prop_allow_set_link_before_realize,
793 OBJ_PROP_LINK_STRONG,
794 &error_abort);
795}
796
797static const VMStateDescription vmstate_zdma = {
798 .name = TYPE_XLNX_ZDMA,
799 .version_id = 1,
800 .minimum_version_id = 1,
801 .minimum_version_id_old = 1,
802 .fields = (VMStateField[]) {
803 VMSTATE_UINT32_ARRAY(regs, XlnxZDMA, ZDMA_R_MAX),
804 VMSTATE_UINT32(state, XlnxZDMA),
805 VMSTATE_UINT32_ARRAY(dsc_src.words, XlnxZDMA, 4),
806 VMSTATE_UINT32_ARRAY(dsc_dst.words, XlnxZDMA, 4),
807 VMSTATE_END_OF_LIST(),
808 }
809};
810
811static Property zdma_props[] = {
812 DEFINE_PROP_UINT32("bus-width", XlnxZDMA, cfg.bus_width, 64),
813 DEFINE_PROP_END_OF_LIST(),
814};
815
816static void zdma_class_init(ObjectClass *klass, void *data)
817{
818 DeviceClass *dc = DEVICE_CLASS(klass);
819
820 dc->reset = zdma_reset;
821 dc->realize = zdma_realize;
822 device_class_set_props(dc, zdma_props);
823 dc->vmsd = &vmstate_zdma;
824}
825
826static const TypeInfo zdma_info = {
827 .name = TYPE_XLNX_ZDMA,
828 .parent = TYPE_SYS_BUS_DEVICE,
829 .instance_size = sizeof(XlnxZDMA),
830 .class_init = zdma_class_init,
831 .instance_init = zdma_init,
832};
833
834static void zdma_register_types(void)
835{
836 type_register_static(&zdma_info);
837}
838
839type_init(zdma_register_types)
840
