qemu/hw/isa/lpc_ich9.c
<<
>>
Prefs
   1/*
   2 * QEMU ICH9 Emulation
   3 *
   4 * Copyright (c) 2006 Fabrice Bellard
   5 * Copyright (c) 2009, 2010, 2011
   6 *               Isaku Yamahata <yamahata at valinux co jp>
   7 *               VA Linux Systems Japan K.K.
   8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9 *
  10 * This is based on piix.c, but heavily modified.
  11 *
  12 * Permission is hereby granted, free of charge, to any person obtaining a copy
  13 * of this software and associated documentation files (the "Software"), to deal
  14 * in the Software without restriction, including without limitation the rights
  15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16 * copies of the Software, and to permit persons to whom the Software is
  17 * furnished to do so, subject to the following conditions:
  18 *
  19 * The above copyright notice and this permission notice shall be included in
  20 * all copies or substantial portions of the Software.
  21 *
  22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28 * THE SOFTWARE.
  29 */
  30
  31#include "qemu/osdep.h"
  32#include "cpu.h"
  33#include "qapi/visitor.h"
  34#include "qemu/range.h"
  35#include "hw/isa/isa.h"
  36#include "hw/sysbus.h"
  37#include "migration/vmstate.h"
  38#include "hw/irq.h"
  39#include "hw/isa/apm.h"
  40#include "hw/pci/pci.h"
  41#include "hw/pci/pci_bridge.h"
  42#include "hw/i386/ich9.h"
  43#include "hw/acpi/acpi.h"
  44#include "hw/acpi/ich9.h"
  45#include "hw/pci/pci_bus.h"
  46#include "hw/qdev-properties.h"
  47#include "exec/address-spaces.h"
  48#include "sysemu/runstate.h"
  49#include "sysemu/sysemu.h"
  50#include "hw/core/cpu.h"
  51#include "hw/nvram/fw_cfg.h"
  52#include "qemu/cutils.h"
  53
  54/*****************************************************************************/
  55/* ICH9 LPC PCI to ISA bridge */
  56
  57static void ich9_lpc_reset(DeviceState *qdev);
  58
  59/* chipset configuration register
  60 * to access chipset configuration registers, pci_[sg]et_{byte, word, long}
  61 * are used.
  62 * Although it's not pci configuration space, it's little endian as Intel.
  63 */
  64
  65static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir)
  66{
  67    int intx;
  68    for (intx = 0; intx < PCI_NUM_PINS; intx++) {
  69        irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK;
  70    }
  71}
  72
  73static void ich9_cc_update(ICH9LPCState *lpc)
  74{
  75    int slot;
  76    int pci_intx;
  77
  78    const int reg_offsets[] = {
  79        ICH9_CC_D25IR,
  80        ICH9_CC_D26IR,
  81        ICH9_CC_D27IR,
  82        ICH9_CC_D28IR,
  83        ICH9_CC_D29IR,
  84        ICH9_CC_D30IR,
  85        ICH9_CC_D31IR,
  86    };
  87    const int *offset;
  88
  89    /* D{25 - 31}IR, but D30IR is read only to 0. */
  90    for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) {
  91        if (slot == 30) {
  92            continue;
  93        }
  94        ich9_cc_update_ir(lpc->irr[slot],
  95                          pci_get_word(lpc->chip_config + *offset));
  96    }
  97
  98    /*
  99     * D30: DMI2PCI bridge
 100     * It is arbitrarily decided how INTx lines of PCI devices behind
 101     * the bridge are connected to pirq lines. Our choice is PIRQ[E-H].
 102     * INT[A-D] are connected to PIRQ[E-H]
 103     */
 104    for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {
 105        lpc->irr[30][pci_intx] = pci_intx + 4;
 106    }
 107}
 108
 109static void ich9_cc_init(ICH9LPCState *lpc)
 110{
 111    int slot;
 112    int intx;
 113
 114    /* the default irq routing is arbitrary as long as it matches with
 115     * acpi irq routing table.
 116     * The one that is incompatible with piix_pci(= bochs) one is
 117     * intentionally chosen to let the users know that the different
 118     * board is used.
 119     *
 120     * int[A-D] -> pirq[E-F]
 121     * avoid pirq A-D because they are used for pci express port
 122     */
 123    for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
 124        for (intx = 0; intx < PCI_NUM_PINS; intx++) {
 125            lpc->irr[slot][intx] = (slot + intx) % 4 + 4;
 126        }
 127    }
 128    ich9_cc_update(lpc);
 129}
 130
 131static void ich9_cc_reset(ICH9LPCState *lpc)
 132{
 133    uint8_t *c = lpc->chip_config;
 134
 135    memset(lpc->chip_config, 0, sizeof(lpc->chip_config));
 136
 137    pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT);
 138    pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT);
 139    pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT);
 140    pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT);
 141    pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT);
 142    pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT);
 143    pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT);
 144    pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT);
 145
 146    ich9_cc_update(lpc);
 147}
 148
 149static void ich9_cc_addr_len(uint64_t *addr, unsigned *len)
 150{
 151    *addr &= ICH9_CC_ADDR_MASK;
 152    if (*addr + *len >= ICH9_CC_SIZE) {
 153        *len = ICH9_CC_SIZE - *addr;
 154    }
 155}
 156
 157/* val: little endian */
 158static void ich9_cc_write(void *opaque, hwaddr addr,
 159                          uint64_t val, unsigned len)
 160{
 161    ICH9LPCState *lpc = (ICH9LPCState *)opaque;
 162
 163    ich9_cc_addr_len(&addr, &len);
 164    memcpy(lpc->chip_config + addr, &val, len);
 165    pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
 166    ich9_cc_update(lpc);
 167}
 168
 169/* return value: little endian */
 170static uint64_t ich9_cc_read(void *opaque, hwaddr addr,
 171                              unsigned len)
 172{
 173    ICH9LPCState *lpc = (ICH9LPCState *)opaque;
 174
 175    uint32_t val = 0;
 176    ich9_cc_addr_len(&addr, &len);
 177    memcpy(&val, lpc->chip_config + addr, len);
 178    return val;
 179}
 180
 181/* IRQ routing */
 182/* */
 183static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis)
 184{
 185    *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK;
 186    *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN;
 187}
 188
 189static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num,
 190                             int *pic_irq, int *pic_dis)
 191{
 192    switch (pirq_num) {
 193    case 0 ... 3: /* A-D */
 194        ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num],
 195                      pic_irq, pic_dis);
 196        return;
 197    case 4 ... 7: /* E-H */
 198        ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)],
 199                      pic_irq, pic_dis);
 200        return;
 201    default:
 202        break;
 203    }
 204    abort();
 205}
 206
 207/* gsi: i8259+ioapic irq 0-15, otherwise assert */
 208static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi)
 209{
 210    int i, pic_level;
 211
 212    assert(gsi < ICH9_LPC_PIC_NUM_PINS);
 213
 214    /* The pic level is the logical OR of all the PCI irqs mapped to it */
 215    pic_level = 0;
 216    for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) {
 217        int tmp_irq;
 218        int tmp_dis;
 219        ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis);
 220        if (!tmp_dis && tmp_irq == gsi) {
 221            pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i);
 222        }
 223    }
 224    if (gsi == lpc->sci_gsi) {
 225        pic_level |= lpc->sci_level;
 226    }
 227
 228    qemu_set_irq(lpc->gsi[gsi], pic_level);
 229}
 230
 231/* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */
 232static int ich9_pirq_to_gsi(int pirq)
 233{
 234    return pirq + ICH9_LPC_PIC_NUM_PINS;
 235}
 236
 237static int ich9_gsi_to_pirq(int gsi)
 238{
 239    return gsi - ICH9_LPC_PIC_NUM_PINS;
 240}
 241
 242/* gsi: ioapic irq 16-23, otherwise assert */
 243static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi)
 244{
 245    int level = 0;
 246
 247    assert(gsi >= ICH9_LPC_PIC_NUM_PINS);
 248
 249    level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi));
 250    if (gsi == lpc->sci_gsi) {
 251        level |= lpc->sci_level;
 252    }
 253
 254    qemu_set_irq(lpc->gsi[gsi], level);
 255}
 256
 257void ich9_lpc_set_irq(void *opaque, int pirq, int level)
 258{
 259    ICH9LPCState *lpc = opaque;
 260    int pic_irq, pic_dis;
 261
 262    assert(0 <= pirq);
 263    assert(pirq < ICH9_LPC_NB_PIRQS);
 264
 265    ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq));
 266    ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis);
 267    ich9_lpc_update_pic(lpc, pic_irq);
 268}
 269
 270/* return the pirq number (PIRQ[A-H]:0-7) corresponding to
 271 * a given device irq pin.
 272 */
 273int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
 274{
 275    BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
 276    PCIBus *pci_bus = PCI_BUS(bus);
 277    PCIDevice *lpc_pdev =
 278            pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)];
 279    ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev);
 280
 281    return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
 282}
 283
 284PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
 285{
 286    ICH9LPCState *lpc = opaque;
 287    PCIINTxRoute route;
 288    int pic_irq;
 289    int pic_dis;
 290
 291    assert(0 <= pirq_pin);
 292    assert(pirq_pin < ICH9_LPC_NB_PIRQS);
 293
 294    route.mode = PCI_INTX_ENABLED;
 295    ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis);
 296    if (!pic_dis) {
 297        if (pic_irq < ICH9_LPC_PIC_NUM_PINS) {
 298            route.irq = pic_irq;
 299        } else {
 300            route.mode = PCI_INTX_DISABLED;
 301            route.irq = -1;
 302        }
 303    } else {
 304        route.irq = ich9_pirq_to_gsi(pirq_pin);
 305    }
 306
 307    return route;
 308}
 309
 310void ich9_generate_smi(void)
 311{
 312    cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
 313}
 314
 315static int ich9_lpc_sci_irq(ICH9LPCState *lpc)
 316{
 317    switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] &
 318            ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) {
 319    case ICH9_LPC_ACPI_CTRL_9:
 320        return 9;
 321    case ICH9_LPC_ACPI_CTRL_10:
 322        return 10;
 323    case ICH9_LPC_ACPI_CTRL_11:
 324        return 11;
 325    case ICH9_LPC_ACPI_CTRL_20:
 326        return 20;
 327    case ICH9_LPC_ACPI_CTRL_21:
 328        return 21;
 329    default:
 330        /* reserved */
 331        break;
 332    }
 333    return -1;
 334}
 335
 336static void ich9_set_sci(void *opaque, int irq_num, int level)
 337{
 338    ICH9LPCState *lpc = opaque;
 339    int irq;
 340
 341    assert(irq_num == 0);
 342    level = !!level;
 343    if (level == lpc->sci_level) {
 344        return;
 345    }
 346    lpc->sci_level = level;
 347
 348    irq = lpc->sci_gsi;
 349    if (irq < 0) {
 350        return;
 351    }
 352
 353    if (irq >= ICH9_LPC_PIC_NUM_PINS) {
 354        ich9_lpc_update_apic(lpc, irq);
 355    } else {
 356        ich9_lpc_update_pic(lpc, irq);
 357    }
 358}
 359
 360static void smi_features_ok_callback(void *opaque)
 361{
 362    ICH9LPCState *lpc = opaque;
 363    uint64_t guest_features;
 364
 365    if (lpc->smi_features_ok) {
 366        /* negotiation already complete, features locked */
 367        return;
 368    }
 369
 370    memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features);
 371    le64_to_cpus(&guest_features);
 372    if (guest_features & ~lpc->smi_host_features) {
 373        /* guest requests invalid features, leave @features_ok at zero */
 374        return;
 375    }
 376
 377    /* valid feature subset requested, lock it down, report success */
 378    lpc->smi_negotiated_features = guest_features;
 379    lpc->smi_features_ok = 1;
 380}
 381
 382void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled)
 383{
 384    ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
 385    qemu_irq sci_irq;
 386    FWCfgState *fw_cfg = fw_cfg_find();
 387
 388    sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0);
 389    ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq);
 390
 391    if (lpc->smi_host_features && fw_cfg) {
 392        uint64_t host_features_le;
 393
 394        host_features_le = cpu_to_le64(lpc->smi_host_features);
 395        memcpy(lpc->smi_host_features_le, &host_features_le,
 396               sizeof host_features_le);
 397        fw_cfg_add_file(fw_cfg, "etc/smi/supported-features",
 398                        lpc->smi_host_features_le,
 399                        sizeof lpc->smi_host_features_le);
 400
 401        /* The other two guest-visible fields are cleared on device reset, we
 402         * just link them into fw_cfg here.
 403         */
 404        fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features",
 405                                 NULL, NULL, NULL,
 406                                 lpc->smi_guest_features_le,
 407                                 sizeof lpc->smi_guest_features_le,
 408                                 false);
 409        fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok",
 410                                 smi_features_ok_callback, NULL, lpc,
 411                                 &lpc->smi_features_ok,
 412                                 sizeof lpc->smi_features_ok,
 413                                 true);
 414    }
 415
 416    ich9_lpc_reset(DEVICE(lpc));
 417}
 418
 419/* APM */
 420
 421static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
 422{
 423    ICH9LPCState *lpc = arg;
 424
 425    /* ACPI specs 3.0, 4.7.2.5 */
 426    acpi_pm1_cnt_update(&lpc->pm.acpi_regs,
 427                        val == ICH9_APM_ACPI_ENABLE,
 428                        val == ICH9_APM_ACPI_DISABLE);
 429    if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) {
 430        return;
 431    }
 432
 433    /* SMI_EN = PMBASE + 30. SMI control and enable register */
 434    if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) {
 435        if (lpc->smi_negotiated_features &
 436            (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) {
 437            CPUState *cs;
 438            CPU_FOREACH(cs) {
 439                cpu_interrupt(cs, CPU_INTERRUPT_SMI);
 440            }
 441        } else {
 442            cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI);
 443        }
 444    }
 445}
 446
 447/* config:PMBASE */
 448static void
 449ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc)
 450{
 451    uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE);
 452    uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL);
 453    uint8_t new_gsi;
 454
 455    if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) {
 456        pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK;
 457    } else {
 458        pm_io_base = 0;
 459    }
 460
 461    ich9_pm_iospace_update(&lpc->pm, pm_io_base);
 462
 463    new_gsi = ich9_lpc_sci_irq(lpc);
 464    if (lpc->sci_level && new_gsi != lpc->sci_gsi) {
 465        qemu_set_irq(lpc->pm.irq, 0);
 466        lpc->sci_gsi = new_gsi;
 467        qemu_set_irq(lpc->pm.irq, 1);
 468    }
 469    lpc->sci_gsi = new_gsi;
 470}
 471
 472/* config:RCBA */
 473static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old)
 474{
 475    uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA);
 476
 477    if (rcba_old & ICH9_LPC_RCBA_EN) {
 478        memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem);
 479    }
 480    if (rcba & ICH9_LPC_RCBA_EN) {
 481        memory_region_add_subregion_overlap(get_system_memory(),
 482                                            rcba & ICH9_LPC_RCBA_BA_MASK,
 483                                            &lpc->rcrb_mem, 1);
 484    }
 485}
 486
 487/* config:GEN_PMCON* */
 488static void
 489ich9_lpc_pmcon_update(ICH9LPCState *lpc)
 490{
 491    uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1);
 492    uint16_t wmask;
 493
 494    if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) {
 495        wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1);
 496        wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK;
 497        pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask);
 498        lpc->pm.smi_en_wmask &= ~1;
 499    }
 500}
 501
 502static int ich9_lpc_post_load(void *opaque, int version_id)
 503{
 504    ICH9LPCState *lpc = opaque;
 505
 506    ich9_lpc_pmbase_sci_update(lpc);
 507    ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */);
 508    ich9_lpc_pmcon_update(lpc);
 509    return 0;
 510}
 511
 512static void ich9_lpc_config_write(PCIDevice *d,
 513                                  uint32_t addr, uint32_t val, int len)
 514{
 515    ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
 516    uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA);
 517
 518    pci_default_write_config(d, addr, val, len);
 519    if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) ||
 520        ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) {
 521        ich9_lpc_pmbase_sci_update(lpc);
 522    }
 523    if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) {
 524        ich9_lpc_rcba_update(lpc, rcba_old);
 525    }
 526    if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) {
 527        pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
 528    }
 529    if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) {
 530        pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
 531    }
 532    if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) {
 533        ich9_lpc_pmcon_update(lpc);
 534    }
 535}
 536
 537static void ich9_lpc_reset(DeviceState *qdev)
 538{
 539    PCIDevice *d = PCI_DEVICE(qdev);
 540    ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
 541    uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA);
 542    int i;
 543
 544    for (i = 0; i < 4; i++) {
 545        pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i,
 546                     ICH9_LPC_PIRQ_ROUT_DEFAULT);
 547    }
 548    for (i = 0; i < 4; i++) {
 549        pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i,
 550                     ICH9_LPC_PIRQ_ROUT_DEFAULT);
 551    }
 552    pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT);
 553
 554    pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT);
 555    pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT);
 556
 557    ich9_cc_reset(lpc);
 558
 559    ich9_lpc_pmbase_sci_update(lpc);
 560    ich9_lpc_rcba_update(lpc, rcba_old);
 561
 562    lpc->sci_level = 0;
 563    lpc->rst_cnt = 0;
 564
 565    memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le);
 566    lpc->smi_features_ok = 0;
 567    lpc->smi_negotiated_features = 0;
 568}
 569
 570/* root complex register block is mapped into memory space */
 571static const MemoryRegionOps rcrb_mmio_ops = {
 572    .read = ich9_cc_read,
 573    .write = ich9_cc_write,
 574    .endianness = DEVICE_LITTLE_ENDIAN,
 575};
 576
 577static void ich9_lpc_machine_ready(Notifier *n, void *opaque)
 578{
 579    ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready);
 580    MemoryRegion *io_as = pci_address_space_io(&s->d);
 581    uint8_t *pci_conf;
 582
 583    pci_conf = s->d.config;
 584    if (memory_region_present(io_as, 0x3f8)) {
 585        /* com1 */
 586        pci_conf[0x82] |= 0x01;
 587    }
 588    if (memory_region_present(io_as, 0x2f8)) {
 589        /* com2 */
 590        pci_conf[0x82] |= 0x02;
 591    }
 592    if (memory_region_present(io_as, 0x378)) {
 593        /* lpt */
 594        pci_conf[0x82] |= 0x04;
 595    }
 596    if (memory_region_present(io_as, 0x3f2)) {
 597        /* floppy */
 598        pci_conf[0x82] |= 0x08;
 599    }
 600}
 601
 602/* reset control */
 603static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val,
 604                               unsigned len)
 605{
 606    ICH9LPCState *lpc = opaque;
 607
 608    if (val & 4) {
 609        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 610        return;
 611    }
 612    lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */
 613}
 614
 615static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len)
 616{
 617    ICH9LPCState *lpc = opaque;
 618
 619    return lpc->rst_cnt;
 620}
 621
 622static const MemoryRegionOps ich9_rst_cnt_ops = {
 623    .read = ich9_rst_cnt_read,
 624    .write = ich9_rst_cnt_write,
 625    .endianness = DEVICE_LITTLE_ENDIAN
 626};
 627
 628static void ich9_lpc_initfn(Object *obj)
 629{
 630    ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
 631
 632    static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
 633    static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
 634
 635    object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT,
 636                                  &lpc->sci_gsi, OBJ_PROP_FLAG_READ, NULL);
 637    object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD,
 638                                  &acpi_enable_cmd, OBJ_PROP_FLAG_READ, NULL);
 639    object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD,
 640                                  &acpi_disable_cmd, OBJ_PROP_FLAG_READ, NULL);
 641
 642    ich9_pm_add_properties(obj, &lpc->pm, NULL);
 643}
 644
 645static void ich9_lpc_realize(PCIDevice *d, Error **errp)
 646{
 647    ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
 648    DeviceState *dev = DEVICE(d);
 649    ISABus *isa_bus;
 650
 651    isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(),
 652                          errp);
 653    if (!isa_bus) {
 654        return;
 655    }
 656
 657    pci_set_long(d->wmask + ICH9_LPC_PMBASE,
 658                 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
 659    pci_set_byte(d->wmask + ICH9_LPC_PMBASE,
 660                 ICH9_LPC_ACPI_CTRL_ACPI_EN |
 661                 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK);
 662
 663    memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc,
 664                          "lpc-rcrb-mmio", ICH9_CC_SIZE);
 665
 666    lpc->isa_bus = isa_bus;
 667
 668    ich9_cc_init(lpc);
 669    apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc);
 670
 671    lpc->machine_ready.notify = ich9_lpc_machine_ready;
 672    qemu_add_machine_init_done_notifier(&lpc->machine_ready);
 673
 674    memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc,
 675                          "lpc-reset-control", 1);
 676    memory_region_add_subregion_overlap(pci_address_space_io(d),
 677                                        ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem,
 678                                        1);
 679
 680    qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS);
 681
 682    isa_bus_irqs(isa_bus, lpc->gsi);
 683}
 684
 685static bool ich9_rst_cnt_needed(void *opaque)
 686{
 687    ICH9LPCState *lpc = opaque;
 688
 689    return (lpc->rst_cnt != 0);
 690}
 691
 692static const VMStateDescription vmstate_ich9_rst_cnt = {
 693    .name = "ICH9LPC/rst_cnt",
 694    .version_id = 1,
 695    .minimum_version_id = 1,
 696    .needed = ich9_rst_cnt_needed,
 697    .fields = (VMStateField[]) {
 698        VMSTATE_UINT8(rst_cnt, ICH9LPCState),
 699        VMSTATE_END_OF_LIST()
 700    }
 701};
 702
 703static bool ich9_smi_feat_needed(void *opaque)
 704{
 705    ICH9LPCState *lpc = opaque;
 706
 707    return !buffer_is_zero(lpc->smi_guest_features_le,
 708                           sizeof lpc->smi_guest_features_le) ||
 709           lpc->smi_features_ok;
 710}
 711
 712static const VMStateDescription vmstate_ich9_smi_feat = {
 713    .name = "ICH9LPC/smi_feat",
 714    .version_id = 1,
 715    .minimum_version_id = 1,
 716    .needed = ich9_smi_feat_needed,
 717    .fields = (VMStateField[]) {
 718        VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState,
 719                            sizeof(uint64_t)),
 720        VMSTATE_UINT8(smi_features_ok, ICH9LPCState),
 721        VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState),
 722        VMSTATE_END_OF_LIST()
 723    }
 724};
 725
 726static const VMStateDescription vmstate_ich9_lpc = {
 727    .name = "ICH9LPC",
 728    .version_id = 1,
 729    .minimum_version_id = 1,
 730    .post_load = ich9_lpc_post_load,
 731    .fields = (VMStateField[]) {
 732        VMSTATE_PCI_DEVICE(d, ICH9LPCState),
 733        VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState),
 734        VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs),
 735        VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE),
 736        VMSTATE_UINT32(sci_level, ICH9LPCState),
 737        VMSTATE_END_OF_LIST()
 738    },
 739    .subsections = (const VMStateDescription*[]) {
 740        &vmstate_ich9_rst_cnt,
 741        &vmstate_ich9_smi_feat,
 742        NULL
 743    }
 744};
 745
 746static Property ich9_lpc_properties[] = {
 747    DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true),
 748    DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features,
 749                      ICH9_LPC_SMI_F_BROADCAST_BIT, true),
 750    DEFINE_PROP_END_OF_LIST(),
 751};
 752
 753static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
 754{
 755    ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
 756
 757    acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev);
 758}
 759
 760static void ich9_lpc_class_init(ObjectClass *klass, void *data)
 761{
 762    DeviceClass *dc = DEVICE_CLASS(klass);
 763    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 764    HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 765    AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
 766
 767    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 768    dc->reset = ich9_lpc_reset;
 769    k->realize = ich9_lpc_realize;
 770    dc->vmsd = &vmstate_ich9_lpc;
 771    device_class_set_props(dc, ich9_lpc_properties);
 772    k->config_write = ich9_lpc_config_write;
 773    dc->desc = "ICH9 LPC bridge";
 774    k->vendor_id = PCI_VENDOR_ID_INTEL;
 775    k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8;
 776    k->revision = ICH9_A2_LPC_REVISION;
 777    k->class_id = PCI_CLASS_BRIDGE_ISA;
 778    /*
 779     * Reason: part of ICH9 southbridge, needs to be wired up by
 780     * pc_q35_init()
 781     */
 782    dc->user_creatable = false;
 783    hc->pre_plug = ich9_pm_device_pre_plug_cb;
 784    hc->plug = ich9_pm_device_plug_cb;
 785    hc->unplug_request = ich9_pm_device_unplug_request_cb;
 786    hc->unplug = ich9_pm_device_unplug_cb;
 787    adevc->ospm_status = ich9_pm_ospm_status;
 788    adevc->send_event = ich9_send_gpe;
 789    adevc->madt_cpu = pc_madt_cpu_entry;
 790}
 791
 792static const TypeInfo ich9_lpc_info = {
 793    .name       = TYPE_ICH9_LPC_DEVICE,
 794    .parent     = TYPE_PCI_DEVICE,
 795    .instance_size = sizeof(struct ICH9LPCState),
 796    .instance_init = ich9_lpc_initfn,
 797    .class_init  = ich9_lpc_class_init,
 798    .interfaces = (InterfaceInfo[]) {
 799        { TYPE_HOTPLUG_HANDLER },
 800        { TYPE_ACPI_DEVICE_IF },
 801        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 802        { }
 803    }
 804};
 805
 806static void ich9_lpc_register(void)
 807{
 808    type_register_static(&ich9_lpc_info);
 809}
 810
 811type_init(ich9_lpc_register);
 812