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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "hw/pci/pci_bridge.h"
24#include "hw/pci/pcie.h"
25#include "hw/pci/msix.h"
26#include "hw/pci/msi.h"
27#include "hw/pci/pci_bus.h"
28#include "hw/pci/pcie_regs.h"
29#include "hw/pci/pcie_port.h"
30#include "qemu/range.h"
31
32
33#ifdef DEBUG_PCIE
34# define PCIE_DPRINTF(fmt, ...) \
35 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
36#else
37# define PCIE_DPRINTF(fmt, ...) do {} while (0)
38#endif
39#define PCIE_DEV_PRINTF(dev, fmt, ...) \
40 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
41
42
43
44
45
46
47static void
48pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version)
49{
50 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
51 uint8_t *cmask = dev->cmask + dev->exp.exp_cap;
52
53
54
55 pci_set_word(exp_cap + PCI_EXP_FLAGS,
56 ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) |
57 version);
58
59
60
61
62
63
64
65
66 pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
67
68 pci_set_long(exp_cap + PCI_EXP_LNKCAP,
69 (port << PCI_EXP_LNKCAP_PN_SHIFT) |
70 PCI_EXP_LNKCAP_ASPMS_0S |
71 QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1) |
72 QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT));
73
74 pci_set_word(exp_cap + PCI_EXP_LNKSTA,
75 QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1) |
76 QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT));
77
78 if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) {
79 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
80 PCI_EXP_LNKSTA_DLLLA);
81 }
82
83
84
85
86
87 pci_set_word(cmask + PCI_EXP_LNKSTA, 0);
88}
89
90static void pcie_cap_fill_slot_lnk(PCIDevice *dev)
91{
92 PCIESlot *s = (PCIESlot *)object_dynamic_cast(OBJECT(dev), TYPE_PCIE_SLOT);
93 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
94
95
96 if (!s) {
97 return;
98 }
99
100
101 pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP,
102 PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS);
103 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP,
104 QEMU_PCI_EXP_LNKCAP_MLW(s->width) |
105 QEMU_PCI_EXP_LNKCAP_MLS(s->speed));
106
107
108
109
110
111
112 if (s->width > QEMU_PCI_EXP_LNK_X1 ||
113 s->speed > QEMU_PCI_EXP_LNK_2_5GT) {
114 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP,
115 PCI_EXP_LNKCAP_LBNC);
116 }
117
118 if (s->speed > QEMU_PCI_EXP_LNK_2_5GT) {
119
120
121
122
123
124
125
126 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP,
127 PCI_EXP_LNKCAP_DLLLARC);
128 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
129 PCI_EXP_LNKSTA_DLLLA);
130
131
132
133
134
135 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKCTL2,
136 PCI_EXP_LNKCTL2_TLS);
137 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKCTL2,
138 QEMU_PCI_EXP_LNKCAP_MLS(s->speed) &
139 PCI_EXP_LNKCTL2_TLS);
140 }
141
142
143
144
145
146
147 if (s->speed > QEMU_PCI_EXP_LNK_5GT) {
148 pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP2, ~0U);
149 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2,
150 PCI_EXP_LNKCAP2_SLS_2_5GB |
151 PCI_EXP_LNKCAP2_SLS_5_0GB |
152 PCI_EXP_LNKCAP2_SLS_8_0GB);
153 if (s->speed > QEMU_PCI_EXP_LNK_8GT) {
154 pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2,
155 PCI_EXP_LNKCAP2_SLS_16_0GB);
156 }
157 }
158}
159
160int pcie_cap_init(PCIDevice *dev, uint8_t offset,
161 uint8_t type, uint8_t port,
162 Error **errp)
163{
164
165 int pos;
166 uint8_t *exp_cap;
167
168 assert(pci_is_express(dev));
169
170 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
171 PCI_EXP_VER2_SIZEOF, errp);
172 if (pos < 0) {
173 return pos;
174 }
175 dev->exp.exp_cap = pos;
176 exp_cap = dev->config + pos;
177
178
179 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER2);
180
181
182 pcie_cap_fill_slot_lnk(dev);
183
184
185 pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
186 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
187
188 pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);
189
190 if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) {
191
192 pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0);
193 }
194
195 return pos;
196}
197
198int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type,
199 uint8_t port)
200{
201
202 int pos;
203 Error *local_err = NULL;
204
205 assert(pci_is_express(dev));
206
207 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
208 PCI_EXP_VER1_SIZEOF, &local_err);
209 if (pos < 0) {
210 error_report_err(local_err);
211 return pos;
212 }
213 dev->exp.exp_cap = pos;
214
215 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1);
216
217 return pos;
218}
219
220static int
221pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size)
222{
223 uint8_t type = PCI_EXP_TYPE_ENDPOINT;
224 Error *local_err = NULL;
225 int ret;
226
227
228
229
230
231
232 if (pci_bus_is_express(pci_get_bus(dev))
233 && pci_bus_is_root(pci_get_bus(dev))) {
234 type = PCI_EXP_TYPE_RC_END;
235 }
236
237 if (cap_size == PCI_EXP_VER1_SIZEOF) {
238 return pcie_cap_v1_init(dev, offset, type, 0);
239 } else {
240 ret = pcie_cap_init(dev, offset, type, 0, &local_err);
241
242 if (ret < 0) {
243 error_report_err(local_err);
244 }
245
246 return ret;
247 }
248}
249
250int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset)
251{
252 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF);
253}
254
255int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset)
256{
257 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF);
258}
259
260void pcie_cap_exit(PCIDevice *dev)
261{
262 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF);
263}
264
265void pcie_cap_v1_exit(PCIDevice *dev)
266{
267 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF);
268}
269
270uint8_t pcie_cap_get_type(const PCIDevice *dev)
271{
272 uint32_t pos = dev->exp.exp_cap;
273 assert(pos > 0);
274 return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) &
275 PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT;
276}
277
278
279
280
281void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector)
282{
283 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
284 assert(vector < 32);
285 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ);
286 pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS,
287 vector << PCI_EXP_FLAGS_IRQ_SHIFT);
288}
289
290uint8_t pcie_cap_flags_get_vector(PCIDevice *dev)
291{
292 return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) &
293 PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT;
294}
295
296void pcie_cap_deverr_init(PCIDevice *dev)
297{
298 uint32_t pos = dev->exp.exp_cap;
299 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP,
300 PCI_EXP_DEVCAP_RBER);
301 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL,
302 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
303 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
304 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA,
305 PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
306 PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD);
307}
308
309void pcie_cap_deverr_reset(PCIDevice *dev)
310{
311 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
312 pci_long_test_and_clear_mask(devctl,
313 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
314 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
315}
316
317void pcie_cap_lnkctl_init(PCIDevice *dev)
318{
319 uint32_t pos = dev->exp.exp_cap;
320 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL,
321 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);
322}
323
324void pcie_cap_lnkctl_reset(PCIDevice *dev)
325{
326 uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL;
327 pci_long_test_and_clear_mask(lnkctl,
328 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);
329}
330
331static void hotplug_event_update_event_status(PCIDevice *dev)
332{
333 uint32_t pos = dev->exp.exp_cap;
334 uint8_t *exp_cap = dev->config + pos;
335 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
336 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
337
338 dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) &&
339 (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED);
340}
341
342static void hotplug_event_notify(PCIDevice *dev)
343{
344 bool prev = dev->exp.hpev_notified;
345
346 hotplug_event_update_event_status(dev);
347
348 if (prev == dev->exp.hpev_notified) {
349 return;
350 }
351
352
353
354
355
356
357
358 if (msix_enabled(dev)) {
359 msix_notify(dev, pcie_cap_flags_get_vector(dev));
360 } else if (msi_enabled(dev)) {
361 msi_notify(dev, pcie_cap_flags_get_vector(dev));
362 } else {
363 pci_set_irq(dev, dev->exp.hpev_notified);
364 }
365}
366
367static void hotplug_event_clear(PCIDevice *dev)
368{
369 hotplug_event_update_event_status(dev);
370 if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
371 pci_irq_deassert(dev);
372 }
373}
374
375
376
377
378
379
380
381
382static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event)
383{
384
385 if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap +
386 PCI_EXP_SLTSTA, event) == event) {
387 return;
388 }
389 hotplug_event_notify(dev);
390}
391
392static void pcie_cap_slot_plug_common(PCIDevice *hotplug_dev, DeviceState *dev,
393 Error **errp)
394{
395 uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap;
396 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
397
398 PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta);
399 if (sltsta & PCI_EXP_SLTSTA_EIS) {
400
401
402
403 error_setg_errno(errp, EBUSY, "slot is electromechanically locked");
404 }
405}
406
407void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
408 Error **errp)
409{
410 pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, errp);
411}
412
413void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
414 Error **errp)
415{
416 PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev);
417 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap;
418 PCIDevice *pci_dev = PCI_DEVICE(dev);
419
420
421
422
423 if (!dev->hotplugged) {
424 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
425 PCI_EXP_SLTSTA_PDS);
426 if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) {
427 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
428 PCI_EXP_LNKSTA_DLLLA);
429 }
430 return;
431 }
432
433
434
435
436
437 if (pci_get_function_0(pci_dev)) {
438 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
439 PCI_EXP_SLTSTA_PDS);
440 if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) {
441 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
442 PCI_EXP_LNKSTA_DLLLA);
443 }
444 pcie_cap_slot_event(PCI_DEVICE(hotplug_dev),
445 PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP);
446 }
447}
448
449void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
450 Error **errp)
451{
452 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
453}
454
455static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque)
456{
457 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(DEVICE(dev));
458
459 if (dev->partially_hotplugged) {
460 dev->qdev.pending_deleted_event = false;
461 return;
462 }
463 hotplug_handler_unplug(hotplug_ctrl, DEVICE(dev), &error_abort);
464 object_unparent(OBJECT(dev));
465}
466
467void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
468 DeviceState *dev, Error **errp)
469{
470 Error *local_err = NULL;
471 PCIDevice *pci_dev = PCI_DEVICE(dev);
472 PCIBus *bus = pci_get_bus(pci_dev);
473
474 pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, &local_err);
475 if (local_err) {
476 error_propagate(errp, local_err);
477 return;
478 }
479
480 dev->pending_deleted_event = true;
481
482
483
484
485
486 if (pci_dev->devfn &&
487 !bus->devices[0]) {
488 pcie_unplug_device(bus, pci_dev, NULL);
489
490 return;
491 }
492
493 pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev));
494}
495
496
497
498void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s)
499{
500 uint32_t pos = dev->exp.exp_cap;
501
502 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
503 PCI_EXP_FLAGS_SLOT);
504
505 pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
506 ~PCI_EXP_SLTCAP_PSN);
507 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
508 (s->slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
509 PCI_EXP_SLTCAP_EIP |
510 PCI_EXP_SLTCAP_PIP |
511 PCI_EXP_SLTCAP_AIP |
512 PCI_EXP_SLTCAP_ABP);
513 if (s->hotplug) {
514 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
515 PCI_EXP_SLTCAP_HPS |
516 PCI_EXP_SLTCAP_HPC);
517 }
518
519 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
520 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
521 PCI_EXP_SLTCAP_PCP);
522 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
523 PCI_EXP_SLTCTL_PCC);
524 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
525 PCI_EXP_SLTCTL_PCC);
526 }
527
528 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
529 PCI_EXP_SLTCTL_PIC |
530 PCI_EXP_SLTCTL_AIC);
531 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL,
532 PCI_EXP_SLTCTL_PIC_OFF |
533 PCI_EXP_SLTCTL_AIC_OFF);
534 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
535 PCI_EXP_SLTCTL_PIC |
536 PCI_EXP_SLTCTL_AIC |
537 PCI_EXP_SLTCTL_HPIE |
538 PCI_EXP_SLTCTL_CCIE |
539 PCI_EXP_SLTCTL_PDCE |
540 PCI_EXP_SLTCTL_ABPE);
541
542
543
544
545
546 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
547 PCI_EXP_SLTCTL_EIC);
548
549 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA,
550 PCI_EXP_HP_EV_SUPPORTED);
551
552 dev->exp.hpev_notified = false;
553
554 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))),
555 OBJECT(dev), NULL);
556}
557
558void pcie_cap_slot_reset(PCIDevice *dev)
559{
560 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
561 uint8_t port_type = pcie_cap_get_type(dev);
562
563 assert(port_type == PCI_EXP_TYPE_DOWNSTREAM ||
564 port_type == PCI_EXP_TYPE_ROOT_PORT);
565
566 PCIE_DEV_PRINTF(dev, "reset\n");
567
568 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
569 PCI_EXP_SLTCTL_EIC |
570 PCI_EXP_SLTCTL_PIC |
571 PCI_EXP_SLTCTL_AIC |
572 PCI_EXP_SLTCTL_HPIE |
573 PCI_EXP_SLTCTL_CCIE |
574 PCI_EXP_SLTCTL_PDCE |
575 PCI_EXP_SLTCTL_ABPE);
576 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
577 PCI_EXP_SLTCTL_AIC_OFF);
578
579 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
580
581 bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0];
582 uint16_t pic;
583
584 if (populated) {
585 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
586 PCI_EXP_SLTCTL_PCC);
587 } else {
588 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
589 PCI_EXP_SLTCTL_PCC);
590 }
591
592 pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF;
593 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic);
594 }
595
596 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
597 PCI_EXP_SLTSTA_EIS |
598
599 PCI_EXP_SLTSTA_CC |
600 PCI_EXP_SLTSTA_PDC |
601 PCI_EXP_SLTSTA_ABP);
602
603 hotplug_event_update_event_status(dev);
604}
605
606void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta)
607{
608 uint32_t pos = dev->exp.exp_cap;
609 uint8_t *exp_cap = dev->config + pos;
610 *slt_ctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
611 *slt_sta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
612}
613
614void pcie_cap_slot_write_config(PCIDevice *dev,
615 uint16_t old_slt_ctl, uint16_t old_slt_sta,
616 uint32_t addr, uint32_t val, int len)
617{
618 uint32_t pos = dev->exp.exp_cap;
619 uint8_t *exp_cap = dev->config + pos;
620 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
621
622 if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) {
623
624
625
626
627
628
629
630
631
632
633
634#define PCIE_SLOT_EVENTS (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | \
635 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | \
636 PCI_EXP_SLTSTA_CC)
637
638 if (val & ~old_slt_sta & PCIE_SLOT_EVENTS) {
639 sltsta = (sltsta & ~PCIE_SLOT_EVENTS) | (old_slt_sta & PCIE_SLOT_EVENTS);
640 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
641 }
642 hotplug_event_clear(dev);
643 }
644
645 if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
646 return;
647 }
648
649 if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
650 PCI_EXP_SLTCTL_EIC)) {
651 sltsta ^= PCI_EXP_SLTSTA_EIS;
652 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
653 PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: "
654 "sltsta -> 0x%02"PRIx16"\n",
655 sltsta);
656 }
657
658
659
660
661
662
663
664
665
666 if ((sltsta & PCI_EXP_SLTSTA_PDS) && (val & PCI_EXP_SLTCTL_PCC) &&
667 (val & PCI_EXP_SLTCTL_PIC_OFF) == PCI_EXP_SLTCTL_PIC_OFF &&
668 (!(old_slt_ctl & PCI_EXP_SLTCTL_PCC) ||
669 (old_slt_ctl & PCI_EXP_SLTCTL_PIC_OFF) != PCI_EXP_SLTCTL_PIC_OFF)) {
670 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
671 pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
672 pcie_unplug_device, NULL);
673
674 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
675 PCI_EXP_SLTSTA_PDS);
676 if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) {
677 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA,
678 PCI_EXP_LNKSTA_DLLLA);
679 }
680 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
681 PCI_EXP_SLTSTA_PDC);
682 }
683
684 hotplug_event_notify(dev);
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
703}
704
705int pcie_cap_slot_post_load(void *opaque, int version_id)
706{
707 PCIDevice *dev = opaque;
708 hotplug_event_update_event_status(dev);
709 return 0;
710}
711
712void pcie_cap_slot_push_attention_button(PCIDevice *dev)
713{
714 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP);
715}
716
717
718void pcie_cap_root_init(PCIDevice *dev)
719{
720 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL,
721 PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
722 PCI_EXP_RTCTL_SEFEE);
723}
724
725void pcie_cap_root_reset(PCIDevice *dev)
726{
727 pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
728}
729
730
731void pcie_cap_flr_init(PCIDevice *dev)
732{
733 pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP,
734 PCI_EXP_DEVCAP_FLR);
735
736
737
738
739
740
741 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL,
742 PCI_EXP_DEVCTL_BCR_FLR);
743}
744
745void pcie_cap_flr_write_config(PCIDevice *dev,
746 uint32_t addr, uint32_t val, int len)
747{
748 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
749 if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) {
750
751
752 pci_device_reset(dev);
753 pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR);
754 }
755}
756
757
758
759
760void pcie_cap_arifwd_init(PCIDevice *dev)
761{
762 uint32_t pos = dev->exp.exp_cap;
763 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2,
764 PCI_EXP_DEVCAP2_ARI);
765 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2,
766 PCI_EXP_DEVCTL2_ARI);
767}
768
769void pcie_cap_arifwd_reset(PCIDevice *dev)
770{
771 uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2;
772 pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI);
773}
774
775bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev)
776{
777 if (!pci_is_express(dev)) {
778 return false;
779 }
780 if (!dev->exp.exp_cap) {
781 return false;
782 }
783
784 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
785 PCI_EXP_DEVCTL2_ARI;
786}
787
788
789
790
791
792
793
794
795
796
797static uint16_t pcie_find_capability_list(PCIDevice *dev, uint32_t cap_id,
798 uint16_t *prev_p)
799{
800 uint16_t prev = 0;
801 uint16_t next;
802 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE);
803
804 if (!header) {
805
806 next = 0;
807 goto out;
808 }
809 for (next = PCI_CONFIG_SPACE_SIZE; next;
810 prev = next, next = PCI_EXT_CAP_NEXT(header)) {
811
812 assert(next >= PCI_CONFIG_SPACE_SIZE);
813 assert(next <= PCIE_CONFIG_SPACE_SIZE - 8);
814
815 header = pci_get_long(dev->config + next);
816 if (PCI_EXT_CAP_ID(header) == cap_id) {
817 break;
818 }
819 }
820
821out:
822 if (prev_p) {
823 *prev_p = prev;
824 }
825 return next;
826}
827
828uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id)
829{
830 return pcie_find_capability_list(dev, cap_id, NULL);
831}
832
833static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next)
834{
835 uint32_t header = pci_get_long(dev->config + pos);
836 assert(!(next & (PCI_EXT_CAP_ALIGN - 1)));
837 header = (header & ~PCI_EXT_CAP_NEXT_MASK) |
838 ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK);
839 pci_set_long(dev->config + pos, header);
840}
841
842
843
844
845
846
847void pcie_add_capability(PCIDevice *dev,
848 uint16_t cap_id, uint8_t cap_ver,
849 uint16_t offset, uint16_t size)
850{
851 assert(offset >= PCI_CONFIG_SPACE_SIZE);
852 assert(offset < offset + size);
853 assert(offset + size <= PCIE_CONFIG_SPACE_SIZE);
854 assert(size >= 8);
855 assert(pci_is_express(dev));
856
857 if (offset != PCI_CONFIG_SPACE_SIZE) {
858 uint16_t prev;
859
860
861
862
863
864 pcie_find_capability_list(dev, 0xffffffff, &prev);
865 assert(prev >= PCI_CONFIG_SPACE_SIZE);
866 pcie_ext_cap_set_next(dev, prev, offset);
867 }
868 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0));
869
870
871 memset(dev->wmask + offset, 0, size);
872 memset(dev->w1cmask + offset, 0, size);
873
874 memset(dev->cmask + offset, 0xFF, size);
875}
876
877
878
879
880
881
882
883
884
885
886
887void pcie_sync_bridge_lnk(PCIDevice *bridge_dev)
888{
889 PCIBridge *br = PCI_BRIDGE(bridge_dev);
890 PCIBus *bus = pci_bridge_get_sec_bus(br);
891 PCIDevice *target = bus->devices[0];
892 uint8_t *exp_cap = bridge_dev->config + bridge_dev->exp.exp_cap;
893 uint16_t lnksta, lnkcap = pci_get_word(exp_cap + PCI_EXP_LNKCAP);
894
895 if (!target || !target->exp.exp_cap) {
896 lnksta = lnkcap;
897 } else {
898 lnksta = target->config_read(target,
899 target->exp.exp_cap + PCI_EXP_LNKSTA,
900 sizeof(lnksta));
901
902 if ((lnksta & PCI_EXP_LNKSTA_NLW) > (lnkcap & PCI_EXP_LNKCAP_MLW)) {
903 lnksta &= ~PCI_EXP_LNKSTA_NLW;
904 lnksta |= lnkcap & PCI_EXP_LNKCAP_MLW;
905 } else if (!(lnksta & PCI_EXP_LNKSTA_NLW)) {
906 lnksta |= QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1);
907 }
908
909 if ((lnksta & PCI_EXP_LNKSTA_CLS) > (lnkcap & PCI_EXP_LNKCAP_SLS)) {
910 lnksta &= ~PCI_EXP_LNKSTA_CLS;
911 lnksta |= lnkcap & PCI_EXP_LNKCAP_SLS;
912 } else if (!(lnksta & PCI_EXP_LNKSTA_CLS)) {
913 lnksta |= QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT);
914 }
915 }
916
917 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA,
918 PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW);
919 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, lnksta &
920 (PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW));
921}
922
923
924
925
926
927
928void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn)
929{
930 pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER,
931 offset, PCI_ARI_SIZEOF);
932 pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8);
933}
934
935void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num)
936{
937 static const int pci_dsn_ver = 1;
938 static const int pci_dsn_cap = 4;
939
940 pcie_add_capability(dev, PCI_EXT_CAP_ID_DSN, pci_dsn_ver, offset,
941 PCI_EXT_CAP_DSN_SIZEOF);
942 pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num);
943}
944
945void pcie_ats_init(PCIDevice *dev, uint16_t offset)
946{
947 pcie_add_capability(dev, PCI_EXT_CAP_ID_ATS, 0x1,
948 offset, PCI_EXT_CAP_ATS_SIZEOF);
949
950 dev->exp.ats_cap = offset;
951
952
953 pci_set_word(dev->config + offset + PCI_ATS_CAP, 0);
954
955 pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0);
956
957 pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f);
958}
959
960
961void pcie_acs_init(PCIDevice *dev, uint16_t offset)
962{
963 bool is_downstream = pci_is_express_downstream_port(dev);
964 uint16_t cap_bits = 0;
965
966
967 assert(is_downstream ||
968 (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) ||
969 PCI_FUNC(dev->devfn));
970
971 pcie_add_capability(dev, PCI_EXT_CAP_ID_ACS, PCI_ACS_VER, offset,
972 PCI_ACS_SIZEOF);
973 dev->exp.acs_cap = offset;
974
975 if (is_downstream) {
976
977
978
979
980
981
982
983 cap_bits = PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
984 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT;
985 }
986
987 pci_set_word(dev->config + offset + PCI_ACS_CAP, cap_bits);
988 pci_set_word(dev->wmask + offset + PCI_ACS_CTRL, cap_bits);
989}
990
991void pcie_acs_reset(PCIDevice *dev)
992{
993 if (dev->exp.acs_cap) {
994 pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0);
995 }
996}
997