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26
27#include "qemu/osdep.h"
28#include "qemu-common.h"
29#include "qapi/error.h"
30#include "qapi/visitor.h"
31#include "sysemu/sysemu.h"
32#include "sysemu/hostmem.h"
33#include "sysemu/numa.h"
34#include "sysemu/qtest.h"
35#include "sysemu/reset.h"
36#include "sysemu/runstate.h"
37#include "qemu/log.h"
38#include "hw/fw-path-provider.h"
39#include "elf.h"
40#include "net/net.h"
41#include "sysemu/device_tree.h"
42#include "sysemu/cpus.h"
43#include "sysemu/hw_accel.h"
44#include "kvm_ppc.h"
45#include "migration/misc.h"
46#include "migration/qemu-file-types.h"
47#include "migration/global_state.h"
48#include "migration/register.h"
49#include "migration/blocker.h"
50#include "mmu-hash64.h"
51#include "mmu-book3s-v3.h"
52#include "cpu-models.h"
53#include "hw/core/cpu.h"
54
55#include "hw/boards.h"
56#include "hw/ppc/ppc.h"
57#include "hw/loader.h"
58
59#include "hw/ppc/fdt.h"
60#include "hw/ppc/spapr.h"
61#include "hw/ppc/spapr_vio.h"
62#include "hw/qdev-properties.h"
63#include "hw/pci-host/spapr.h"
64#include "hw/pci/msi.h"
65
66#include "hw/pci/pci.h"
67#include "hw/scsi/scsi.h"
68#include "hw/virtio/virtio-scsi.h"
69#include "hw/virtio/vhost-scsi-common.h"
70
71#include "exec/address-spaces.h"
72#include "exec/ram_addr.h"
73#include "hw/usb.h"
74#include "qemu/config-file.h"
75#include "qemu/error-report.h"
76#include "trace.h"
77#include "hw/nmi.h"
78#include "hw/intc/intc.h"
79
80#include "hw/ppc/spapr_cpu_core.h"
81#include "hw/mem/memory-device.h"
82#include "hw/ppc/spapr_tpm_proxy.h"
83#include "hw/ppc/spapr_nvdimm.h"
84
85#include "monitor/monitor.h"
86
87#include <libfdt.h>
88
89
90
91
92
93
94
95
96
97
98
99#define FDT_MAX_SIZE 0x100000
100#define RTAS_MAX_ADDR 0x80000000
101#define FW_MAX_SIZE 0x400000
102#define FW_FILE_NAME "slof.bin"
103#define FW_OVERHEAD 0x2800000
104#define KERNEL_LOAD_ADDR FW_MAX_SIZE
105
106#define MIN_RMA_SLOF (128 * MiB)
107
108#define PHANDLE_INTC 0x00001111
109
110
111
112
113
114static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index)
115{
116 MachineState *ms = MACHINE(spapr);
117 unsigned int smp_threads = ms->smp.threads;
118
119 assert(spapr->vsmt);
120 return
121 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
122}
123static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr,
124 PowerPCCPU *cpu)
125{
126 assert(spapr->vsmt);
127 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
128}
129
130static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
131{
132
133
134
135
136 return false;
137}
138
139static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
140 .name = "icp/server",
141 .version_id = 1,
142 .minimum_version_id = 1,
143 .needed = pre_2_10_vmstate_dummy_icp_needed,
144 .fields = (VMStateField[]) {
145 VMSTATE_UNUSED(4),
146 VMSTATE_UNUSED(1),
147 VMSTATE_UNUSED(1),
148 VMSTATE_END_OF_LIST()
149 },
150};
151
152static void pre_2_10_vmstate_register_dummy_icp(int i)
153{
154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
155 (void *)(uintptr_t) i);
156}
157
158static void pre_2_10_vmstate_unregister_dummy_icp(int i)
159{
160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
161 (void *)(uintptr_t) i);
162}
163
164int spapr_max_server_number(SpaprMachineState *spapr)
165{
166 MachineState *ms = MACHINE(spapr);
167
168 assert(spapr->vsmt);
169 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads);
170}
171
172static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
173 int smt_threads)
174{
175 int i, ret = 0;
176 uint32_t servers_prop[smt_threads];
177 uint32_t gservers_prop[smt_threads * 2];
178 int index = spapr_get_vcpu_id(cpu);
179
180 if (cpu->compat_pvr) {
181 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
182 if (ret < 0) {
183 return ret;
184 }
185 }
186
187
188 for (i = 0; i < smt_threads; i++) {
189 servers_prop[i] = cpu_to_be32(index + i);
190
191 gservers_prop[i*2] = cpu_to_be32(index + i);
192 gservers_prop[i*2 + 1] = 0;
193 }
194 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
195 servers_prop, sizeof(servers_prop));
196 if (ret < 0) {
197 return ret;
198 }
199 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
200 gservers_prop, sizeof(gservers_prop));
201
202 return ret;
203}
204
205static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
206{
207 int index = spapr_get_vcpu_id(cpu);
208 uint32_t associativity[] = {cpu_to_be32(0x5),
209 cpu_to_be32(0x0),
210 cpu_to_be32(0x0),
211 cpu_to_be32(0x0),
212 cpu_to_be32(cpu->node_id),
213 cpu_to_be32(index)};
214
215
216 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
217 sizeof(associativity));
218}
219
220static void spapr_dt_pa_features(SpaprMachineState *spapr,
221 PowerPCCPU *cpu,
222 void *fdt, int offset)
223{
224 uint8_t pa_features_206[] = { 6, 0,
225 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
226 uint8_t pa_features_207[] = { 24, 0,
227 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
228 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
229 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
230 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
231 uint8_t pa_features_300[] = { 66, 0,
232
233
234 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
235
236 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
237
238 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
239
240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
241
242 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
243
244 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00,
245
246 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
247
248 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
249
250 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
251
252 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
253
254 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
255 };
256 uint8_t *pa_features = NULL;
257 size_t pa_size;
258
259 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
260 pa_features = pa_features_206;
261 pa_size = sizeof(pa_features_206);
262 }
263 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
264 pa_features = pa_features_207;
265 pa_size = sizeof(pa_features_207);
266 }
267 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
268 pa_features = pa_features_300;
269 pa_size = sizeof(pa_features_300);
270 }
271 if (!pa_features) {
272 return;
273 }
274
275 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
276
277
278
279
280
281
282
283 pa_features[3] |= 0x20;
284 }
285 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
286 pa_features[24] |= 0x80;
287 }
288 if (spapr->cas_pre_isa3_guest && pa_size > 40) {
289
290
291
292 pa_features[40 + 2] &= ~0x80;
293 }
294
295 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
296}
297
298static hwaddr spapr_node0_size(MachineState *machine)
299{
300 if (machine->numa_state->num_nodes) {
301 int i;
302 for (i = 0; i < machine->numa_state->num_nodes; ++i) {
303 if (machine->numa_state->nodes[i].node_mem) {
304 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem),
305 machine->ram_size);
306 }
307 }
308 }
309 return machine->ram_size;
310}
311
312static void add_str(GString *s, const gchar *s1)
313{
314 g_string_append_len(s, s1, strlen(s1) + 1);
315}
316
317static int spapr_dt_memory_node(void *fdt, int nodeid, hwaddr start,
318 hwaddr size)
319{
320 uint32_t associativity[] = {
321 cpu_to_be32(0x4),
322 cpu_to_be32(0x0), cpu_to_be32(0x0),
323 cpu_to_be32(0x0), cpu_to_be32(nodeid)
324 };
325 char mem_name[32];
326 uint64_t mem_reg_property[2];
327 int off;
328
329 mem_reg_property[0] = cpu_to_be64(start);
330 mem_reg_property[1] = cpu_to_be64(size);
331
332 sprintf(mem_name, "memory@%" HWADDR_PRIx, start);
333 off = fdt_add_subnode(fdt, 0, mem_name);
334 _FDT(off);
335 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
336 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
337 sizeof(mem_reg_property))));
338 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
339 sizeof(associativity))));
340 return off;
341}
342
343static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
344{
345 MemoryDeviceInfoList *info;
346
347 for (info = list; info; info = info->next) {
348 MemoryDeviceInfo *value = info->value;
349
350 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
351 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
352
353 if (addr >= pcdimm_info->addr &&
354 addr < (pcdimm_info->addr + pcdimm_info->size)) {
355 return pcdimm_info->node;
356 }
357 }
358 }
359
360 return -1;
361}
362
363struct sPAPRDrconfCellV2 {
364 uint32_t seq_lmbs;
365 uint64_t base_addr;
366 uint32_t drc_index;
367 uint32_t aa_index;
368 uint32_t flags;
369} QEMU_PACKED;
370
371typedef struct DrconfCellQueue {
372 struct sPAPRDrconfCellV2 cell;
373 QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
374} DrconfCellQueue;
375
376static DrconfCellQueue *
377spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
378 uint32_t drc_index, uint32_t aa_index,
379 uint32_t flags)
380{
381 DrconfCellQueue *elem;
382
383 elem = g_malloc0(sizeof(*elem));
384 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
385 elem->cell.base_addr = cpu_to_be64(base_addr);
386 elem->cell.drc_index = cpu_to_be32(drc_index);
387 elem->cell.aa_index = cpu_to_be32(aa_index);
388 elem->cell.flags = cpu_to_be32(flags);
389
390 return elem;
391}
392
393static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt,
394 int offset, MemoryDeviceInfoList *dimms)
395{
396 MachineState *machine = MACHINE(spapr);
397 uint8_t *int_buf, *cur_index;
398 int ret;
399 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
400 uint64_t addr, cur_addr, size;
401 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
402 uint64_t mem_end = machine->device_memory->base +
403 memory_region_size(&machine->device_memory->mr);
404 uint32_t node, buf_len, nr_entries = 0;
405 SpaprDrc *drc;
406 DrconfCellQueue *elem, *next;
407 MemoryDeviceInfoList *info;
408 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
409 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
410
411
412 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
413 SPAPR_LMB_FLAGS_RESERVED |
414 SPAPR_LMB_FLAGS_DRC_INVALID);
415 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
416 nr_entries++;
417
418 cur_addr = machine->device_memory->base;
419 for (info = dimms; info; info = info->next) {
420 PCDIMMDeviceInfo *di = info->value->u.dimm.data;
421
422 addr = di->addr;
423 size = di->size;
424 node = di->node;
425
426
427
428
429
430
431 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM)
432 continue;
433
434
435 if (cur_addr < addr) {
436 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
437 g_assert(drc);
438 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
439 cur_addr, spapr_drc_index(drc), -1, 0);
440 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
441 nr_entries++;
442 }
443
444
445 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
446 g_assert(drc);
447 elem = spapr_get_drconf_cell(size / lmb_size, addr,
448 spapr_drc_index(drc), node,
449 SPAPR_LMB_FLAGS_ASSIGNED);
450 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
451 nr_entries++;
452 cur_addr = addr + size;
453 }
454
455
456 if (cur_addr < mem_end) {
457 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
458 g_assert(drc);
459 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
460 cur_addr, spapr_drc_index(drc), -1, 0);
461 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
462 nr_entries++;
463 }
464
465 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
466 int_buf = cur_index = g_malloc0(buf_len);
467 *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
468 cur_index += sizeof(nr_entries);
469
470 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
471 memcpy(cur_index, &elem->cell, sizeof(elem->cell));
472 cur_index += sizeof(elem->cell);
473 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
474 g_free(elem);
475 }
476
477 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
478 g_free(int_buf);
479 if (ret < 0) {
480 return -1;
481 }
482 return 0;
483}
484
485static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt,
486 int offset, MemoryDeviceInfoList *dimms)
487{
488 MachineState *machine = MACHINE(spapr);
489 int i, ret;
490 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
491 uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
492 uint32_t nr_lmbs = (machine->device_memory->base +
493 memory_region_size(&machine->device_memory->mr)) /
494 lmb_size;
495 uint32_t *int_buf, *cur_index, buf_len;
496
497
498
499
500 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
501 cur_index = int_buf = g_malloc0(buf_len);
502 int_buf[0] = cpu_to_be32(nr_lmbs);
503 cur_index++;
504 for (i = 0; i < nr_lmbs; i++) {
505 uint64_t addr = i * lmb_size;
506 uint32_t *dynamic_memory = cur_index;
507
508 if (i >= device_lmb_start) {
509 SpaprDrc *drc;
510
511 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
512 g_assert(drc);
513
514 dynamic_memory[0] = cpu_to_be32(addr >> 32);
515 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
516 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
517 dynamic_memory[3] = cpu_to_be32(0);
518 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
519 if (memory_region_present(get_system_memory(), addr)) {
520 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
521 } else {
522 dynamic_memory[5] = cpu_to_be32(0);
523 }
524 } else {
525
526
527
528
529
530 dynamic_memory[0] = cpu_to_be32(addr >> 32);
531 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
532 dynamic_memory[2] = cpu_to_be32(0);
533 dynamic_memory[3] = cpu_to_be32(0);
534 dynamic_memory[4] = cpu_to_be32(-1);
535 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
536 SPAPR_LMB_FLAGS_DRC_INVALID);
537 }
538
539 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
540 }
541 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
542 g_free(int_buf);
543 if (ret < 0) {
544 return -1;
545 }
546 return 0;
547}
548
549
550
551
552
553
554static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr,
555 void *fdt)
556{
557 MachineState *machine = MACHINE(spapr);
558 int nb_numa_nodes = machine->numa_state->num_nodes;
559 int ret, i, offset;
560 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
561 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
562 uint32_t *int_buf, *cur_index, buf_len;
563 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
564 MemoryDeviceInfoList *dimms = NULL;
565
566
567
568
569 if (machine->ram_size == machine->maxram_size) {
570 return 0;
571 }
572
573 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
574
575 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
576 sizeof(prop_lmb_size));
577 if (ret < 0) {
578 return ret;
579 }
580
581 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
582 if (ret < 0) {
583 return ret;
584 }
585
586 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
587 if (ret < 0) {
588 return ret;
589 }
590
591
592 dimms = qmp_memory_device_list();
593 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
594 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms);
595 } else {
596 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms);
597 }
598 qapi_free_MemoryDeviceInfoList(dimms);
599
600 if (ret < 0) {
601 return ret;
602 }
603
604
605 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t);
606 cur_index = int_buf = g_malloc0(buf_len);
607 int_buf[0] = cpu_to_be32(nr_nodes);
608 int_buf[1] = cpu_to_be32(4);
609 cur_index += 2;
610 for (i = 0; i < nr_nodes; i++) {
611 uint32_t associativity[] = {
612 cpu_to_be32(0x0),
613 cpu_to_be32(0x0),
614 cpu_to_be32(0x0),
615 cpu_to_be32(i)
616 };
617 memcpy(cur_index, associativity, sizeof(associativity));
618 cur_index += 4;
619 }
620 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
621 (cur_index - int_buf) * sizeof(uint32_t));
622 g_free(int_buf);
623
624 return ret;
625}
626
627static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt)
628{
629 MachineState *machine = MACHINE(spapr);
630 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
631 hwaddr mem_start, node_size;
632 int i, nb_nodes = machine->numa_state->num_nodes;
633 NodeInfo *nodes = machine->numa_state->nodes;
634
635 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
636 if (!nodes[i].node_mem) {
637 continue;
638 }
639 if (mem_start >= machine->ram_size) {
640 node_size = 0;
641 } else {
642 node_size = nodes[i].node_mem;
643 if (node_size > machine->ram_size - mem_start) {
644 node_size = machine->ram_size - mem_start;
645 }
646 }
647 if (!mem_start) {
648
649
650 spapr_dt_memory_node(fdt, i, 0, spapr->rma_size);
651 mem_start += spapr->rma_size;
652 node_size -= spapr->rma_size;
653 }
654 for ( ; node_size; ) {
655 hwaddr sizetmp = pow2floor(node_size);
656
657
658 if (ctzl(mem_start) < ctzl(sizetmp)) {
659 sizetmp = 1ULL << ctzl(mem_start);
660 }
661
662 spapr_dt_memory_node(fdt, i, mem_start, sizetmp);
663 node_size -= sizetmp;
664 mem_start += sizetmp;
665 }
666 }
667
668
669 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) {
670 int ret;
671
672 g_assert(smc->dr_lmb_enabled);
673 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt);
674 if (ret) {
675 return ret;
676 }
677 }
678
679 return 0;
680}
681
682static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset,
683 SpaprMachineState *spapr)
684{
685 MachineState *ms = MACHINE(spapr);
686 PowerPCCPU *cpu = POWERPC_CPU(cs);
687 CPUPPCState *env = &cpu->env;
688 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
689 int index = spapr_get_vcpu_id(cpu);
690 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
691 0xffffffff, 0xffffffff};
692 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
693 : SPAPR_TIMEBASE_FREQ;
694 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
695 uint32_t page_sizes_prop[64];
696 size_t page_sizes_prop_size;
697 unsigned int smp_threads = ms->smp.threads;
698 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores;
699 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
700 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
701 SpaprDrc *drc;
702 int drc_index;
703 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
704 int i;
705
706 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
707 if (drc) {
708 drc_index = spapr_drc_index(drc);
709 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
710 }
711
712 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
713 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
714
715 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
716 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
717 env->dcache_line_size)));
718 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
719 env->dcache_line_size)));
720 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
721 env->icache_line_size)));
722 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
723 env->icache_line_size)));
724
725 if (pcc->l1_dcache_size) {
726 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
727 pcc->l1_dcache_size)));
728 } else {
729 warn_report("Unknown L1 dcache size for cpu");
730 }
731 if (pcc->l1_icache_size) {
732 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
733 pcc->l1_icache_size)));
734 } else {
735 warn_report("Unknown L1 icache size for cpu");
736 }
737
738 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
739 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
740 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
741 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
742 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
743 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
744
745 if (env->spr_cb[SPR_PURR].oea_read) {
746 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1)));
747 }
748 if (env->spr_cb[SPR_SPURR].oea_read) {
749 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1)));
750 }
751
752 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
753 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
754 segs, sizeof(segs))));
755 }
756
757
758
759
760
761
762
763 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
764 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
765 } else {
766 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
767 }
768
769
770
771
772 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
773 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
774 }
775
776 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
777 sizeof(page_sizes_prop));
778 if (page_sizes_prop_size) {
779 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
780 page_sizes_prop, page_sizes_prop_size)));
781 }
782
783 spapr_dt_pa_features(spapr, cpu, fdt, offset);
784
785 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
786 cs->cpu_index / vcpus_per_socket)));
787
788 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
789 pft_size_prop, sizeof(pft_size_prop))));
790
791 if (ms->numa_state->num_nodes > 1) {
792 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
793 }
794
795 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
796
797 if (pcc->radix_page_info) {
798 for (i = 0; i < pcc->radix_page_info->count; i++) {
799 radix_AP_encodings[i] =
800 cpu_to_be32(pcc->radix_page_info->entries[i]);
801 }
802 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
803 radix_AP_encodings,
804 pcc->radix_page_info->count *
805 sizeof(radix_AP_encodings[0]))));
806 }
807
808
809
810
811
812 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF)
813 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits",
814 pcc->lrg_decr_bits)));
815}
816
817static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr)
818{
819 CPUState **rev;
820 CPUState *cs;
821 int n_cpus;
822 int cpus_offset;
823 char *nodename;
824 int i;
825
826 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
827 _FDT(cpus_offset);
828 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
829 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
830
831
832
833
834
835
836
837
838
839 n_cpus = 0;
840 rev = NULL;
841 CPU_FOREACH(cs) {
842 rev = g_renew(CPUState *, rev, n_cpus + 1);
843 rev[n_cpus++] = cs;
844 }
845
846 for (i = n_cpus - 1; i >= 0; i--) {
847 CPUState *cs = rev[i];
848 PowerPCCPU *cpu = POWERPC_CPU(cs);
849 int index = spapr_get_vcpu_id(cpu);
850 DeviceClass *dc = DEVICE_GET_CLASS(cs);
851 int offset;
852
853 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
854 continue;
855 }
856
857 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
858 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
859 g_free(nodename);
860 _FDT(offset);
861 spapr_dt_cpu(cs, fdt, offset, spapr);
862 }
863
864 g_free(rev);
865}
866
867static int spapr_dt_rng(void *fdt)
868{
869 int node;
870 int ret;
871
872 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities");
873 if (node <= 0) {
874 return -1;
875 }
876 ret = fdt_setprop_string(fdt, node, "device_type",
877 "ibm,platform-facilities");
878 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1);
879 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0);
880
881 node = fdt_add_subnode(fdt, node, "ibm,random-v1");
882 if (node <= 0) {
883 return -1;
884 }
885 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random");
886
887 return ret ? -1 : 0;
888}
889
890static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
891{
892 MachineState *ms = MACHINE(spapr);
893 int rtas;
894 GString *hypertas = g_string_sized_new(256);
895 GString *qemu_hypertas = g_string_sized_new(256);
896 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
897 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
898 memory_region_size(&MACHINE(spapr)->device_memory->mr);
899 uint32_t lrdr_capacity[] = {
900 cpu_to_be32(max_device_addr >> 32),
901 cpu_to_be32(max_device_addr & 0xffffffff),
902 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
903 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads),
904 };
905 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0);
906 uint32_t maxdomains[] = {
907 cpu_to_be32(4),
908 maxdomain,
909 maxdomain,
910 maxdomain,
911 cpu_to_be32(spapr->gpu_numa_id),
912 };
913
914 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
915
916
917 add_str(hypertas, "hcall-pft");
918 add_str(hypertas, "hcall-term");
919 add_str(hypertas, "hcall-dabr");
920 add_str(hypertas, "hcall-interrupt");
921 add_str(hypertas, "hcall-tce");
922 add_str(hypertas, "hcall-vio");
923 add_str(hypertas, "hcall-splpar");
924 add_str(hypertas, "hcall-join");
925 add_str(hypertas, "hcall-bulk");
926 add_str(hypertas, "hcall-set-mode");
927 add_str(hypertas, "hcall-sprg0");
928 add_str(hypertas, "hcall-copy");
929 add_str(hypertas, "hcall-debug");
930 add_str(hypertas, "hcall-vphn");
931 add_str(qemu_hypertas, "hcall-memop1");
932
933 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
934 add_str(hypertas, "hcall-multi-tce");
935 }
936
937 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
938 add_str(hypertas, "hcall-hpt-resize");
939 }
940
941 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
942 hypertas->str, hypertas->len));
943 g_string_free(hypertas, TRUE);
944 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
945 qemu_hypertas->str, qemu_hypertas->len));
946 g_string_free(qemu_hypertas, TRUE);
947
948 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
949 refpoints, sizeof(refpoints)));
950
951 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
952 maxdomains, sizeof(maxdomains)));
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX +
976 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t)));
977 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
978 RTAS_ERROR_LOG_MAX));
979 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
980 RTAS_EVENT_SCAN_RATE));
981
982 g_assert(msi_nonbroken);
983 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
984
985
986
987
988
989
990
991
992 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
993
994 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
995 lrdr_capacity, sizeof(lrdr_capacity)));
996
997 spapr_dt_rtas_tokens(fdt, rtas);
998}
999
1000
1001
1002
1003
1004
1005static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt,
1006 int chosen)
1007{
1008 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
1009
1010 char val[2 * 4] = {
1011 23, 0x00,
1012 24, 0x00,
1013 25, 0x00,
1014 26, 0x40,
1015 };
1016
1017 if (spapr->irq->xics && spapr->irq->xive) {
1018 val[1] = SPAPR_OV5_XIVE_BOTH;
1019 } else if (spapr->irq->xive) {
1020 val[1] = SPAPR_OV5_XIVE_EXPLOIT;
1021 } else {
1022 assert(spapr->irq->xics);
1023 val[1] = SPAPR_OV5_XIVE_LEGACY;
1024 }
1025
1026 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1027 first_ppc_cpu->compat_pvr)) {
1028
1029
1030
1031
1032 val[1] = SPAPR_OV5_XIVE_LEGACY;
1033 val[3] = 0x00;
1034 } else if (kvm_enabled()) {
1035 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1036 val[3] = 0x80;
1037 } else if (kvmppc_has_cap_mmu_radix()) {
1038 val[3] = 0x40;
1039 } else {
1040 val[3] = 0x00;
1041 }
1042 } else {
1043
1044 val[3] = 0xC0;
1045 }
1046 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
1047 val, sizeof(val)));
1048}
1049
1050static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset)
1051{
1052 MachineState *machine = MACHINE(spapr);
1053 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1054 int chosen;
1055
1056 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1057
1058 if (reset) {
1059 const char *boot_device = machine->boot_order;
1060 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1061 size_t cb = 0;
1062 char *bootlist = get_boot_devices_list(&cb);
1063
1064 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) {
1065 _FDT(fdt_setprop_string(fdt, chosen, "bootargs",
1066 machine->kernel_cmdline));
1067 }
1068
1069 if (spapr->initrd_size) {
1070 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1071 spapr->initrd_base));
1072 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1073 spapr->initrd_base + spapr->initrd_size));
1074 }
1075
1076 if (spapr->kernel_size) {
1077 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr),
1078 cpu_to_be64(spapr->kernel_size) };
1079
1080 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1081 &kprop, sizeof(kprop)));
1082 if (spapr->kernel_le) {
1083 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1084 }
1085 }
1086 if (boot_menu) {
1087 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1088 }
1089 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1090 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1091 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1092
1093 if (cb && bootlist) {
1094 int i;
1095
1096 for (i = 0; i < cb; i++) {
1097 if (bootlist[i] == '\n') {
1098 bootlist[i] = ' ';
1099 }
1100 }
1101 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1102 }
1103
1104 if (boot_device && strlen(boot_device)) {
1105 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1106 }
1107
1108 if (!spapr->has_graphics && stdout_path) {
1109
1110
1111
1112
1113
1114
1115
1116 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1117 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
1118 }
1119
1120
1121
1122
1123
1124 if (smc->linux_pci_probe) {
1125 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0));
1126 }
1127
1128 spapr_dt_ov5_platform_support(spapr, fdt, chosen);
1129
1130 g_free(stdout_path);
1131 g_free(bootlist);
1132 }
1133
1134 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5"));
1135}
1136
1137static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt)
1138{
1139
1140
1141 int hypervisor;
1142 uint8_t hypercall[16];
1143
1144 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1145
1146 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1147 if (kvmppc_has_cap_fixup_hcalls()) {
1148
1149
1150
1151
1152 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1153 sizeof(hypercall))) {
1154 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1155 hypercall, sizeof(hypercall)));
1156 }
1157 }
1158}
1159
1160void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space)
1161{
1162 MachineState *machine = MACHINE(spapr);
1163 MachineClass *mc = MACHINE_GET_CLASS(machine);
1164 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1165 int ret;
1166 void *fdt;
1167 SpaprPhbState *phb;
1168 char *buf;
1169
1170 fdt = g_malloc0(space);
1171 _FDT((fdt_create_empty_tree(fdt, space)));
1172
1173
1174 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1175 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1176 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1177
1178
1179 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1180 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1181 if (qemu_uuid_set) {
1182 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1183 }
1184 g_free(buf);
1185
1186 if (qemu_get_vm_name()) {
1187 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1188 qemu_get_vm_name()));
1189 }
1190
1191
1192 if (spapr->host_model) {
1193 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model));
1194 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) {
1195 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1196 g_free(buf);
1197 }
1198
1199 if (spapr->host_serial) {
1200 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial));
1201 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) {
1202 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1203 g_free(buf);
1204 }
1205
1206 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1207 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1208
1209
1210 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC);
1211
1212 ret = spapr_dt_memory(spapr, fdt);
1213 if (ret < 0) {
1214 error_report("couldn't setup memory nodes in fdt");
1215 exit(1);
1216 }
1217
1218
1219 spapr_dt_vdevice(spapr->vio_bus, fdt);
1220
1221 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1222 ret = spapr_dt_rng(fdt);
1223 if (ret < 0) {
1224 error_report("could not set up rng device in the fdt");
1225 exit(1);
1226 }
1227 }
1228
1229 QLIST_FOREACH(phb, &spapr->phbs, list) {
1230 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL);
1231 if (ret < 0) {
1232 error_report("couldn't setup PCI devices in fdt");
1233 exit(1);
1234 }
1235 }
1236
1237 spapr_dt_cpus(fdt, spapr);
1238
1239 if (smc->dr_lmb_enabled) {
1240 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1241 }
1242
1243 if (mc->has_hotpluggable_cpus) {
1244 int offset = fdt_path_offset(fdt, "/cpus");
1245 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU);
1246 if (ret < 0) {
1247 error_report("Couldn't set up CPU DR device tree properties");
1248 exit(1);
1249 }
1250 }
1251
1252
1253 spapr_dt_events(spapr, fdt);
1254
1255
1256 spapr_dt_rtas(spapr, fdt);
1257
1258
1259 spapr_dt_chosen(spapr, fdt, reset);
1260
1261
1262 if (kvm_enabled()) {
1263 spapr_dt_hypervisor(spapr, fdt);
1264 }
1265
1266
1267 if (reset) {
1268 if (spapr->kernel_size) {
1269 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr,
1270 spapr->kernel_size)));
1271 }
1272 if (spapr->initrd_size) {
1273 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base,
1274 spapr->initrd_size)));
1275 }
1276 }
1277
1278 if (smc->dr_phb_enabled) {
1279 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB);
1280 if (ret < 0) {
1281 error_report("Couldn't set up PHB DR device tree properties");
1282 exit(1);
1283 }
1284 }
1285
1286
1287 if (mc->nvdimm_supported) {
1288 spapr_dt_persistent_memory(fdt);
1289 }
1290
1291 return fdt;
1292}
1293
1294static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1295{
1296 SpaprMachineState *spapr = opaque;
1297
1298 return (addr & 0x0fffffff) + spapr->kernel_addr;
1299}
1300
1301static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1302 PowerPCCPU *cpu)
1303{
1304 CPUPPCState *env = &cpu->env;
1305
1306
1307 g_assert(qemu_mutex_iothread_locked());
1308
1309 if (msr_pr) {
1310 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1311 env->gpr[3] = H_PRIVILEGE;
1312 } else {
1313 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1314 }
1315}
1316
1317struct LPCRSyncState {
1318 target_ulong value;
1319 target_ulong mask;
1320};
1321
1322static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg)
1323{
1324 struct LPCRSyncState *s = arg.host_ptr;
1325 PowerPCCPU *cpu = POWERPC_CPU(cs);
1326 CPUPPCState *env = &cpu->env;
1327 target_ulong lpcr;
1328
1329 cpu_synchronize_state(cs);
1330 lpcr = env->spr[SPR_LPCR];
1331 lpcr &= ~s->mask;
1332 lpcr |= s->value;
1333 ppc_store_lpcr(cpu, lpcr);
1334}
1335
1336void spapr_set_all_lpcrs(target_ulong value, target_ulong mask)
1337{
1338 CPUState *cs;
1339 struct LPCRSyncState s = {
1340 .value = value,
1341 .mask = mask
1342 };
1343 CPU_FOREACH(cs) {
1344 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s));
1345 }
1346}
1347
1348static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry)
1349{
1350 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1351
1352
1353 entry->dw0 = spapr->patb_entry & PATE0_HR;
1354 entry->dw1 = spapr->patb_entry;
1355}
1356
1357#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1358#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1359#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1360#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1361#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1362
1363
1364
1365
1366static int get_htab_fd(SpaprMachineState *spapr)
1367{
1368 Error *local_err = NULL;
1369
1370 if (spapr->htab_fd >= 0) {
1371 return spapr->htab_fd;
1372 }
1373
1374 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1375 if (spapr->htab_fd < 0) {
1376 error_report_err(local_err);
1377 }
1378
1379 return spapr->htab_fd;
1380}
1381
1382void close_htab_fd(SpaprMachineState *spapr)
1383{
1384 if (spapr->htab_fd >= 0) {
1385 close(spapr->htab_fd);
1386 }
1387 spapr->htab_fd = -1;
1388}
1389
1390static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1391{
1392 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1393
1394 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1395}
1396
1397static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1398{
1399 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1400
1401 assert(kvm_enabled());
1402
1403 if (!spapr->htab) {
1404 return 0;
1405 }
1406
1407 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1408}
1409
1410static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1411 hwaddr ptex, int n)
1412{
1413 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1414 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1415
1416 if (!spapr->htab) {
1417
1418
1419
1420 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1421 kvmppc_read_hptes(hptes, ptex, n);
1422 return hptes;
1423 }
1424
1425
1426
1427
1428
1429 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1430}
1431
1432static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1433 const ppc_hash_pte64_t *hptes,
1434 hwaddr ptex, int n)
1435{
1436 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1437
1438 if (!spapr->htab) {
1439 g_free((void *)hptes);
1440 }
1441
1442
1443}
1444
1445void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
1446 uint64_t pte0, uint64_t pte1)
1447{
1448 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp);
1449 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1450
1451 if (!spapr->htab) {
1452 kvmppc_write_hpte(ptex, pte0, pte1);
1453 } else {
1454 if (pte0 & HPTE64_V_VALID) {
1455 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1456
1457
1458
1459
1460
1461 smp_wmb();
1462 stq_p(spapr->htab + offset, pte0);
1463 } else {
1464 stq_p(spapr->htab + offset, pte0);
1465
1466
1467
1468
1469
1470 smp_wmb();
1471 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1472 }
1473 }
1474}
1475
1476static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1477 uint64_t pte1)
1478{
1479 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15;
1480 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1481
1482 if (!spapr->htab) {
1483
1484 error_report("spapr_hpte_set_c called with no hash table !");
1485 return;
1486 }
1487
1488
1489 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80);
1490}
1491
1492static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1493 uint64_t pte1)
1494{
1495 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14;
1496 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1497
1498 if (!spapr->htab) {
1499
1500 error_report("spapr_hpte_set_r called with no hash table !");
1501 return;
1502 }
1503
1504
1505 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01);
1506}
1507
1508int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1509{
1510 int shift;
1511
1512
1513
1514
1515 shift = ctz64(pow2ceil(ramsize)) - 7;
1516 shift = MAX(shift, 18);
1517 shift = MIN(shift, 46);
1518 return shift;
1519}
1520
1521void spapr_free_hpt(SpaprMachineState *spapr)
1522{
1523 g_free(spapr->htab);
1524 spapr->htab = NULL;
1525 spapr->htab_shift = 0;
1526 close_htab_fd(spapr);
1527}
1528
1529void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
1530 Error **errp)
1531{
1532 long rc;
1533
1534
1535 spapr_free_hpt(spapr);
1536
1537 rc = kvmppc_reset_htab(shift);
1538 if (rc < 0) {
1539
1540 error_setg_errno(errp, errno,
1541 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1542 shift);
1543
1544
1545 } else if (rc > 0) {
1546
1547 if (rc != shift) {
1548 error_setg(errp,
1549 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1550 shift, rc);
1551 }
1552
1553 spapr->htab_shift = shift;
1554 spapr->htab = NULL;
1555 } else {
1556
1557 size_t size = 1ULL << shift;
1558 int i;
1559
1560 spapr->htab = qemu_memalign(size, size);
1561 if (!spapr->htab) {
1562 error_setg_errno(errp, errno,
1563 "Could not allocate HPT of order %d", shift);
1564 return;
1565 }
1566
1567 memset(spapr->htab, 0, size);
1568 spapr->htab_shift = shift;
1569
1570 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1571 DIRTY_HPTE(HPTE(spapr->htab, i));
1572 }
1573 }
1574
1575 spapr->patb_entry = 0;
1576 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT);
1577}
1578
1579void spapr_setup_hpt(SpaprMachineState *spapr)
1580{
1581 int hpt_shift;
1582
1583 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1584 || (spapr->cas_reboot
1585 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1586 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1587 } else {
1588 uint64_t current_ram_size;
1589
1590 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1591 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1592 }
1593 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1594
1595 if (kvm_enabled()) {
1596 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift);
1597
1598
1599 if (vrma_limit < spapr->rma_size) {
1600 error_report("Unable to create %" HWADDR_PRIu
1601 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB",
1602 spapr->rma_size / MiB, vrma_limit / MiB);
1603 exit(EXIT_FAILURE);
1604 }
1605 }
1606}
1607
1608static int spapr_reset_drcs(Object *child, void *opaque)
1609{
1610 SpaprDrc *drc =
1611 (SpaprDrc *) object_dynamic_cast(child,
1612 TYPE_SPAPR_DR_CONNECTOR);
1613
1614 if (drc) {
1615 spapr_drc_reset(drc);
1616 }
1617
1618 return 0;
1619}
1620
1621static void spapr_machine_reset(MachineState *machine)
1622{
1623 SpaprMachineState *spapr = SPAPR_MACHINE(machine);
1624 PowerPCCPU *first_ppc_cpu;
1625 hwaddr fdt_addr;
1626 void *fdt;
1627 int rc;
1628
1629 kvmppc_svm_off(&error_fatal);
1630 spapr_caps_apply(spapr);
1631
1632 first_ppc_cpu = POWERPC_CPU(first_cpu);
1633 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1634 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
1635 spapr->max_compat_pvr)) {
1636
1637
1638
1639
1640
1641 spapr->patb_entry = PATE1_GR;
1642 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT);
1643 } else {
1644 spapr_setup_hpt(spapr);
1645 }
1646
1647 qemu_devices_reset();
1648
1649
1650
1651
1652
1653 if (!spapr->cas_reboot) {
1654 spapr_ovec_cleanup(spapr->ov5_cas);
1655 spapr->ov5_cas = spapr_ovec_new();
1656
1657 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
1658 }
1659
1660
1661
1662
1663
1664 spapr_irq_reset(spapr, &error_fatal);
1665
1666
1667
1668
1669
1670
1671 if (qtest_enabled()) {
1672 spapr_ovec_cleanup(spapr->ov5_cas);
1673 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
1674 }
1675
1676
1677
1678
1679
1680
1681 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1682
1683 spapr_clear_pending_events(spapr);
1684
1685
1686
1687
1688
1689
1690 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE;
1691
1692 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE);
1693
1694 rc = fdt_pack(fdt);
1695
1696
1697 assert(rc == 0);
1698
1699
1700 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1701 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1702 g_free(spapr->fdt_blob);
1703 spapr->fdt_size = fdt_totalsize(fdt);
1704 spapr->fdt_initial_size = spapr->fdt_size;
1705 spapr->fdt_blob = fdt;
1706
1707
1708 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0);
1709 first_ppc_cpu->env.gpr[5] = 0;
1710
1711 spapr->cas_reboot = false;
1712
1713 spapr->fwnmi_system_reset_addr = -1;
1714 spapr->fwnmi_machine_check_addr = -1;
1715 spapr->fwnmi_machine_check_interlock = -1;
1716
1717
1718 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond);
1719
1720 migrate_del_blocker(spapr->fwnmi_migration_blocker);
1721}
1722
1723static void spapr_create_nvram(SpaprMachineState *spapr)
1724{
1725 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1726 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1727
1728 if (dinfo) {
1729 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1730 &error_fatal);
1731 }
1732
1733 qdev_init_nofail(dev);
1734
1735 spapr->nvram = (struct SpaprNvram *)dev;
1736}
1737
1738static void spapr_rtc_create(SpaprMachineState *spapr)
1739{
1740 object_initialize_child(OBJECT(spapr), "rtc",
1741 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC,
1742 &error_fatal, NULL);
1743 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1744 &error_fatal);
1745 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1746 "date", &error_fatal);
1747}
1748
1749
1750static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1751{
1752 switch (vga_interface_type) {
1753 case VGA_NONE:
1754 return false;
1755 case VGA_DEVICE:
1756 return true;
1757 case VGA_STD:
1758 case VGA_VIRTIO:
1759 case VGA_CIRRUS:
1760 return pci_vga_init(pci_bus) != NULL;
1761 default:
1762 error_setg(errp,
1763 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1764 return false;
1765 }
1766}
1767
1768static int spapr_pre_load(void *opaque)
1769{
1770 int rc;
1771
1772 rc = spapr_caps_pre_load(opaque);
1773 if (rc) {
1774 return rc;
1775 }
1776
1777 return 0;
1778}
1779
1780static int spapr_post_load(void *opaque, int version_id)
1781{
1782 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1783 int err = 0;
1784
1785 err = spapr_caps_post_migration(spapr);
1786 if (err) {
1787 return err;
1788 }
1789
1790
1791
1792
1793
1794
1795
1796 if (version_id < 3) {
1797 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1798 if (err) {
1799 return err;
1800 }
1801 }
1802
1803 if (kvm_enabled() && spapr->patb_entry) {
1804 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1805 bool radix = !!(spapr->patb_entry & PATE1_GR);
1806 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1807
1808
1809
1810
1811
1812 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0,
1813 LPCR_HR | LPCR_UPRT);
1814
1815 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1816 if (err) {
1817 error_report("Process table config unsupported by the host");
1818 return -EINVAL;
1819 }
1820 }
1821
1822 err = spapr_irq_post_load(spapr, version_id);
1823 if (err) {
1824 return err;
1825 }
1826
1827 return err;
1828}
1829
1830static int spapr_pre_save(void *opaque)
1831{
1832 int rc;
1833
1834 rc = spapr_caps_pre_save(opaque);
1835 if (rc) {
1836 return rc;
1837 }
1838
1839 return 0;
1840}
1841
1842static bool version_before_3(void *opaque, int version_id)
1843{
1844 return version_id < 3;
1845}
1846
1847static bool spapr_pending_events_needed(void *opaque)
1848{
1849 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1850 return !QTAILQ_EMPTY(&spapr->pending_events);
1851}
1852
1853static const VMStateDescription vmstate_spapr_event_entry = {
1854 .name = "spapr_event_log_entry",
1855 .version_id = 1,
1856 .minimum_version_id = 1,
1857 .fields = (VMStateField[]) {
1858 VMSTATE_UINT32(summary, SpaprEventLogEntry),
1859 VMSTATE_UINT32(extended_length, SpaprEventLogEntry),
1860 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0,
1861 NULL, extended_length),
1862 VMSTATE_END_OF_LIST()
1863 },
1864};
1865
1866static const VMStateDescription vmstate_spapr_pending_events = {
1867 .name = "spapr_pending_events",
1868 .version_id = 1,
1869 .minimum_version_id = 1,
1870 .needed = spapr_pending_events_needed,
1871 .fields = (VMStateField[]) {
1872 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1,
1873 vmstate_spapr_event_entry, SpaprEventLogEntry, next),
1874 VMSTATE_END_OF_LIST()
1875 },
1876};
1877
1878static bool spapr_ov5_cas_needed(void *opaque)
1879{
1880 SpaprMachineState *spapr = opaque;
1881 SpaprOptionVector *ov5_mask = spapr_ovec_new();
1882 bool cas_needed;
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1910 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1911 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2);
1912
1913
1914
1915 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask);
1916
1917 spapr_ovec_cleanup(ov5_mask);
1918
1919 return cas_needed;
1920}
1921
1922static const VMStateDescription vmstate_spapr_ov5_cas = {
1923 .name = "spapr_option_vector_ov5_cas",
1924 .version_id = 1,
1925 .minimum_version_id = 1,
1926 .needed = spapr_ov5_cas_needed,
1927 .fields = (VMStateField[]) {
1928 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1,
1929 vmstate_spapr_ovec, SpaprOptionVector),
1930 VMSTATE_END_OF_LIST()
1931 },
1932};
1933
1934static bool spapr_patb_entry_needed(void *opaque)
1935{
1936 SpaprMachineState *spapr = opaque;
1937
1938 return !!spapr->patb_entry;
1939}
1940
1941static const VMStateDescription vmstate_spapr_patb_entry = {
1942 .name = "spapr_patb_entry",
1943 .version_id = 1,
1944 .minimum_version_id = 1,
1945 .needed = spapr_patb_entry_needed,
1946 .fields = (VMStateField[]) {
1947 VMSTATE_UINT64(patb_entry, SpaprMachineState),
1948 VMSTATE_END_OF_LIST()
1949 },
1950};
1951
1952static bool spapr_irq_map_needed(void *opaque)
1953{
1954 SpaprMachineState *spapr = opaque;
1955
1956 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr);
1957}
1958
1959static const VMStateDescription vmstate_spapr_irq_map = {
1960 .name = "spapr_irq_map",
1961 .version_id = 1,
1962 .minimum_version_id = 1,
1963 .needed = spapr_irq_map_needed,
1964 .fields = (VMStateField[]) {
1965 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr),
1966 VMSTATE_END_OF_LIST()
1967 },
1968};
1969
1970static bool spapr_dtb_needed(void *opaque)
1971{
1972 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque);
1973
1974 return smc->update_dt_enabled;
1975}
1976
1977static int spapr_dtb_pre_load(void *opaque)
1978{
1979 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1980
1981 g_free(spapr->fdt_blob);
1982 spapr->fdt_blob = NULL;
1983 spapr->fdt_size = 0;
1984
1985 return 0;
1986}
1987
1988static const VMStateDescription vmstate_spapr_dtb = {
1989 .name = "spapr_dtb",
1990 .version_id = 1,
1991 .minimum_version_id = 1,
1992 .needed = spapr_dtb_needed,
1993 .pre_load = spapr_dtb_pre_load,
1994 .fields = (VMStateField[]) {
1995 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState),
1996 VMSTATE_UINT32(fdt_size, SpaprMachineState),
1997 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL,
1998 fdt_size),
1999 VMSTATE_END_OF_LIST()
2000 },
2001};
2002
2003static bool spapr_fwnmi_needed(void *opaque)
2004{
2005 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
2006
2007 return spapr->fwnmi_machine_check_addr != -1;
2008}
2009
2010static int spapr_fwnmi_pre_save(void *opaque)
2011{
2012 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
2013
2014
2015
2016
2017
2018 if (spapr->fwnmi_machine_check_interlock != -1) {
2019 warn_report("A machine check is being handled during migration. The"
2020 "handler may run and log hardware error on the destination");
2021 }
2022
2023 return 0;
2024}
2025
2026static const VMStateDescription vmstate_spapr_fwnmi = {
2027 .name = "spapr_fwnmi",
2028 .version_id = 1,
2029 .minimum_version_id = 1,
2030 .needed = spapr_fwnmi_needed,
2031 .pre_save = spapr_fwnmi_pre_save,
2032 .fields = (VMStateField[]) {
2033 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState),
2034 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState),
2035 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState),
2036 VMSTATE_END_OF_LIST()
2037 },
2038};
2039
2040static const VMStateDescription vmstate_spapr = {
2041 .name = "spapr",
2042 .version_id = 3,
2043 .minimum_version_id = 1,
2044 .pre_load = spapr_pre_load,
2045 .post_load = spapr_post_load,
2046 .pre_save = spapr_pre_save,
2047 .fields = (VMStateField[]) {
2048
2049 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
2050
2051
2052 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3),
2053
2054 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2),
2055 VMSTATE_END_OF_LIST()
2056 },
2057 .subsections = (const VMStateDescription*[]) {
2058 &vmstate_spapr_ov5_cas,
2059 &vmstate_spapr_patb_entry,
2060 &vmstate_spapr_pending_events,
2061 &vmstate_spapr_cap_htm,
2062 &vmstate_spapr_cap_vsx,
2063 &vmstate_spapr_cap_dfp,
2064 &vmstate_spapr_cap_cfpc,
2065 &vmstate_spapr_cap_sbbc,
2066 &vmstate_spapr_cap_ibs,
2067 &vmstate_spapr_cap_hpt_maxpagesize,
2068 &vmstate_spapr_irq_map,
2069 &vmstate_spapr_cap_nested_kvm_hv,
2070 &vmstate_spapr_dtb,
2071 &vmstate_spapr_cap_large_decr,
2072 &vmstate_spapr_cap_ccf_assist,
2073 &vmstate_spapr_cap_fwnmi,
2074 &vmstate_spapr_fwnmi,
2075 NULL
2076 }
2077};
2078
2079static int htab_save_setup(QEMUFile *f, void *opaque)
2080{
2081 SpaprMachineState *spapr = opaque;
2082
2083
2084 if (!spapr->htab_shift) {
2085 qemu_put_be32(f, -1);
2086 } else {
2087 qemu_put_be32(f, spapr->htab_shift);
2088 }
2089
2090 if (spapr->htab) {
2091 spapr->htab_save_index = 0;
2092 spapr->htab_first_pass = true;
2093 } else {
2094 if (spapr->htab_shift) {
2095 assert(kvm_enabled());
2096 }
2097 }
2098
2099
2100 return 0;
2101}
2102
2103static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr,
2104 int chunkstart, int n_valid, int n_invalid)
2105{
2106 qemu_put_be32(f, chunkstart);
2107 qemu_put_be16(f, n_valid);
2108 qemu_put_be16(f, n_invalid);
2109 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
2110 HASH_PTE_SIZE_64 * n_valid);
2111}
2112
2113static void htab_save_end_marker(QEMUFile *f)
2114{
2115 qemu_put_be32(f, 0);
2116 qemu_put_be16(f, 0);
2117 qemu_put_be16(f, 0);
2118}
2119
2120static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr,
2121 int64_t max_ns)
2122{
2123 bool has_timeout = max_ns != -1;
2124 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2125 int index = spapr->htab_save_index;
2126 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2127
2128 assert(spapr->htab_first_pass);
2129
2130 do {
2131 int chunkstart;
2132
2133
2134 while ((index < htabslots)
2135 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2136 CLEAN_HPTE(HPTE(spapr->htab, index));
2137 index++;
2138 }
2139
2140
2141 chunkstart = index;
2142 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2143 && HPTE_VALID(HPTE(spapr->htab, index))) {
2144 CLEAN_HPTE(HPTE(spapr->htab, index));
2145 index++;
2146 }
2147
2148 if (index > chunkstart) {
2149 int n_valid = index - chunkstart;
2150
2151 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
2152
2153 if (has_timeout &&
2154 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2155 break;
2156 }
2157 }
2158 } while ((index < htabslots) && !qemu_file_rate_limit(f));
2159
2160 if (index >= htabslots) {
2161 assert(index == htabslots);
2162 index = 0;
2163 spapr->htab_first_pass = false;
2164 }
2165 spapr->htab_save_index = index;
2166}
2167
2168static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr,
2169 int64_t max_ns)
2170{
2171 bool final = max_ns < 0;
2172 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2173 int examined = 0, sent = 0;
2174 int index = spapr->htab_save_index;
2175 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2176
2177 assert(!spapr->htab_first_pass);
2178
2179 do {
2180 int chunkstart, invalidstart;
2181
2182
2183 while ((index < htabslots)
2184 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
2185 index++;
2186 examined++;
2187 }
2188
2189 chunkstart = index;
2190
2191 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2192 && HPTE_DIRTY(HPTE(spapr->htab, index))
2193 && HPTE_VALID(HPTE(spapr->htab, index))) {
2194 CLEAN_HPTE(HPTE(spapr->htab, index));
2195 index++;
2196 examined++;
2197 }
2198
2199 invalidstart = index;
2200
2201 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
2202 && HPTE_DIRTY(HPTE(spapr->htab, index))
2203 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2204 CLEAN_HPTE(HPTE(spapr->htab, index));
2205 index++;
2206 examined++;
2207 }
2208
2209 if (index > chunkstart) {
2210 int n_valid = invalidstart - chunkstart;
2211 int n_invalid = index - invalidstart;
2212
2213 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
2214 sent += index - chunkstart;
2215
2216 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2217 break;
2218 }
2219 }
2220
2221 if (examined >= htabslots) {
2222 break;
2223 }
2224
2225 if (index >= htabslots) {
2226 assert(index == htabslots);
2227 index = 0;
2228 }
2229 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
2230
2231 if (index >= htabslots) {
2232 assert(index == htabslots);
2233 index = 0;
2234 }
2235
2236 spapr->htab_save_index = index;
2237
2238 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
2239}
2240
2241#define MAX_ITERATION_NS 5000000
2242#define MAX_KVM_BUF_SIZE 2048
2243
2244static int htab_save_iterate(QEMUFile *f, void *opaque)
2245{
2246 SpaprMachineState *spapr = opaque;
2247 int fd;
2248 int rc = 0;
2249
2250
2251 if (!spapr->htab_shift) {
2252 qemu_put_be32(f, -1);
2253 return 1;
2254 } else {
2255 qemu_put_be32(f, 0);
2256 }
2257
2258 if (!spapr->htab) {
2259 assert(kvm_enabled());
2260
2261 fd = get_htab_fd(spapr);
2262 if (fd < 0) {
2263 return fd;
2264 }
2265
2266 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
2267 if (rc < 0) {
2268 return rc;
2269 }
2270 } else if (spapr->htab_first_pass) {
2271 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2272 } else {
2273 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
2274 }
2275
2276 htab_save_end_marker(f);
2277
2278 return rc;
2279}
2280
2281static int htab_save_complete(QEMUFile *f, void *opaque)
2282{
2283 SpaprMachineState *spapr = opaque;
2284 int fd;
2285
2286
2287 if (!spapr->htab_shift) {
2288 qemu_put_be32(f, -1);
2289 return 0;
2290 } else {
2291 qemu_put_be32(f, 0);
2292 }
2293
2294 if (!spapr->htab) {
2295 int rc;
2296
2297 assert(kvm_enabled());
2298
2299 fd = get_htab_fd(spapr);
2300 if (fd < 0) {
2301 return fd;
2302 }
2303
2304 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2305 if (rc < 0) {
2306 return rc;
2307 }
2308 } else {
2309 if (spapr->htab_first_pass) {
2310 htab_save_first_pass(f, spapr, -1);
2311 }
2312 htab_save_later_pass(f, spapr, -1);
2313 }
2314
2315
2316 htab_save_end_marker(f);
2317
2318 return 0;
2319}
2320
2321static int htab_load(QEMUFile *f, void *opaque, int version_id)
2322{
2323 SpaprMachineState *spapr = opaque;
2324 uint32_t section_hdr;
2325 int fd = -1;
2326 Error *local_err = NULL;
2327
2328 if (version_id < 1 || version_id > 1) {
2329 error_report("htab_load() bad version");
2330 return -EINVAL;
2331 }
2332
2333 section_hdr = qemu_get_be32(f);
2334
2335 if (section_hdr == -1) {
2336 spapr_free_hpt(spapr);
2337 return 0;
2338 }
2339
2340 if (section_hdr) {
2341
2342 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2343 if (local_err) {
2344 error_report_err(local_err);
2345 return -EINVAL;
2346 }
2347 return 0;
2348 }
2349
2350 if (!spapr->htab) {
2351 assert(kvm_enabled());
2352
2353 fd = kvmppc_get_htab_fd(true, 0, &local_err);
2354 if (fd < 0) {
2355 error_report_err(local_err);
2356 return fd;
2357 }
2358 }
2359
2360 while (true) {
2361 uint32_t index;
2362 uint16_t n_valid, n_invalid;
2363
2364 index = qemu_get_be32(f);
2365 n_valid = qemu_get_be16(f);
2366 n_invalid = qemu_get_be16(f);
2367
2368 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2369
2370 break;
2371 }
2372
2373 if ((index + n_valid + n_invalid) >
2374 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2375
2376 error_report(
2377 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2378 index, n_valid, n_invalid, spapr->htab_shift);
2379 return -EINVAL;
2380 }
2381
2382 if (spapr->htab) {
2383 if (n_valid) {
2384 qemu_get_buffer(f, HPTE(spapr->htab, index),
2385 HASH_PTE_SIZE_64 * n_valid);
2386 }
2387 if (n_invalid) {
2388 memset(HPTE(spapr->htab, index + n_valid), 0,
2389 HASH_PTE_SIZE_64 * n_invalid);
2390 }
2391 } else {
2392 int rc;
2393
2394 assert(fd >= 0);
2395
2396 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2397 if (rc < 0) {
2398 return rc;
2399 }
2400 }
2401 }
2402
2403 if (!spapr->htab) {
2404 assert(fd >= 0);
2405 close(fd);
2406 }
2407
2408 return 0;
2409}
2410
2411static void htab_save_cleanup(void *opaque)
2412{
2413 SpaprMachineState *spapr = opaque;
2414
2415 close_htab_fd(spapr);
2416}
2417
2418static SaveVMHandlers savevm_htab_handlers = {
2419 .save_setup = htab_save_setup,
2420 .save_live_iterate = htab_save_iterate,
2421 .save_live_complete_precopy = htab_save_complete,
2422 .save_cleanup = htab_save_cleanup,
2423 .load_state = htab_load,
2424};
2425
2426static void spapr_boot_set(void *opaque, const char *boot_device,
2427 Error **errp)
2428{
2429 MachineState *machine = MACHINE(opaque);
2430 machine->boot_order = g_strdup(boot_device);
2431}
2432
2433static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr)
2434{
2435 MachineState *machine = MACHINE(spapr);
2436 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2437 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2438 int i;
2439
2440 for (i = 0; i < nr_lmbs; i++) {
2441 uint64_t addr;
2442
2443 addr = i * lmb_size + machine->device_memory->base;
2444 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2445 addr / lmb_size);
2446 }
2447}
2448
2449
2450
2451
2452
2453
2454static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2455{
2456 int i;
2457
2458 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2459 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2460 " is not aligned to %" PRIu64 " MiB",
2461 machine->ram_size,
2462 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2463 return;
2464 }
2465
2466 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2467 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2468 " is not aligned to %" PRIu64 " MiB",
2469 machine->ram_size,
2470 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2471 return;
2472 }
2473
2474 for (i = 0; i < machine->numa_state->num_nodes; i++) {
2475 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2476 error_setg(errp,
2477 "Node %d memory size 0x%" PRIx64
2478 " is not aligned to %" PRIu64 " MiB",
2479 i, machine->numa_state->nodes[i].node_mem,
2480 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2481 return;
2482 }
2483 }
2484}
2485
2486
2487static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2488{
2489 int index = id / ms->smp.threads;
2490
2491 if (index >= ms->possible_cpus->len) {
2492 return NULL;
2493 }
2494 if (idx) {
2495 *idx = index;
2496 }
2497 return &ms->possible_cpus->cpus[index];
2498}
2499
2500static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp)
2501{
2502 MachineState *ms = MACHINE(spapr);
2503 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
2504 Error *local_err = NULL;
2505 bool vsmt_user = !!spapr->vsmt;
2506 int kvm_smt = kvmppc_smt_threads();
2507 int ret;
2508 unsigned int smp_threads = ms->smp.threads;
2509
2510 if (!kvm_enabled() && (smp_threads > 1)) {
2511 error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2512 "on a pseries machine");
2513 goto out;
2514 }
2515 if (!is_power_of_2(smp_threads)) {
2516 error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2517 "machine because it must be a power of 2", smp_threads);
2518 goto out;
2519 }
2520
2521
2522 if (vsmt_user) {
2523 if (spapr->vsmt < smp_threads) {
2524 error_setg(&local_err, "Cannot support VSMT mode %d"
2525 " because it must be >= threads/core (%d)",
2526 spapr->vsmt, smp_threads);
2527 goto out;
2528 }
2529
2530 } else if (!smc->smp_threads_vsmt) {
2531
2532
2533
2534
2535
2536
2537
2538 spapr->vsmt = MAX(8, smp_threads);
2539 } else {
2540 spapr->vsmt = smp_threads;
2541 }
2542
2543
2544 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2545 ret = kvmppc_set_smt_threads(spapr->vsmt);
2546 if (ret) {
2547
2548 error_setg(&local_err,
2549 "Failed to set KVM's VSMT mode to %d (errno %d)",
2550 spapr->vsmt, ret);
2551
2552
2553
2554
2555 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2556 warn_report_err(local_err);
2557 local_err = NULL;
2558 goto out;
2559 } else {
2560 if (!vsmt_user) {
2561 error_append_hint(&local_err,
2562 "On PPC, a VM with %d threads/core"
2563 " on a host with %d threads/core"
2564 " requires the use of VSMT mode %d.\n",
2565 smp_threads, kvm_smt, spapr->vsmt);
2566 }
2567 kvmppc_error_append_smt_possible_hint(&local_err);
2568 goto out;
2569 }
2570 }
2571 }
2572
2573out:
2574 error_propagate(errp, local_err);
2575}
2576
2577static void spapr_init_cpus(SpaprMachineState *spapr)
2578{
2579 MachineState *machine = MACHINE(spapr);
2580 MachineClass *mc = MACHINE_GET_CLASS(machine);
2581 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2582 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2583 const CPUArchIdList *possible_cpus;
2584 unsigned int smp_cpus = machine->smp.cpus;
2585 unsigned int smp_threads = machine->smp.threads;
2586 unsigned int max_cpus = machine->smp.max_cpus;
2587 int boot_cores_nr = smp_cpus / smp_threads;
2588 int i;
2589
2590 possible_cpus = mc->possible_cpu_arch_ids(machine);
2591 if (mc->has_hotpluggable_cpus) {
2592 if (smp_cpus % smp_threads) {
2593 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2594 smp_cpus, smp_threads);
2595 exit(1);
2596 }
2597 if (max_cpus % smp_threads) {
2598 error_report("max_cpus (%u) must be multiple of threads (%u)",
2599 max_cpus, smp_threads);
2600 exit(1);
2601 }
2602 } else {
2603 if (max_cpus != smp_cpus) {
2604 error_report("This machine version does not support CPU hotplug");
2605 exit(1);
2606 }
2607 boot_cores_nr = possible_cpus->len;
2608 }
2609
2610 if (smc->pre_2_10_has_unused_icps) {
2611 int i;
2612
2613 for (i = 0; i < spapr_max_server_number(spapr); i++) {
2614
2615
2616
2617 pre_2_10_vmstate_register_dummy_icp(i);
2618 }
2619 }
2620
2621 for (i = 0; i < possible_cpus->len; i++) {
2622 int core_id = i * smp_threads;
2623
2624 if (mc->has_hotpluggable_cpus) {
2625 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2626 spapr_vcpu_id(spapr, core_id));
2627 }
2628
2629 if (i < boot_cores_nr) {
2630 Object *core = object_new(type);
2631 int nr_threads = smp_threads;
2632
2633
2634 if ((i + 1) * smp_threads >= smp_cpus) {
2635 nr_threads = smp_cpus - i * smp_threads;
2636 }
2637
2638 object_property_set_int(core, nr_threads, "nr-threads",
2639 &error_fatal);
2640 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2641 &error_fatal);
2642 object_property_set_bool(core, true, "realized", &error_fatal);
2643
2644 object_unref(core);
2645 }
2646 }
2647}
2648
2649static PCIHostState *spapr_create_default_phb(void)
2650{
2651 DeviceState *dev;
2652
2653 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
2654 qdev_prop_set_uint32(dev, "index", 0);
2655 qdev_init_nofail(dev);
2656
2657 return PCI_HOST_BRIDGE(dev);
2658}
2659
2660static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp)
2661{
2662 MachineState *machine = MACHINE(spapr);
2663 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
2664 hwaddr rma_size = machine->ram_size;
2665 hwaddr node0_size = spapr_node0_size(machine);
2666
2667
2668 rma_size = MIN(rma_size, node0_size);
2669
2670
2671
2672
2673
2674 rma_size = MIN(rma_size, 1 * TiB);
2675
2676
2677
2678
2679
2680
2681 if (smc->rma_limit) {
2682 rma_size = MIN(rma_size, smc->rma_limit);
2683 }
2684
2685 if (rma_size < MIN_RMA_SLOF) {
2686 error_setg(errp,
2687 "pSeries SLOF firmware requires >= %" HWADDR_PRIx
2688 "ldMiB guest RMA (Real Mode Area memory)",
2689 MIN_RMA_SLOF / MiB);
2690 return 0;
2691 }
2692
2693 return rma_size;
2694}
2695
2696
2697static void spapr_machine_init(MachineState *machine)
2698{
2699 SpaprMachineState *spapr = SPAPR_MACHINE(machine);
2700 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2701 MachineClass *mc = MACHINE_GET_CLASS(machine);
2702 const char *kernel_filename = machine->kernel_filename;
2703 const char *initrd_filename = machine->initrd_filename;
2704 PCIHostState *phb;
2705 int i;
2706 MemoryRegion *sysmem = get_system_memory();
2707 long load_limit, fw_size;
2708 char *filename;
2709 Error *resize_hpt_err = NULL;
2710
2711 msi_nonbroken = true;
2712
2713 QLIST_INIT(&spapr->phbs);
2714 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2715
2716
2717 spapr_caps_init(spapr);
2718
2719 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2720 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2721
2722
2723
2724
2725
2726
2727 if (resize_hpt_err) {
2728 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2729 error_free(resize_hpt_err);
2730 resize_hpt_err = NULL;
2731 } else {
2732 spapr->resize_hpt = smc->resize_hpt_default;
2733 }
2734 }
2735
2736 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2737
2738 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2739
2740
2741
2742 error_report_err(resize_hpt_err);
2743 exit(1);
2744 }
2745
2746 spapr->rma_size = spapr_rma_size(spapr, &error_fatal);
2747
2748
2749 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2750
2751
2752
2753
2754
2755 spapr_set_vsmt_mode(spapr, &error_fatal);
2756
2757
2758 spapr_irq_init(spapr, &error_fatal);
2759
2760
2761
2762 spapr->ov5 = spapr_ovec_new();
2763 spapr->ov5_cas = spapr_ovec_new();
2764
2765 if (smc->dr_lmb_enabled) {
2766 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2767 spapr_validate_node_memory(machine, &error_fatal);
2768 }
2769
2770 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2771
2772
2773 if (spapr->use_hotplug_event_source) {
2774 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2775 }
2776
2777
2778 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2779 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2780 }
2781
2782
2783 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
2784
2785
2786 if (spapr->irq->xive) {
2787 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT);
2788 }
2789
2790
2791 spapr_init_cpus(spapr);
2792
2793
2794
2795
2796
2797
2798
2799
2800 if (machine->numa_state->num_nodes) {
2801 for (i = 0; i < machine->numa_state->num_nodes; ++i) {
2802
2803 if (machine->numa_state->nodes[i].node_mem == 0) {
2804 CPUState *cs;
2805 int found = 0;
2806
2807 CPU_FOREACH(cs) {
2808 PowerPCCPU *cpu = POWERPC_CPU(cs);
2809 if (cpu->node_id == i) {
2810 found = 1;
2811 break;
2812 }
2813 }
2814
2815 if (!found) {
2816 error_report(
2817 "Memory-less/cpu-less nodes are not supported (node %d)",
2818 i);
2819 exit(1);
2820 }
2821 }
2822 }
2823
2824 }
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes);
2836
2837 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2838 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
2839 spapr->max_compat_pvr)) {
2840
2841 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2842 }
2843
2844
2845 if (kvm_enabled()) {
2846
2847 kvmppc_enable_logical_ci_hcalls();
2848 kvmppc_enable_set_mode_hcall();
2849
2850
2851 kvmppc_enable_clear_ref_mod_hcalls();
2852
2853
2854 kvmppc_enable_h_page_init();
2855 }
2856
2857
2858 memory_region_add_subregion(sysmem, 0, machine->ram);
2859
2860
2861 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
2862
2863
2864 if (machine->ram_size < machine->maxram_size) {
2865 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
2866
2867
2868
2869
2870
2871 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2872 SPAPR_MAX_RAM_SLOTS;
2873
2874 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2875 max_memslots = SPAPR_MAX_RAM_SLOTS;
2876 }
2877 if (machine->ram_slots > max_memslots) {
2878 error_report("Specified number of memory slots %"
2879 PRIu64" exceeds max supported %d",
2880 machine->ram_slots, max_memslots);
2881 exit(1);
2882 }
2883
2884 machine->device_memory->base = ROUND_UP(machine->ram_size,
2885 SPAPR_DEVICE_MEM_ALIGN);
2886 memory_region_init(&machine->device_memory->mr, OBJECT(spapr),
2887 "device-memory", device_mem_size);
2888 memory_region_add_subregion(sysmem, machine->device_memory->base,
2889 &machine->device_memory->mr);
2890 }
2891
2892 if (smc->dr_lmb_enabled) {
2893 spapr_create_lmb_dr_connectors(spapr);
2894 }
2895
2896 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) {
2897
2898 error_setg(&spapr->fwnmi_migration_blocker,
2899 "A machine check is being handled during migration. The handler"
2900 "may run and log hardware error on the destination");
2901 }
2902
2903 if (mc->nvdimm_supported) {
2904 spapr_create_nvdimm_dr_connectors(spapr);
2905 }
2906
2907
2908 spapr_events_init(spapr);
2909
2910
2911 spapr_rtc_create(spapr);
2912
2913
2914 spapr->vio_bus = spapr_vio_bus_init();
2915
2916 for (i = 0; i < serial_max_hds(); i++) {
2917 if (serial_hd(i)) {
2918 spapr_vty_create(spapr->vio_bus, serial_hd(i));
2919 }
2920 }
2921
2922
2923 spapr_create_nvram(spapr);
2924
2925
2926
2927
2928
2929
2930
2931
2932 if (smc->dr_phb_enabled) {
2933 for (i = 0; i < SPAPR_MAX_PHBS; i++) {
2934 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i);
2935 }
2936 }
2937
2938
2939 spapr_pci_rtas_init();
2940
2941 phb = spapr_create_default_phb();
2942
2943 for (i = 0; i < nb_nics; i++) {
2944 NICInfo *nd = &nd_table[i];
2945
2946 if (!nd->model) {
2947 nd->model = g_strdup("spapr-vlan");
2948 }
2949
2950 if (g_str_equal(nd->model, "spapr-vlan") ||
2951 g_str_equal(nd->model, "ibmveth")) {
2952 spapr_vlan_create(spapr->vio_bus, nd);
2953 } else {
2954 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2955 }
2956 }
2957
2958 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2959 spapr_vscsi_create(spapr->vio_bus);
2960 }
2961
2962
2963 if (spapr_vga_init(phb->bus, &error_fatal)) {
2964 spapr->has_graphics = true;
2965 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2966 }
2967
2968 if (machine->usb) {
2969 if (smc->use_ohci_by_default) {
2970 pci_create_simple(phb->bus, -1, "pci-ohci");
2971 } else {
2972 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2973 }
2974
2975 if (spapr->has_graphics) {
2976 USBBus *usb_bus = usb_bus_find(-1);
2977
2978 usb_create_simple(usb_bus, "usb-kbd");
2979 usb_create_simple(usb_bus, "usb-mouse");
2980 }
2981 }
2982
2983 if (kernel_filename) {
2984 uint64_t lowaddr = 0;
2985
2986 spapr->kernel_size = load_elf(kernel_filename, NULL,
2987 translate_kernel_address, spapr,
2988 NULL, &lowaddr, NULL, NULL, 1,
2989 PPC_ELF_MACHINE, 0, 0);
2990 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2991 spapr->kernel_size = load_elf(kernel_filename, NULL,
2992 translate_kernel_address, spapr, NULL,
2993 &lowaddr, NULL, NULL, 0,
2994 PPC_ELF_MACHINE,
2995 0, 0);
2996 spapr->kernel_le = spapr->kernel_size > 0;
2997 }
2998 if (spapr->kernel_size < 0) {
2999 error_report("error loading %s: %s", kernel_filename,
3000 load_elf_strerror(spapr->kernel_size));
3001 exit(1);
3002 }
3003
3004
3005 if (initrd_filename) {
3006
3007
3008
3009 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size
3010 + 0x1ffff) & ~0xffff;
3011 spapr->initrd_size = load_image_targphys(initrd_filename,
3012 spapr->initrd_base,
3013 load_limit
3014 - spapr->initrd_base);
3015 if (spapr->initrd_size < 0) {
3016 error_report("could not load initial ram disk '%s'",
3017 initrd_filename);
3018 exit(1);
3019 }
3020 }
3021 }
3022
3023 if (bios_name == NULL) {
3024 bios_name = FW_FILE_NAME;
3025 }
3026 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
3027 if (!filename) {
3028 error_report("Could not find LPAR firmware '%s'", bios_name);
3029 exit(1);
3030 }
3031 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
3032 if (fw_size <= 0) {
3033 error_report("Could not load LPAR firmware '%s'", filename);
3034 exit(1);
3035 }
3036 g_free(filename);
3037
3038
3039
3040
3041 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
3042 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1,
3043 &savevm_htab_handlers, spapr);
3044
3045 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine),
3046 &error_fatal);
3047
3048 qemu_register_boot_set(spapr_boot_set, spapr);
3049
3050
3051
3052
3053
3054
3055 qemu_register_wakeup_support();
3056
3057 if (kvm_enabled()) {
3058
3059 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
3060 &spapr->tb);
3061
3062 kvmppc_spapr_enable_inkernel_multitce();
3063 }
3064
3065 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond);
3066}
3067
3068static int spapr_kvm_type(MachineState *machine, const char *vm_type)
3069{
3070 if (!vm_type) {
3071 return 0;
3072 }
3073
3074 if (!strcmp(vm_type, "HV")) {
3075 return 1;
3076 }
3077
3078 if (!strcmp(vm_type, "PR")) {
3079 return 2;
3080 }
3081
3082 error_report("Unknown kvm-type specified '%s'", vm_type);
3083 exit(1);
3084}
3085
3086
3087
3088
3089
3090static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
3091 DeviceState *dev)
3092{
3093#define CAST(type, obj, name) \
3094 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3095 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
3096 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
3097 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
3098
3099 if (d) {
3100 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
3101 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
3102 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
3103
3104 if (spapr) {
3105
3106
3107
3108
3109
3110
3111 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun;
3112 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3113 (uint64_t)id << 48);
3114 } else if (virtio) {
3115
3116
3117
3118
3119
3120
3121
3122 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
3123 if (d->lun >= 256) {
3124
3125 id |= 0x4000;
3126 }
3127 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3128 (uint64_t)id << 32);
3129 } else if (usb) {
3130
3131
3132
3133
3134 unsigned usb_port = atoi(usb->port->path);
3135 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
3136 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3137 (uint64_t)id << 32);
3138 }
3139 }
3140
3141
3142
3143
3144
3145
3146
3147 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
3148 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
3149 if (usb_host_dev_is_scsi_storage(usbdev)) {
3150 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
3151 }
3152 }
3153
3154 if (phb) {
3155
3156 return g_strdup_printf("pci@%"PRIX64, phb->buid);
3157 }
3158
3159 if (vsc) {
3160
3161 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
3162 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
3163 }
3164
3165 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
3166
3167 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
3168 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
3169 }
3170
3171 return NULL;
3172}
3173
3174static char *spapr_get_kvm_type(Object *obj, Error **errp)
3175{
3176 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3177
3178 return g_strdup(spapr->kvm_type);
3179}
3180
3181static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
3182{
3183 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3184
3185 g_free(spapr->kvm_type);
3186 spapr->kvm_type = g_strdup(value);
3187}
3188
3189static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
3190{
3191 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3192
3193 return spapr->use_hotplug_event_source;
3194}
3195
3196static void spapr_set_modern_hotplug_events(Object *obj, bool value,
3197 Error **errp)
3198{
3199 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3200
3201 spapr->use_hotplug_event_source = value;
3202}
3203
3204static bool spapr_get_msix_emulation(Object *obj, Error **errp)
3205{
3206 return true;
3207}
3208
3209static char *spapr_get_resize_hpt(Object *obj, Error **errp)
3210{
3211 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3212
3213 switch (spapr->resize_hpt) {
3214 case SPAPR_RESIZE_HPT_DEFAULT:
3215 return g_strdup("default");
3216 case SPAPR_RESIZE_HPT_DISABLED:
3217 return g_strdup("disabled");
3218 case SPAPR_RESIZE_HPT_ENABLED:
3219 return g_strdup("enabled");
3220 case SPAPR_RESIZE_HPT_REQUIRED:
3221 return g_strdup("required");
3222 }
3223 g_assert_not_reached();
3224}
3225
3226static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
3227{
3228 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3229
3230 if (strcmp(value, "default") == 0) {
3231 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
3232 } else if (strcmp(value, "disabled") == 0) {
3233 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
3234 } else if (strcmp(value, "enabled") == 0) {
3235 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
3236 } else if (strcmp(value, "required") == 0) {
3237 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
3238 } else {
3239 error_setg(errp, "Bad value for \"resize-hpt\" property");
3240 }
3241}
3242
3243static char *spapr_get_ic_mode(Object *obj, Error **errp)
3244{
3245 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3246
3247 if (spapr->irq == &spapr_irq_xics_legacy) {
3248 return g_strdup("legacy");
3249 } else if (spapr->irq == &spapr_irq_xics) {
3250 return g_strdup("xics");
3251 } else if (spapr->irq == &spapr_irq_xive) {
3252 return g_strdup("xive");
3253 } else if (spapr->irq == &spapr_irq_dual) {
3254 return g_strdup("dual");
3255 }
3256 g_assert_not_reached();
3257}
3258
3259static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp)
3260{
3261 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3262
3263 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
3264 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3265 return;
3266 }
3267
3268
3269 if (strcmp(value, "xics") == 0) {
3270 spapr->irq = &spapr_irq_xics;
3271 } else if (strcmp(value, "xive") == 0) {
3272 spapr->irq = &spapr_irq_xive;
3273 } else if (strcmp(value, "dual") == 0) {
3274 spapr->irq = &spapr_irq_dual;
3275 } else {
3276 error_setg(errp, "Bad value for \"ic-mode\" property");
3277 }
3278}
3279
3280static char *spapr_get_host_model(Object *obj, Error **errp)
3281{
3282 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3283
3284 return g_strdup(spapr->host_model);
3285}
3286
3287static void spapr_set_host_model(Object *obj, const char *value, Error **errp)
3288{
3289 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3290
3291 g_free(spapr->host_model);
3292 spapr->host_model = g_strdup(value);
3293}
3294
3295static char *spapr_get_host_serial(Object *obj, Error **errp)
3296{
3297 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3298
3299 return g_strdup(spapr->host_serial);
3300}
3301
3302static void spapr_set_host_serial(Object *obj, const char *value, Error **errp)
3303{
3304 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3305
3306 g_free(spapr->host_serial);
3307 spapr->host_serial = g_strdup(value);
3308}
3309
3310static void spapr_instance_init(Object *obj)
3311{
3312 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3313 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3314
3315 spapr->htab_fd = -1;
3316 spapr->use_hotplug_event_source = true;
3317 object_property_add_str(obj, "kvm-type",
3318 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
3319 object_property_set_description(obj, "kvm-type",
3320 "Specifies the KVM virtualization mode (HV, PR)",
3321 NULL);
3322 object_property_add_bool(obj, "modern-hotplug-events",
3323 spapr_get_modern_hotplug_events,
3324 spapr_set_modern_hotplug_events,
3325 NULL);
3326 object_property_set_description(obj, "modern-hotplug-events",
3327 "Use dedicated hotplug event mechanism in"
3328 " place of standard EPOW events when possible"
3329 " (required for memory hot-unplug support)",
3330 NULL);
3331 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
3332 "Maximum permitted CPU compatibility mode",
3333 &error_fatal);
3334
3335 object_property_add_str(obj, "resize-hpt",
3336 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
3337 object_property_set_description(obj, "resize-hpt",
3338 "Resizing of the Hash Page Table (enabled, disabled, required)",
3339 NULL);
3340 object_property_add_uint32_ptr(obj, "vsmt",
3341 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE,
3342 &error_abort);
3343 object_property_set_description(obj, "vsmt",
3344 "Virtual SMT: KVM behaves as if this were"
3345 " the host's SMT mode", &error_abort);
3346
3347 object_property_add_bool(obj, "vfio-no-msix-emulation",
3348 spapr_get_msix_emulation, NULL, NULL);
3349
3350 object_property_add_uint64_ptr(obj, "kernel-addr",
3351 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE,
3352 &error_abort);
3353 object_property_set_description(obj, "kernel-addr",
3354 stringify(KERNEL_LOAD_ADDR)
3355 " for -kernel is the default",
3356 NULL);
3357 spapr->kernel_addr = KERNEL_LOAD_ADDR;
3358
3359 spapr->irq = smc->irq;
3360 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode,
3361 spapr_set_ic_mode, NULL);
3362 object_property_set_description(obj, "ic-mode",
3363 "Specifies the interrupt controller mode (xics, xive, dual)",
3364 NULL);
3365
3366 object_property_add_str(obj, "host-model",
3367 spapr_get_host_model, spapr_set_host_model,
3368 &error_abort);
3369 object_property_set_description(obj, "host-model",
3370 "Host model to advertise in guest device tree", &error_abort);
3371 object_property_add_str(obj, "host-serial",
3372 spapr_get_host_serial, spapr_set_host_serial,
3373 &error_abort);
3374 object_property_set_description(obj, "host-serial",
3375 "Host serial number to advertise in guest device tree", &error_abort);
3376}
3377
3378static void spapr_machine_finalizefn(Object *obj)
3379{
3380 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3381
3382 g_free(spapr->kvm_type);
3383}
3384
3385void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
3386{
3387 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
3388
3389 cpu_synchronize_state(cs);
3390
3391 if (spapr->fwnmi_system_reset_addr != -1) {
3392 uint64_t rtas_addr, addr;
3393 PowerPCCPU *cpu = POWERPC_CPU(cs);
3394 CPUPPCState *env = &cpu->env;
3395
3396
3397 rtas_addr = spapr_get_rtas_addr();
3398 if (!rtas_addr) {
3399 qemu_system_guest_panicked(NULL);
3400 return;
3401 }
3402
3403 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2;
3404 stq_be_phys(&address_space_memory, addr, env->gpr[3]);
3405 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0);
3406 env->gpr[3] = addr;
3407 }
3408 ppc_cpu_do_system_reset(cs, spapr->fwnmi_system_reset_addr);
3409}
3410
3411static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
3412{
3413 CPUState *cs;
3414
3415 CPU_FOREACH(cs) {
3416 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
3417 }
3418}
3419
3420int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3421 void *fdt, int *fdt_start_offset, Error **errp)
3422{
3423 uint64_t addr;
3424 uint32_t node;
3425
3426 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE;
3427 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP,
3428 &error_abort);
3429 *fdt_start_offset = spapr_dt_memory_node(fdt, node, addr,
3430 SPAPR_MEMORY_BLOCK_SIZE);
3431 return 0;
3432}
3433
3434static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
3435 bool dedicated_hp_event_source, Error **errp)
3436{
3437 SpaprDrc *drc;
3438 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
3439 int i;
3440 uint64_t addr = addr_start;
3441 bool hotplugged = spapr_drc_hotplugged(dev);
3442 Error *local_err = NULL;
3443
3444 for (i = 0; i < nr_lmbs; i++) {
3445 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3446 addr / SPAPR_MEMORY_BLOCK_SIZE);
3447 g_assert(drc);
3448
3449 spapr_drc_attach(drc, dev, &local_err);
3450 if (local_err) {
3451 while (addr > addr_start) {
3452 addr -= SPAPR_MEMORY_BLOCK_SIZE;
3453 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3454 addr / SPAPR_MEMORY_BLOCK_SIZE);
3455 spapr_drc_detach(drc);
3456 }
3457 error_propagate(errp, local_err);
3458 return;
3459 }
3460 if (!hotplugged) {
3461 spapr_drc_reset(drc);
3462 }
3463 addr += SPAPR_MEMORY_BLOCK_SIZE;
3464 }
3465
3466
3467
3468 if (hotplugged) {
3469 if (dedicated_hp_event_source) {
3470 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3471 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3472 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3473 nr_lmbs,
3474 spapr_drc_index(drc));
3475 } else {
3476 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
3477 nr_lmbs);
3478 }
3479 }
3480}
3481
3482static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3483 Error **errp)
3484{
3485 Error *local_err = NULL;
3486 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev);
3487 PCDIMMDevice *dimm = PC_DIMM(dev);
3488 uint64_t size, addr, slot;
3489 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
3490
3491 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort);
3492
3493 pc_dimm_plug(dimm, MACHINE(ms), &local_err);
3494 if (local_err) {
3495 goto out;
3496 }
3497
3498 if (!is_nvdimm) {
3499 addr = object_property_get_uint(OBJECT(dimm),
3500 PC_DIMM_ADDR_PROP, &local_err);
3501 if (local_err) {
3502 goto out_unplug;
3503 }
3504 spapr_add_lmbs(dev, addr, size,
3505 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
3506 &local_err);
3507 } else {
3508 slot = object_property_get_uint(OBJECT(dimm),
3509 PC_DIMM_SLOT_PROP, &local_err);
3510 if (local_err) {
3511 goto out_unplug;
3512 }
3513 spapr_add_nvdimm(dev, slot, &local_err);
3514 }
3515
3516 if (local_err) {
3517 goto out_unplug;
3518 }
3519
3520 return;
3521
3522out_unplug:
3523 pc_dimm_unplug(dimm, MACHINE(ms));
3524out:
3525 error_propagate(errp, local_err);
3526}
3527
3528static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3529 Error **errp)
3530{
3531 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev);
3532 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3533 const MachineClass *mc = MACHINE_CLASS(smc);
3534 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
3535 PCDIMMDevice *dimm = PC_DIMM(dev);
3536 Error *local_err = NULL;
3537 uint64_t size;
3538 Object *memdev;
3539 hwaddr pagesize;
3540
3541 if (!smc->dr_lmb_enabled) {
3542 error_setg(errp, "Memory hotplug not supported for this machine");
3543 return;
3544 }
3545
3546 if (is_nvdimm && !mc->nvdimm_supported) {
3547 error_setg(errp, "NVDIMM hotplug not supported for this machine");
3548 return;
3549 }
3550
3551 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err);
3552 if (local_err) {
3553 error_propagate(errp, local_err);
3554 return;
3555 }
3556
3557 if (!is_nvdimm && size % SPAPR_MEMORY_BLOCK_SIZE) {
3558 error_setg(errp, "Hotplugged memory size must be a multiple of "
3559 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB);
3560 return;
3561 } else if (is_nvdimm) {
3562 spapr_nvdimm_validate_opts(NVDIMM(dev), size, &local_err);
3563 if (local_err) {
3564 error_propagate(errp, local_err);
3565 return;
3566 }
3567 }
3568
3569 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP,
3570 &error_abort);
3571 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev));
3572 spapr_check_pagesize(spapr, pagesize, &local_err);
3573 if (local_err) {
3574 error_propagate(errp, local_err);
3575 return;
3576 }
3577
3578 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp);
3579}
3580
3581struct SpaprDimmState {
3582 PCDIMMDevice *dimm;
3583 uint32_t nr_lmbs;
3584 QTAILQ_ENTRY(SpaprDimmState) next;
3585};
3586
3587static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s,
3588 PCDIMMDevice *dimm)
3589{
3590 SpaprDimmState *dimm_state = NULL;
3591
3592 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
3593 if (dimm_state->dimm == dimm) {
3594 break;
3595 }
3596 }
3597 return dimm_state;
3598}
3599
3600static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr,
3601 uint32_t nr_lmbs,
3602 PCDIMMDevice *dimm)
3603{
3604 SpaprDimmState *ds = NULL;
3605
3606
3607
3608
3609
3610
3611
3612 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
3613 if (!ds) {
3614 ds = g_malloc0(sizeof(SpaprDimmState));
3615 ds->nr_lmbs = nr_lmbs;
3616 ds->dimm = dimm;
3617 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3618 }
3619 return ds;
3620}
3621
3622static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr,
3623 SpaprDimmState *dimm_state)
3624{
3625 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3626 g_free(dimm_state);
3627}
3628
3629static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms,
3630 PCDIMMDevice *dimm)
3631{
3632 SpaprDrc *drc;
3633 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm),
3634 &error_abort);
3635 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3636 uint32_t avail_lmbs = 0;
3637 uint64_t addr_start, addr;
3638 int i;
3639
3640 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3641 &error_abort);
3642
3643 addr = addr_start;
3644 for (i = 0; i < nr_lmbs; i++) {
3645 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3646 addr / SPAPR_MEMORY_BLOCK_SIZE);
3647 g_assert(drc);
3648 if (drc->dev) {
3649 avail_lmbs++;
3650 }
3651 addr += SPAPR_MEMORY_BLOCK_SIZE;
3652 }
3653
3654 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3655}
3656
3657
3658void spapr_lmb_release(DeviceState *dev)
3659{
3660 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3661 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl);
3662 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3663
3664
3665
3666 if (ds == NULL) {
3667 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3668 g_assert(ds);
3669
3670 g_assert(ds->nr_lmbs);
3671 }
3672
3673 if (--ds->nr_lmbs) {
3674 return;
3675 }
3676
3677
3678
3679
3680
3681 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3682 object_unparent(OBJECT(dev));
3683}
3684
3685static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3686{
3687 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3688 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3689
3690 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev));
3691 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
3692 spapr_pending_dimm_unplugs_remove(spapr, ds);
3693}
3694
3695static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3696 DeviceState *dev, Error **errp)
3697{
3698 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3699 Error *local_err = NULL;
3700 PCDIMMDevice *dimm = PC_DIMM(dev);
3701 uint32_t nr_lmbs;
3702 uint64_t size, addr_start, addr;
3703 int i;
3704 SpaprDrc *drc;
3705
3706 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
3707 error_setg(&local_err,
3708 "nvdimm device hot unplug is not supported yet.");
3709 goto out;
3710 }
3711
3712 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort);
3713 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3714
3715 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3716 &local_err);
3717 if (local_err) {
3718 goto out;
3719 }
3720
3721
3722
3723
3724
3725
3726
3727 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3728 error_setg(&local_err,
3729 "Memory unplug already in progress for device %s",
3730 dev->id);
3731 goto out;
3732 }
3733
3734 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3735
3736 addr = addr_start;
3737 for (i = 0; i < nr_lmbs; i++) {
3738 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3739 addr / SPAPR_MEMORY_BLOCK_SIZE);
3740 g_assert(drc);
3741
3742 spapr_drc_detach(drc);
3743 addr += SPAPR_MEMORY_BLOCK_SIZE;
3744 }
3745
3746 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3747 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3748 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3749 nr_lmbs, spapr_drc_index(drc));
3750out:
3751 error_propagate(errp, local_err);
3752}
3753
3754
3755void spapr_core_release(DeviceState *dev)
3756{
3757 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3758
3759
3760 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3761 object_unparent(OBJECT(dev));
3762}
3763
3764static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3765{
3766 MachineState *ms = MACHINE(hotplug_dev);
3767 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3768 CPUCore *cc = CPU_CORE(dev);
3769 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3770
3771 if (smc->pre_2_10_has_unused_icps) {
3772 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3773 int i;
3774
3775 for (i = 0; i < cc->nr_threads; i++) {
3776 CPUState *cs = CPU(sc->threads[i]);
3777
3778 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3779 }
3780 }
3781
3782 assert(core_slot);
3783 core_slot->cpu = NULL;
3784 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
3785}
3786
3787static
3788void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3789 Error **errp)
3790{
3791 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3792 int index;
3793 SpaprDrc *drc;
3794 CPUCore *cc = CPU_CORE(dev);
3795
3796 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3797 error_setg(errp, "Unable to find CPU core with core-id: %d",
3798 cc->core_id);
3799 return;
3800 }
3801 if (index == 0) {
3802 error_setg(errp, "Boot CPU core may not be unplugged");
3803 return;
3804 }
3805
3806 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3807 spapr_vcpu_id(spapr, cc->core_id));
3808 g_assert(drc);
3809
3810 if (!spapr_drc_unplug_requested(drc)) {
3811 spapr_drc_detach(drc);
3812 spapr_hotplug_req_remove_by_index(drc);
3813 }
3814}
3815
3816int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3817 void *fdt, int *fdt_start_offset, Error **errp)
3818{
3819 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev);
3820 CPUState *cs = CPU(core->threads[0]);
3821 PowerPCCPU *cpu = POWERPC_CPU(cs);
3822 DeviceClass *dc = DEVICE_GET_CLASS(cs);
3823 int id = spapr_get_vcpu_id(cpu);
3824 char *nodename;
3825 int offset;
3826
3827 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3828 offset = fdt_add_subnode(fdt, 0, nodename);
3829 g_free(nodename);
3830
3831 spapr_dt_cpu(cs, fdt, offset, spapr);
3832
3833 *fdt_start_offset = offset;
3834 return 0;
3835}
3836
3837static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3838 Error **errp)
3839{
3840 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3841 MachineClass *mc = MACHINE_GET_CLASS(spapr);
3842 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3843 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3844 CPUCore *cc = CPU_CORE(dev);
3845 CPUState *cs;
3846 SpaprDrc *drc;
3847 Error *local_err = NULL;
3848 CPUArchId *core_slot;
3849 int index;
3850 bool hotplugged = spapr_drc_hotplugged(dev);
3851 int i;
3852
3853 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3854 if (!core_slot) {
3855 error_setg(errp, "Unable to find CPU core with core-id: %d",
3856 cc->core_id);
3857 return;
3858 }
3859 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3860 spapr_vcpu_id(spapr, cc->core_id));
3861
3862 g_assert(drc || !mc->has_hotpluggable_cpus);
3863
3864 if (drc) {
3865 spapr_drc_attach(drc, dev, &local_err);
3866 if (local_err) {
3867 error_propagate(errp, local_err);
3868 return;
3869 }
3870
3871 if (hotplugged) {
3872
3873
3874
3875
3876 spapr_hotplug_req_add_by_index(drc);
3877 } else {
3878 spapr_drc_reset(drc);
3879 }
3880 }
3881
3882 core_slot->cpu = OBJECT(dev);
3883
3884 if (smc->pre_2_10_has_unused_icps) {
3885 for (i = 0; i < cc->nr_threads; i++) {
3886 cs = CPU(core->threads[i]);
3887 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3888 }
3889 }
3890
3891
3892
3893
3894
3895 if (hotplugged) {
3896 for (i = 0; i < cc->nr_threads; i++) {
3897 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr,
3898 &local_err);
3899 if (local_err) {
3900 error_propagate(errp, local_err);
3901 return;
3902 }
3903 }
3904 }
3905}
3906
3907static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3908 Error **errp)
3909{
3910 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3911 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3912 Error *local_err = NULL;
3913 CPUCore *cc = CPU_CORE(dev);
3914 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type);
3915 const char *type = object_get_typename(OBJECT(dev));
3916 CPUArchId *core_slot;
3917 int index;
3918 unsigned int smp_threads = machine->smp.threads;
3919
3920 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3921 error_setg(&local_err, "CPU hotplug not supported for this machine");
3922 goto out;
3923 }
3924
3925 if (strcmp(base_core_type, type)) {
3926 error_setg(&local_err, "CPU core type should be %s", base_core_type);
3927 goto out;
3928 }
3929
3930 if (cc->core_id % smp_threads) {
3931 error_setg(&local_err, "invalid core id %d", cc->core_id);
3932 goto out;
3933 }
3934
3935
3936
3937
3938
3939
3940
3941 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3942 error_setg(&local_err, "invalid nr-threads %d, must be %d",
3943 cc->nr_threads, smp_threads);
3944 goto out;
3945 }
3946
3947 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3948 if (!core_slot) {
3949 error_setg(&local_err, "core id %d out of range", cc->core_id);
3950 goto out;
3951 }
3952
3953 if (core_slot->cpu) {
3954 error_setg(&local_err, "core %d already populated", cc->core_id);
3955 goto out;
3956 }
3957
3958 numa_cpu_pre_plug(core_slot, dev, &local_err);
3959
3960out:
3961 error_propagate(errp, local_err);
3962}
3963
3964int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3965 void *fdt, int *fdt_start_offset, Error **errp)
3966{
3967 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev);
3968 int intc_phandle;
3969
3970 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp);
3971 if (intc_phandle <= 0) {
3972 return -1;
3973 }
3974
3975 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) {
3976 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index);
3977 return -1;
3978 }
3979
3980
3981 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci"));
3982
3983 return 0;
3984}
3985
3986static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3987 Error **errp)
3988{
3989 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3990 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3991 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3992 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
3993
3994 if (dev->hotplugged && !smc->dr_phb_enabled) {
3995 error_setg(errp, "PHB hotplug not supported for this machine");
3996 return;
3997 }
3998
3999 if (sphb->index == (uint32_t)-1) {
4000 error_setg(errp, "\"index\" for PAPR PHB is mandatory");
4001 return;
4002 }
4003
4004
4005
4006
4007
4008 smc->phb_placement(spapr, sphb->index,
4009 &sphb->buid, &sphb->io_win_addr,
4010 &sphb->mem_win_addr, &sphb->mem64_win_addr,
4011 windows_supported, sphb->dma_liobn,
4012 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr,
4013 errp);
4014}
4015
4016static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
4017 Error **errp)
4018{
4019 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
4020 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
4021 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
4022 SpaprDrc *drc;
4023 bool hotplugged = spapr_drc_hotplugged(dev);
4024 Error *local_err = NULL;
4025
4026 if (!smc->dr_phb_enabled) {
4027 return;
4028 }
4029
4030 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index);
4031
4032 assert(drc);
4033
4034 spapr_drc_attach(drc, DEVICE(dev), &local_err);
4035 if (local_err) {
4036 error_propagate(errp, local_err);
4037 return;
4038 }
4039
4040 if (hotplugged) {
4041 spapr_hotplug_req_add_by_index(drc);
4042 } else {
4043 spapr_drc_reset(drc);
4044 }
4045}
4046
4047void spapr_phb_release(DeviceState *dev)
4048{
4049 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
4050
4051 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
4052 object_unparent(OBJECT(dev));
4053}
4054
4055static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
4056{
4057 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
4058}
4059
4060static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev,
4061 DeviceState *dev, Error **errp)
4062{
4063 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
4064 SpaprDrc *drc;
4065
4066 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index);
4067 assert(drc);
4068
4069 if (!spapr_drc_unplug_requested(drc)) {
4070 spapr_drc_detach(drc);
4071 spapr_hotplug_req_remove_by_index(drc);
4072 }
4073}
4074
4075static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
4076 Error **errp)
4077{
4078 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
4079 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev);
4080
4081 if (spapr->tpm_proxy != NULL) {
4082 error_setg(errp, "Only one TPM proxy can be specified for this machine");
4083 return;
4084 }
4085
4086 spapr->tpm_proxy = tpm_proxy;
4087}
4088
4089static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
4090{
4091 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
4092
4093 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
4094 object_unparent(OBJECT(dev));
4095 spapr->tpm_proxy = NULL;
4096}
4097
4098static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
4099 DeviceState *dev, Error **errp)
4100{
4101 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4102 spapr_memory_plug(hotplug_dev, dev, errp);
4103 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4104 spapr_core_plug(hotplug_dev, dev, errp);
4105 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4106 spapr_phb_plug(hotplug_dev, dev, errp);
4107 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) {
4108 spapr_tpm_proxy_plug(hotplug_dev, dev, errp);
4109 }
4110}
4111
4112static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
4113 DeviceState *dev, Error **errp)
4114{
4115 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4116 spapr_memory_unplug(hotplug_dev, dev);
4117 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4118 spapr_core_unplug(hotplug_dev, dev);
4119 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4120 spapr_phb_unplug(hotplug_dev, dev);
4121 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) {
4122 spapr_tpm_proxy_unplug(hotplug_dev, dev);
4123 }
4124}
4125
4126static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
4127 DeviceState *dev, Error **errp)
4128{
4129 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
4130 MachineClass *mc = MACHINE_GET_CLASS(sms);
4131 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4132
4133 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4134 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
4135 spapr_memory_unplug_request(hotplug_dev, dev, errp);
4136 } else {
4137
4138
4139
4140
4141
4142
4143 error_setg(errp, "Memory hot unplug not supported for this guest");
4144 }
4145 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4146 if (!mc->has_hotpluggable_cpus) {
4147 error_setg(errp, "CPU hot unplug not supported on this machine");
4148 return;
4149 }
4150 spapr_core_unplug_request(hotplug_dev, dev, errp);
4151 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4152 if (!smc->dr_phb_enabled) {
4153 error_setg(errp, "PHB hot unplug not supported on this machine");
4154 return;
4155 }
4156 spapr_phb_unplug_request(hotplug_dev, dev, errp);
4157 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) {
4158 spapr_tpm_proxy_unplug(hotplug_dev, dev);
4159 }
4160}
4161
4162static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
4163 DeviceState *dev, Error **errp)
4164{
4165 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4166 spapr_memory_pre_plug(hotplug_dev, dev, errp);
4167 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4168 spapr_core_pre_plug(hotplug_dev, dev, errp);
4169 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4170 spapr_phb_pre_plug(hotplug_dev, dev, errp);
4171 }
4172}
4173
4174static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
4175 DeviceState *dev)
4176{
4177 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
4178 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) ||
4179 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) ||
4180 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) {
4181 return HOTPLUG_HANDLER(machine);
4182 }
4183 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
4184 PCIDevice *pcidev = PCI_DEVICE(dev);
4185 PCIBus *root = pci_device_root_bus(pcidev);
4186 SpaprPhbState *phb =
4187 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent),
4188 TYPE_SPAPR_PCI_HOST_BRIDGE);
4189
4190 if (phb) {
4191 return HOTPLUG_HANDLER(phb);
4192 }
4193 }
4194 return NULL;
4195}
4196
4197static CpuInstanceProperties
4198spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
4199{
4200 CPUArchId *core_slot;
4201 MachineClass *mc = MACHINE_GET_CLASS(machine);
4202
4203
4204 mc->possible_cpu_arch_ids(machine);
4205
4206 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
4207 assert(core_slot);
4208 return core_slot->props;
4209}
4210
4211static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
4212{
4213 return idx / ms->smp.cores % ms->numa_state->num_nodes;
4214}
4215
4216static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
4217{
4218 int i;
4219 unsigned int smp_threads = machine->smp.threads;
4220 unsigned int smp_cpus = machine->smp.cpus;
4221 const char *core_type;
4222 int spapr_max_cores = machine->smp.max_cpus / smp_threads;
4223 MachineClass *mc = MACHINE_GET_CLASS(machine);
4224
4225 if (!mc->has_hotpluggable_cpus) {
4226 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
4227 }
4228 if (machine->possible_cpus) {
4229 assert(machine->possible_cpus->len == spapr_max_cores);
4230 return machine->possible_cpus;
4231 }
4232
4233 core_type = spapr_get_cpu_core_type(machine->cpu_type);
4234 if (!core_type) {
4235 error_report("Unable to find sPAPR CPU Core definition");
4236 exit(1);
4237 }
4238
4239 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
4240 sizeof(CPUArchId) * spapr_max_cores);
4241 machine->possible_cpus->len = spapr_max_cores;
4242 for (i = 0; i < machine->possible_cpus->len; i++) {
4243 int core_id = i * smp_threads;
4244
4245 machine->possible_cpus->cpus[i].type = core_type;
4246 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
4247 machine->possible_cpus->cpus[i].arch_id = core_id;
4248 machine->possible_cpus->cpus[i].props.has_core_id = true;
4249 machine->possible_cpus->cpus[i].props.core_id = core_id;
4250 }
4251 return machine->possible_cpus;
4252}
4253
4254static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index,
4255 uint64_t *buid, hwaddr *pio,
4256 hwaddr *mmio32, hwaddr *mmio64,
4257 unsigned n_dma, uint32_t *liobns,
4258 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4259{
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275 const uint64_t base_buid = 0x800000020000000ULL;
4276 int i;
4277
4278
4279 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
4280 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
4281 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
4282 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
4283
4284 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
4285 SPAPR_PCI_MEM32_WIN_SIZE);
4286 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
4287 SPAPR_PCI_MEM64_WIN_SIZE);
4288
4289 if (index >= SPAPR_MAX_PHBS) {
4290 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
4291 SPAPR_MAX_PHBS - 1);
4292 return;
4293 }
4294
4295 *buid = base_buid + index;
4296 for (i = 0; i < n_dma; ++i) {
4297 liobns[i] = SPAPR_PCI_LIOBN(index, i);
4298 }
4299
4300 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
4301 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
4302 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
4303
4304 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE;
4305 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE;
4306}
4307
4308static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
4309{
4310 SpaprMachineState *spapr = SPAPR_MACHINE(dev);
4311
4312 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
4313}
4314
4315static void spapr_ics_resend(XICSFabric *dev)
4316{
4317 SpaprMachineState *spapr = SPAPR_MACHINE(dev);
4318
4319 ics_resend(spapr->ics);
4320}
4321
4322static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
4323{
4324 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
4325
4326 return cpu ? spapr_cpu_state(cpu)->icp : NULL;
4327}
4328
4329static void spapr_pic_print_info(InterruptStatsProvider *obj,
4330 Monitor *mon)
4331{
4332 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
4333
4334 spapr_irq_print_info(spapr, mon);
4335 monitor_printf(mon, "irqchip: %s\n",
4336 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
4337}
4338
4339
4340
4341
4342static int spapr_match_nvt(XiveFabric *xfb, uint8_t format,
4343 uint8_t nvt_blk, uint32_t nvt_idx,
4344 bool cam_ignore, uint8_t priority,
4345 uint32_t logic_serv, XiveTCTXMatch *match)
4346{
4347 SpaprMachineState *spapr = SPAPR_MACHINE(xfb);
4348 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc);
4349 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
4350 int count;
4351
4352 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
4353 priority, logic_serv, match);
4354 if (count < 0) {
4355 return count;
4356 }
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367 if (count == 0) {
4368 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n",
4369 nvt_blk, nvt_idx);
4370 }
4371
4372 return count;
4373}
4374
4375int spapr_get_vcpu_id(PowerPCCPU *cpu)
4376{
4377 return cpu->vcpu_id;
4378}
4379
4380void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp)
4381{
4382 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
4383 MachineState *ms = MACHINE(spapr);
4384 int vcpu_id;
4385
4386 vcpu_id = spapr_vcpu_id(spapr, cpu_index);
4387
4388 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) {
4389 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id);
4390 error_append_hint(errp, "Adjust the number of cpus to %d "
4391 "or try to raise the number of threads per core\n",
4392 vcpu_id * ms->smp.threads / spapr->vsmt);
4393 return;
4394 }
4395
4396 cpu->vcpu_id = vcpu_id;
4397}
4398
4399PowerPCCPU *spapr_find_cpu(int vcpu_id)
4400{
4401 CPUState *cs;
4402
4403 CPU_FOREACH(cs) {
4404 PowerPCCPU *cpu = POWERPC_CPU(cs);
4405
4406 if (spapr_get_vcpu_id(cpu) == vcpu_id) {
4407 return cpu;
4408 }
4409 }
4410
4411 return NULL;
4412}
4413
4414static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
4415{
4416 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
4417
4418
4419
4420 spapr_cpu->prod = false;
4421 if (spapr_cpu->vpa_addr) {
4422 CPUState *cs = CPU(cpu);
4423 uint32_t dispatch;
4424
4425 dispatch = ldl_be_phys(cs->as,
4426 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER);
4427 dispatch++;
4428 if ((dispatch & 1) != 0) {
4429 qemu_log_mask(LOG_GUEST_ERROR,
4430 "VPA: incorrect dispatch counter value for "
4431 "dispatched partition %u, correcting.\n", dispatch);
4432 dispatch++;
4433 }
4434 stl_be_phys(cs->as,
4435 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch);
4436 }
4437}
4438
4439static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
4440{
4441 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
4442
4443 if (spapr_cpu->vpa_addr) {
4444 CPUState *cs = CPU(cpu);
4445 uint32_t dispatch;
4446
4447 dispatch = ldl_be_phys(cs->as,
4448 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER);
4449 dispatch++;
4450 if ((dispatch & 1) != 1) {
4451 qemu_log_mask(LOG_GUEST_ERROR,
4452 "VPA: incorrect dispatch counter value for "
4453 "preempted partition %u, correcting.\n", dispatch);
4454 dispatch++;
4455 }
4456 stl_be_phys(cs->as,
4457 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch);
4458 }
4459}
4460
4461static void spapr_machine_class_init(ObjectClass *oc, void *data)
4462{
4463 MachineClass *mc = MACHINE_CLASS(oc);
4464 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
4465 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
4466 NMIClass *nc = NMI_CLASS(oc);
4467 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
4468 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
4469 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
4470 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
4471 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
4472
4473 mc->desc = "pSeries Logical Partition (PAPR compliant)";
4474 mc->ignore_boot_device_suffixes = true;
4475
4476
4477
4478
4479
4480
4481 mc->init = spapr_machine_init;
4482 mc->reset = spapr_machine_reset;
4483 mc->block_default_type = IF_SCSI;
4484 mc->max_cpus = 1024;
4485 mc->no_parallel = 1;
4486 mc->default_boot_order = "";
4487 mc->default_ram_size = 512 * MiB;
4488 mc->default_ram_id = "ppc_spapr.ram";
4489 mc->default_display = "std";
4490 mc->kvm_type = spapr_kvm_type;
4491 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
4492 mc->pci_allow_0_address = true;
4493 assert(!mc->get_hotplug_handler);
4494 mc->get_hotplug_handler = spapr_get_hotplug_handler;
4495 hc->pre_plug = spapr_machine_device_pre_plug;
4496 hc->plug = spapr_machine_device_plug;
4497 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
4498 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
4499 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
4500 hc->unplug_request = spapr_machine_device_unplug_request;
4501 hc->unplug = spapr_machine_device_unplug;
4502
4503 smc->dr_lmb_enabled = true;
4504 smc->update_dt_enabled = true;
4505 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
4506 mc->has_hotpluggable_cpus = true;
4507 mc->nvdimm_supported = true;
4508 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
4509 fwc->get_dev_path = spapr_get_fw_dev_path;
4510 nc->nmi_monitor_handler = spapr_nmi;
4511 smc->phb_placement = spapr_phb_placement;
4512 vhc->hypercall = emulate_spapr_hypercall;
4513 vhc->hpt_mask = spapr_hpt_mask;
4514 vhc->map_hptes = spapr_map_hptes;
4515 vhc->unmap_hptes = spapr_unmap_hptes;
4516 vhc->hpte_set_c = spapr_hpte_set_c;
4517 vhc->hpte_set_r = spapr_hpte_set_r;
4518 vhc->get_pate = spapr_get_pate;
4519 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
4520 vhc->cpu_exec_enter = spapr_cpu_exec_enter;
4521 vhc->cpu_exec_exit = spapr_cpu_exec_exit;
4522 xic->ics_get = spapr_ics_get;
4523 xic->ics_resend = spapr_ics_resend;
4524 xic->icp_get = spapr_icp_get;
4525 ispc->print_info = spapr_pic_print_info;
4526
4527
4528
4529
4530 mc->numa_mem_align_shift = 28;
4531 mc->numa_mem_supported = true;
4532 mc->auto_enable_numa = true;
4533
4534 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
4535 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON;
4536 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON;
4537 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4538 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4539 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND;
4540 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16;
4541 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF;
4542 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON;
4543 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON;
4544 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON;
4545 spapr_caps_add_properties(smc, &error_abort);
4546 smc->irq = &spapr_irq_dual;
4547 smc->dr_phb_enabled = true;
4548 smc->linux_pci_probe = true;
4549 smc->smp_threads_vsmt = true;
4550 smc->nr_xirqs = SPAPR_NR_XIRQS;
4551 xfc->match_nvt = spapr_match_nvt;
4552}
4553
4554static const TypeInfo spapr_machine_info = {
4555 .name = TYPE_SPAPR_MACHINE,
4556 .parent = TYPE_MACHINE,
4557 .abstract = true,
4558 .instance_size = sizeof(SpaprMachineState),
4559 .instance_init = spapr_instance_init,
4560 .instance_finalize = spapr_machine_finalizefn,
4561 .class_size = sizeof(SpaprMachineClass),
4562 .class_init = spapr_machine_class_init,
4563 .interfaces = (InterfaceInfo[]) {
4564 { TYPE_FW_PATH_PROVIDER },
4565 { TYPE_NMI },
4566 { TYPE_HOTPLUG_HANDLER },
4567 { TYPE_PPC_VIRTUAL_HYPERVISOR },
4568 { TYPE_XICS_FABRIC },
4569 { TYPE_INTERRUPT_STATS_PROVIDER },
4570 { TYPE_XIVE_FABRIC },
4571 { }
4572 },
4573};
4574
4575static void spapr_machine_latest_class_options(MachineClass *mc)
4576{
4577 mc->alias = "pseries";
4578 mc->is_default = true;
4579}
4580
4581#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4582 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4583 void *data) \
4584 { \
4585 MachineClass *mc = MACHINE_CLASS(oc); \
4586 spapr_machine_##suffix##_class_options(mc); \
4587 if (latest) { \
4588 spapr_machine_latest_class_options(mc); \
4589 } \
4590 } \
4591 static const TypeInfo spapr_machine_##suffix##_info = { \
4592 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4593 .parent = TYPE_SPAPR_MACHINE, \
4594 .class_init = spapr_machine_##suffix##_class_init, \
4595 }; \
4596 static void spapr_machine_register_##suffix(void) \
4597 { \
4598 type_register(&spapr_machine_##suffix##_info); \
4599 } \
4600 type_init(spapr_machine_register_##suffix)
4601
4602
4603
4604
4605static void spapr_machine_5_0_class_options(MachineClass *mc)
4606{
4607
4608}
4609
4610DEFINE_SPAPR_MACHINE(5_0, "5.0", true);
4611
4612
4613
4614
4615static void spapr_machine_4_2_class_options(MachineClass *mc)
4616{
4617 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4618
4619 spapr_machine_5_0_class_options(mc);
4620 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
4621 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF;
4622 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF;
4623 smc->rma_limit = 16 * GiB;
4624 mc->nvdimm_supported = false;
4625}
4626
4627DEFINE_SPAPR_MACHINE(4_2, "4.2", false);
4628
4629
4630
4631
4632static void spapr_machine_4_1_class_options(MachineClass *mc)
4633{
4634 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4635 static GlobalProperty compat[] = {
4636
4637 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" },
4638 };
4639
4640 spapr_machine_4_2_class_options(mc);
4641 smc->linux_pci_probe = false;
4642 smc->smp_threads_vsmt = false;
4643 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
4644 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4645}
4646
4647DEFINE_SPAPR_MACHINE(4_1, "4.1", false);
4648
4649
4650
4651
4652static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index,
4653 uint64_t *buid, hwaddr *pio,
4654 hwaddr *mmio32, hwaddr *mmio64,
4655 unsigned n_dma, uint32_t *liobns,
4656 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4657{
4658 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns,
4659 nv2gpa, nv2atsd, errp);
4660 *nv2gpa = 0;
4661 *nv2atsd = 0;
4662}
4663
4664static void spapr_machine_4_0_class_options(MachineClass *mc)
4665{
4666 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4667
4668 spapr_machine_4_1_class_options(mc);
4669 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
4670 smc->phb_placement = phb_placement_4_0;
4671 smc->irq = &spapr_irq_xics;
4672 smc->pre_4_1_migration = true;
4673}
4674
4675DEFINE_SPAPR_MACHINE(4_0, "4.0", false);
4676
4677
4678
4679
4680static void spapr_machine_3_1_class_options(MachineClass *mc)
4681{
4682 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4683
4684 spapr_machine_4_0_class_options(mc);
4685 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
4686
4687 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
4688 smc->update_dt_enabled = false;
4689 smc->dr_phb_enabled = false;
4690 smc->broken_host_serial_model = true;
4691 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
4692 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
4693 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
4694 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF;
4695}
4696
4697DEFINE_SPAPR_MACHINE(3_1, "3.1", false);
4698
4699
4700
4701
4702
4703static void spapr_machine_3_0_class_options(MachineClass *mc)
4704{
4705 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4706
4707 spapr_machine_3_1_class_options(mc);
4708 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
4709
4710 smc->legacy_irq_allocation = true;
4711 smc->nr_xirqs = 0x400;
4712 smc->irq = &spapr_irq_xics_legacy;
4713}
4714
4715DEFINE_SPAPR_MACHINE(3_0, "3.0", false);
4716
4717
4718
4719
4720static void spapr_machine_2_12_class_options(MachineClass *mc)
4721{
4722 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4723 static GlobalProperty compat[] = {
4724 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" },
4725 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" },
4726 };
4727
4728 spapr_machine_3_0_class_options(mc);
4729 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
4730 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4731
4732
4733
4734
4735
4736
4737 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0;
4738}
4739
4740DEFINE_SPAPR_MACHINE(2_12, "2.12", false);
4741
4742static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc)
4743{
4744 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4745
4746 spapr_machine_2_12_class_options(mc);
4747 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4748 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4749 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD;
4750}
4751
4752DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false);
4753
4754
4755
4756
4757
4758static void spapr_machine_2_11_class_options(MachineClass *mc)
4759{
4760 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4761
4762 spapr_machine_2_12_class_options(mc);
4763 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON;
4764 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
4765}
4766
4767DEFINE_SPAPR_MACHINE(2_11, "2.11", false);
4768
4769
4770
4771
4772
4773static void spapr_machine_2_10_class_options(MachineClass *mc)
4774{
4775 spapr_machine_2_11_class_options(mc);
4776 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
4777}
4778
4779DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
4780
4781
4782
4783
4784
4785static void spapr_machine_2_9_class_options(MachineClass *mc)
4786{
4787 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4788 static GlobalProperty compat[] = {
4789 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" },
4790 };
4791
4792 spapr_machine_2_10_class_options(mc);
4793 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
4794 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4795 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
4796 smc->pre_2_10_has_unused_icps = true;
4797 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
4798}
4799
4800DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
4801
4802
4803
4804
4805
4806static void spapr_machine_2_8_class_options(MachineClass *mc)
4807{
4808 static GlobalProperty compat[] = {
4809 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" },
4810 };
4811
4812 spapr_machine_2_9_class_options(mc);
4813 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
4814 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4815 mc->numa_mem_align_shift = 23;
4816}
4817
4818DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
4819
4820
4821
4822
4823
4824static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index,
4825 uint64_t *buid, hwaddr *pio,
4826 hwaddr *mmio32, hwaddr *mmio64,
4827 unsigned n_dma, uint32_t *liobns,
4828 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4829{
4830
4831 const uint64_t base_buid = 0x800000020000000ULL;
4832 const hwaddr phb_spacing = 0x1000000000ULL;
4833 const hwaddr mmio_offset = 0xa0000000;
4834 const hwaddr pio_offset = 0x80000000;
4835 const uint32_t max_index = 255;
4836 const hwaddr phb0_alignment = 0x10000000000ULL;
4837
4838 uint64_t ram_top = MACHINE(spapr)->ram_size;
4839 hwaddr phb0_base, phb_base;
4840 int i;
4841
4842
4843 if (MACHINE(spapr)->maxram_size > ram_top) {
4844
4845
4846
4847 ram_top = MACHINE(spapr)->device_memory->base +
4848 memory_region_size(&MACHINE(spapr)->device_memory->mr);
4849 }
4850
4851 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
4852
4853 if (index > max_index) {
4854 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
4855 max_index);
4856 return;
4857 }
4858
4859 *buid = base_buid + index;
4860 for (i = 0; i < n_dma; ++i) {
4861 liobns[i] = SPAPR_PCI_LIOBN(index, i);
4862 }
4863
4864 phb_base = phb0_base + index * phb_spacing;
4865 *pio = phb_base + pio_offset;
4866 *mmio32 = phb_base + mmio_offset;
4867
4868
4869
4870
4871
4872
4873 *nv2gpa = 0;
4874 *nv2atsd = 0;
4875}
4876
4877static void spapr_machine_2_7_class_options(MachineClass *mc)
4878{
4879 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4880 static GlobalProperty compat[] = {
4881 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", },
4882 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", },
4883 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", },
4884 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", },
4885 };
4886
4887 spapr_machine_2_8_class_options(mc);
4888 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
4889 mc->default_machine_opts = "modern-hotplug-events=off";
4890 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
4891 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4892 smc->phb_placement = phb_placement_2_7;
4893}
4894
4895DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
4896
4897
4898
4899
4900
4901static void spapr_machine_2_6_class_options(MachineClass *mc)
4902{
4903 static GlobalProperty compat[] = {
4904 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" },
4905 };
4906
4907 spapr_machine_2_7_class_options(mc);
4908 mc->has_hotpluggable_cpus = false;
4909 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
4910 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4911}
4912
4913DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4914
4915
4916
4917
4918
4919static void spapr_machine_2_5_class_options(MachineClass *mc)
4920{
4921 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4922 static GlobalProperty compat[] = {
4923 { "spapr-vlan", "use-rx-buffer-pools", "off" },
4924 };
4925
4926 spapr_machine_2_6_class_options(mc);
4927 smc->use_ohci_by_default = true;
4928 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len);
4929 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4930}
4931
4932DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
4933
4934
4935
4936
4937
4938static void spapr_machine_2_4_class_options(MachineClass *mc)
4939{
4940 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4941
4942 spapr_machine_2_5_class_options(mc);
4943 smc->dr_lmb_enabled = false;
4944 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len);
4945}
4946
4947DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
4948
4949
4950
4951
4952
4953static void spapr_machine_2_3_class_options(MachineClass *mc)
4954{
4955 static GlobalProperty compat[] = {
4956 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
4957 };
4958 spapr_machine_2_4_class_options(mc);
4959 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len);
4960 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4961}
4962DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
4963
4964
4965
4966
4967
4968static void spapr_machine_2_2_class_options(MachineClass *mc)
4969{
4970 static GlobalProperty compat[] = {
4971 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" },
4972 };
4973
4974 spapr_machine_2_3_class_options(mc);
4975 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len);
4976 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4977 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on";
4978}
4979DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4980
4981
4982
4983
4984
4985static void spapr_machine_2_1_class_options(MachineClass *mc)
4986{
4987 spapr_machine_2_2_class_options(mc);
4988 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len);
4989}
4990DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
4991
4992static void spapr_machine_register_types(void)
4993{
4994 type_register_static(&spapr_machine_info);
4995}
4996
4997type_init(spapr_machine_register_types)
4998