qemu/hw/sparc/leon3.c
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   1/*
   2 * QEMU Leon3 System Emulator
   3 *
   4 * Copyright (c) 2010-2019 AdaCore
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "qemu/units.h"
  27#include "qemu/error-report.h"
  28#include "qapi/error.h"
  29#include "qemu-common.h"
  30#include "cpu.h"
  31#include "hw/irq.h"
  32#include "qemu/timer.h"
  33#include "hw/ptimer.h"
  34#include "hw/qdev-properties.h"
  35#include "sysemu/sysemu.h"
  36#include "sysemu/qtest.h"
  37#include "sysemu/reset.h"
  38#include "hw/boards.h"
  39#include "hw/loader.h"
  40#include "elf.h"
  41#include "trace.h"
  42#include "exec/address-spaces.h"
  43
  44#include "hw/sparc/grlib.h"
  45#include "hw/misc/grlib_ahb_apb_pnp.h"
  46
  47/* Default system clock.  */
  48#define CPU_CLK (40 * 1000 * 1000)
  49
  50#define LEON3_PROM_FILENAME "u-boot.bin"
  51#define LEON3_PROM_OFFSET    (0x00000000)
  52#define LEON3_RAM_OFFSET     (0x40000000)
  53
  54#define MAX_PILS 16
  55
  56#define LEON3_UART_OFFSET  (0x80000100)
  57#define LEON3_UART_IRQ     (3)
  58
  59#define LEON3_IRQMP_OFFSET (0x80000200)
  60
  61#define LEON3_TIMER_OFFSET (0x80000300)
  62#define LEON3_TIMER_IRQ    (6)
  63#define LEON3_TIMER_COUNT  (2)
  64
  65#define LEON3_APB_PNP_OFFSET (0x800FF000)
  66#define LEON3_AHB_PNP_OFFSET (0xFFFFF000)
  67
  68typedef struct ResetData {
  69    SPARCCPU *cpu;
  70    uint32_t  entry;            /* save kernel entry in case of reset */
  71    target_ulong sp;            /* initial stack pointer */
  72} ResetData;
  73
  74static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val)
  75{
  76    stl_p(code++, 0x82100000); /* mov %g0, %g1                */
  77    stl_p(code++, 0x84100000); /* mov %g0, %g2                */
  78    stl_p(code++, 0x03000000 +
  79      extract32(addr, 10, 22));
  80                               /* sethi %hi(addr), %g1        */
  81    stl_p(code++, 0x82106000 +
  82      extract32(addr, 0, 10));
  83                               /* or %g1, addr, %g1           */
  84    stl_p(code++, 0x05000000 +
  85      extract32(val, 10, 22));
  86                               /* sethi %hi(val), %g2         */
  87    stl_p(code++, 0x8410a000 +
  88      extract32(val, 0, 10));
  89                               /* or %g2, val, %g2            */
  90    stl_p(code++, 0xc4204000); /* st %g2, [ %g1 ]             */
  91
  92    return code;
  93}
  94
  95/*
  96 * When loading a kernel in RAM the machine is expected to be in a different
  97 * state (eg: initialized by the bootloader). This little code reproduces
  98 * this behavior.
  99 */
 100static void write_bootloader(CPUSPARCState *env, uint8_t *base,
 101                             hwaddr kernel_addr)
 102{
 103    uint32_t *p = (uint32_t *) base;
 104
 105    /* Initialize the UARTs                                        */
 106    /* *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE; */
 107    p = gen_store_u32(p, 0x80000108, 3);
 108
 109    /* Initialize the TIMER 0                                      */
 110    /* *GPTIMER_SCALER_RELOAD = 40 - 1;                            */
 111    p = gen_store_u32(p, 0x80000304, 39);
 112    /* *GPTIMER0_COUNTER_RELOAD = 0xFFFE;                          */
 113    p = gen_store_u32(p, 0x80000314, 0xFFFFFFFE);
 114    /* *GPTIMER0_CONFIG = GPTIMER_ENABLE | GPTIMER_RESTART;        */
 115    p = gen_store_u32(p, 0x80000318, 3);
 116
 117    /* JUMP to the entry point                                     */
 118    stl_p(p++, 0x82100000); /* mov %g0, %g1 */
 119    stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22));
 120                            /* sethi %hi(kernel_addr), %g1 */
 121    stl_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10));
 122                            /* or kernel_addr, %g1 */
 123    stl_p(p++, 0x81c04000); /* jmp  %g1 */
 124    stl_p(p++, 0x01000000); /* nop */
 125}
 126
 127static void main_cpu_reset(void *opaque)
 128{
 129    ResetData *s   = (ResetData *)opaque;
 130    CPUState *cpu = CPU(s->cpu);
 131    CPUSPARCState  *env = &s->cpu->env;
 132
 133    cpu_reset(cpu);
 134
 135    cpu->halted = 0;
 136    env->pc     = s->entry;
 137    env->npc    = s->entry + 4;
 138    env->regbase[6] = s->sp;
 139}
 140
 141void leon3_irq_ack(void *irq_manager, int intno)
 142{
 143    grlib_irqmp_ack((DeviceState *)irq_manager, intno);
 144}
 145
 146/*
 147 * This device assumes that the incoming 'level' value on the
 148 * qemu_irq is the interrupt number, not just a simple 0/1 level.
 149 */
 150static void leon3_set_pil_in(void *opaque, int n, int level)
 151{
 152    CPUSPARCState *env = opaque;
 153    uint32_t pil_in = level;
 154    CPUState *cs;
 155
 156    assert(env != NULL);
 157
 158    env->pil_in = pil_in;
 159
 160    if (env->pil_in && (env->interrupt_index == 0 ||
 161                        (env->interrupt_index & ~15) == TT_EXTINT)) {
 162        unsigned int i;
 163
 164        for (i = 15; i > 0; i--) {
 165            if (env->pil_in & (1 << i)) {
 166                int old_interrupt = env->interrupt_index;
 167
 168                env->interrupt_index = TT_EXTINT | i;
 169                if (old_interrupt != env->interrupt_index) {
 170                    cs = env_cpu(env);
 171                    trace_leon3_set_irq(i);
 172                    cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 173                }
 174                break;
 175            }
 176        }
 177    } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
 178        cs = env_cpu(env);
 179        trace_leon3_reset_irq(env->interrupt_index & 15);
 180        env->interrupt_index = 0;
 181        cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 182    }
 183}
 184
 185static void leon3_generic_hw_init(MachineState *machine)
 186{
 187    ram_addr_t ram_size = machine->ram_size;
 188    const char *kernel_filename = machine->kernel_filename;
 189    SPARCCPU *cpu;
 190    CPUSPARCState   *env;
 191    MemoryRegion *address_space_mem = get_system_memory();
 192    MemoryRegion *prom = g_new(MemoryRegion, 1);
 193    int         ret;
 194    char       *filename;
 195    qemu_irq   *cpu_irqs = NULL;
 196    int         bios_size;
 197    int         prom_size;
 198    ResetData  *reset_info;
 199    DeviceState *dev;
 200    int i;
 201    AHBPnp *ahb_pnp;
 202    APBPnp *apb_pnp;
 203
 204    /* Init CPU */
 205    cpu = SPARC_CPU(cpu_create(machine->cpu_type));
 206    env = &cpu->env;
 207
 208    cpu_sparc_set_id(env, 0);
 209
 210    /* Reset data */
 211    reset_info        = g_malloc0(sizeof(ResetData));
 212    reset_info->cpu   = cpu;
 213    reset_info->sp    = LEON3_RAM_OFFSET + ram_size;
 214    qemu_register_reset(main_cpu_reset, reset_info);
 215
 216    ahb_pnp = GRLIB_AHB_PNP(object_new(TYPE_GRLIB_AHB_PNP));
 217    object_property_set_bool(OBJECT(ahb_pnp), true, "realized", &error_fatal);
 218    sysbus_mmio_map(SYS_BUS_DEVICE(ahb_pnp), 0, LEON3_AHB_PNP_OFFSET);
 219    grlib_ahb_pnp_add_entry(ahb_pnp, 0, 0, GRLIB_VENDOR_GAISLER,
 220                            GRLIB_LEON3_DEV, GRLIB_AHB_MASTER,
 221                            GRLIB_CPU_AREA);
 222
 223    apb_pnp = GRLIB_APB_PNP(object_new(TYPE_GRLIB_APB_PNP));
 224    object_property_set_bool(OBJECT(apb_pnp), true, "realized", &error_fatal);
 225    sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET);
 226    grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF,
 227                            GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV,
 228                            GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA);
 229
 230    /* Allocate IRQ manager */
 231    dev = qdev_create(NULL, TYPE_GRLIB_IRQMP);
 232    qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in,
 233                                        env, "pil", 1);
 234    qdev_connect_gpio_out_named(dev, "grlib-irq", 0,
 235                                qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0));
 236    qdev_init_nofail(dev);
 237    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_IRQMP_OFFSET);
 238    env->irq_manager = dev;
 239    env->qemu_irq_ack = leon3_irq_manager;
 240    cpu_irqs = qemu_allocate_irqs(grlib_irqmp_set_irq, dev, MAX_PILS);
 241    grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF,
 242                            GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV,
 243                            2, 0, GRLIB_APBIO_AREA);
 244
 245    /* Allocate RAM */
 246    if (ram_size > 1 * GiB) {
 247        error_report("Too much memory for this machine: %" PRId64 "MB,"
 248                     " maximum 1G",
 249                     ram_size / MiB);
 250        exit(1);
 251    }
 252
 253    memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET,
 254                                machine->ram);
 255
 256    /* Allocate BIOS */
 257    prom_size = 8 * MiB;
 258    memory_region_init_rom(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
 259    memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom);
 260
 261    /* Load boot prom */
 262    if (bios_name == NULL) {
 263        bios_name = LEON3_PROM_FILENAME;
 264    }
 265    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 266
 267    if (filename) {
 268        bios_size = get_image_size(filename);
 269    } else {
 270        bios_size = -1;
 271    }
 272
 273    if (bios_size > prom_size) {
 274        error_report("could not load prom '%s': file too big", filename);
 275        exit(1);
 276    }
 277
 278    if (bios_size > 0) {
 279        ret = load_image_targphys(filename, LEON3_PROM_OFFSET, bios_size);
 280        if (ret < 0 || ret > prom_size) {
 281            error_report("could not load prom '%s'", filename);
 282            exit(1);
 283        }
 284    } else if (kernel_filename == NULL && !qtest_enabled()) {
 285        error_report("Can't read bios image '%s'", filename
 286                                                   ? filename
 287                                                   : LEON3_PROM_FILENAME);
 288        exit(1);
 289    }
 290    g_free(filename);
 291
 292    /* Can directly load an application. */
 293    if (kernel_filename != NULL) {
 294        long     kernel_size;
 295        uint64_t entry;
 296
 297        kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
 298                               &entry, NULL, NULL, NULL,
 299                               1 /* big endian */, EM_SPARC, 0, 0);
 300        if (kernel_size < 0) {
 301            kernel_size = load_uimage(kernel_filename, NULL, &entry,
 302                                      NULL, NULL, NULL);
 303        }
 304        if (kernel_size < 0) {
 305            error_report("could not load kernel '%s'", kernel_filename);
 306            exit(1);
 307        }
 308        if (bios_size <= 0) {
 309            /*
 310             * If there is no bios/monitor just start the application but put
 311             * the machine in an initialized state through a little
 312             * bootloader.
 313             */
 314            uint8_t *bootloader_entry;
 315
 316            bootloader_entry = memory_region_get_ram_ptr(prom);
 317            write_bootloader(env, bootloader_entry, entry);
 318            env->pc = LEON3_PROM_OFFSET;
 319            env->npc = LEON3_PROM_OFFSET + 4;
 320            reset_info->entry = LEON3_PROM_OFFSET;
 321        }
 322    }
 323
 324    /* Allocate timers */
 325    dev = qdev_create(NULL, TYPE_GRLIB_GPTIMER);
 326    qdev_prop_set_uint32(dev, "nr-timers", LEON3_TIMER_COUNT);
 327    qdev_prop_set_uint32(dev, "frequency", CPU_CLK);
 328    qdev_prop_set_uint32(dev, "irq-line", LEON3_TIMER_IRQ);
 329    qdev_init_nofail(dev);
 330
 331    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_TIMER_OFFSET);
 332    for (i = 0; i < LEON3_TIMER_COUNT; i++) {
 333        sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
 334                           cpu_irqs[LEON3_TIMER_IRQ + i]);
 335    }
 336
 337    grlib_apb_pnp_add_entry(apb_pnp, LEON3_TIMER_OFFSET, 0xFFF,
 338                            GRLIB_VENDOR_GAISLER, GRLIB_GPTIMER_DEV,
 339                            0, LEON3_TIMER_IRQ, GRLIB_APBIO_AREA);
 340
 341    /* Allocate uart */
 342    if (serial_hd(0)) {
 343        dev = qdev_create(NULL, TYPE_GRLIB_APB_UART);
 344        qdev_prop_set_chr(dev, "chrdev", serial_hd(0));
 345        qdev_init_nofail(dev);
 346        sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET);
 347        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irqs[LEON3_UART_IRQ]);
 348        grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF,
 349                                GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1,
 350                                LEON3_UART_IRQ, GRLIB_APBIO_AREA);
 351    }
 352}
 353
 354static void leon3_generic_machine_init(MachineClass *mc)
 355{
 356    mc->desc = "Leon-3 generic";
 357    mc->init = leon3_generic_hw_init;
 358    mc->default_cpu_type = SPARC_CPU_TYPE_NAME("LEON3");
 359    mc->default_ram_id = "leon3.ram";
 360}
 361
 362DEFINE_MACHINE("leon3_generic", leon3_generic_machine_init)
 363