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25#include "qemu/osdep.h"
26#include "qemu/units.h"
27#include "qapi/error.h"
28#include "qemu-common.h"
29#include "cpu.h"
30#include "hw/sysbus.h"
31#include "qemu/error-report.h"
32#include "qemu/timer.h"
33#include "hw/sparc/sun4m_iommu.h"
34#include "hw/rtc/m48t59.h"
35#include "migration/vmstate.h"
36#include "hw/sparc/sparc32_dma.h"
37#include "hw/block/fdc.h"
38#include "sysemu/reset.h"
39#include "sysemu/runstate.h"
40#include "sysemu/sysemu.h"
41#include "net/net.h"
42#include "hw/boards.h"
43#include "hw/scsi/esp.h"
44#include "hw/nvram/sun_nvram.h"
45#include "hw/qdev-properties.h"
46#include "hw/nvram/chrp_nvram.h"
47#include "hw/nvram/fw_cfg.h"
48#include "hw/char/escc.h"
49#include "hw/empty_slot.h"
50#include "hw/irq.h"
51#include "hw/loader.h"
52#include "elf.h"
53#include "trace.h"
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71#define KERNEL_LOAD_ADDR 0x00004000
72#define CMDLINE_ADDR 0x007ff000
73#define INITRD_LOAD_ADDR 0x00800000
74#define PROM_SIZE_MAX (1 * MiB)
75#define PROM_VADDR 0xffd00000
76#define PROM_FILENAME "openbios-sparc32"
77#define CFG_ADDR 0xd00000510ULL
78#define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
79#define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
80#define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
81
82#define MAX_CPUS 16
83#define MAX_PILS 16
84#define MAX_VSIMMS 4
85
86#define ESCC_CLOCK 4915200
87
88struct sun4m_hwdef {
89 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
90 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
91 hwaddr serial_base, fd_base;
92 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
93 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
94 hwaddr bpp_base, dbri_base, sx_base;
95 struct {
96 hwaddr reg_base, vram_base;
97 } vsimm[MAX_VSIMMS];
98 hwaddr ecc_base;
99 uint64_t max_mem;
100 uint32_t ecc_version;
101 uint32_t iommu_version;
102 uint16_t machine_id;
103 uint8_t nvram_machine_id;
104};
105
106const char *fw_cfg_arch_key_name(uint16_t key)
107{
108 static const struct {
109 uint16_t key;
110 const char *name;
111 } fw_cfg_arch_wellknown_keys[] = {
112 {FW_CFG_SUN4M_DEPTH, "depth"},
113 {FW_CFG_SUN4M_WIDTH, "width"},
114 {FW_CFG_SUN4M_HEIGHT, "height"},
115 };
116
117 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
118 if (fw_cfg_arch_wellknown_keys[i].key == key) {
119 return fw_cfg_arch_wellknown_keys[i].name;
120 }
121 }
122 return NULL;
123}
124
125static void fw_cfg_boot_set(void *opaque, const char *boot_device,
126 Error **errp)
127{
128 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
129}
130
131static void nvram_init(Nvram *nvram, uint8_t *macaddr,
132 const char *cmdline, const char *boot_devices,
133 ram_addr_t RAM_size, uint32_t kernel_size,
134 int width, int height, int depth,
135 int nvram_machine_id, const char *arch)
136{
137 unsigned int i;
138 int sysp_end;
139 uint8_t image[0x1ff0];
140 NvramClass *k = NVRAM_GET_CLASS(nvram);
141
142 memset(image, '\0', sizeof(image));
143
144
145 sysp_end = chrp_nvram_create_system_partition(image, 0);
146
147
148 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
149
150 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
151 nvram_machine_id);
152
153 for (i = 0; i < sizeof(image); i++) {
154 (k->write)(nvram, i, image[i]);
155 }
156}
157
158void cpu_check_irqs(CPUSPARCState *env)
159{
160 CPUState *cs;
161
162
163 g_assert(qemu_mutex_iothread_locked());
164
165 if (env->pil_in && (env->interrupt_index == 0 ||
166 (env->interrupt_index & ~15) == TT_EXTINT)) {
167 unsigned int i;
168
169 for (i = 15; i > 0; i--) {
170 if (env->pil_in & (1 << i)) {
171 int old_interrupt = env->interrupt_index;
172
173 env->interrupt_index = TT_EXTINT | i;
174 if (old_interrupt != env->interrupt_index) {
175 cs = env_cpu(env);
176 trace_sun4m_cpu_interrupt(i);
177 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
178 }
179 break;
180 }
181 }
182 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
183 cs = env_cpu(env);
184 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
185 env->interrupt_index = 0;
186 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
187 }
188}
189
190static void cpu_kick_irq(SPARCCPU *cpu)
191{
192 CPUSPARCState *env = &cpu->env;
193 CPUState *cs = CPU(cpu);
194
195 cs->halted = 0;
196 cpu_check_irqs(env);
197 qemu_cpu_kick(cs);
198}
199
200static void cpu_set_irq(void *opaque, int irq, int level)
201{
202 SPARCCPU *cpu = opaque;
203 CPUSPARCState *env = &cpu->env;
204
205 if (level) {
206 trace_sun4m_cpu_set_irq_raise(irq);
207 env->pil_in |= 1 << irq;
208 cpu_kick_irq(cpu);
209 } else {
210 trace_sun4m_cpu_set_irq_lower(irq);
211 env->pil_in &= ~(1 << irq);
212 cpu_check_irqs(env);
213 }
214}
215
216static void dummy_cpu_set_irq(void *opaque, int irq, int level)
217{
218}
219
220static void main_cpu_reset(void *opaque)
221{
222 SPARCCPU *cpu = opaque;
223 CPUState *cs = CPU(cpu);
224
225 cpu_reset(cs);
226 cs->halted = 0;
227}
228
229static void secondary_cpu_reset(void *opaque)
230{
231 SPARCCPU *cpu = opaque;
232 CPUState *cs = CPU(cpu);
233
234 cpu_reset(cs);
235 cs->halted = 1;
236}
237
238static void cpu_halt_signal(void *opaque, int irq, int level)
239{
240 if (level && current_cpu) {
241 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
242 }
243}
244
245static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
246{
247 return addr - 0xf0000000ULL;
248}
249
250static unsigned long sun4m_load_kernel(const char *kernel_filename,
251 const char *initrd_filename,
252 ram_addr_t RAM_size,
253 uint32_t *initrd_size)
254{
255 int linux_boot;
256 unsigned int i;
257 long kernel_size;
258 uint8_t *ptr;
259
260 linux_boot = (kernel_filename != NULL);
261
262 kernel_size = 0;
263 if (linux_boot) {
264 int bswap_needed;
265
266#ifdef BSWAP_NEEDED
267 bswap_needed = 1;
268#else
269 bswap_needed = 0;
270#endif
271 kernel_size = load_elf(kernel_filename, NULL,
272 translate_kernel_address, NULL,
273 NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
274 if (kernel_size < 0)
275 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
276 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
277 TARGET_PAGE_SIZE);
278 if (kernel_size < 0)
279 kernel_size = load_image_targphys(kernel_filename,
280 KERNEL_LOAD_ADDR,
281 RAM_size - KERNEL_LOAD_ADDR);
282 if (kernel_size < 0) {
283 error_report("could not load kernel '%s'", kernel_filename);
284 exit(1);
285 }
286
287
288 *initrd_size = 0;
289 if (initrd_filename) {
290 *initrd_size = load_image_targphys(initrd_filename,
291 INITRD_LOAD_ADDR,
292 RAM_size - INITRD_LOAD_ADDR);
293 if ((int)*initrd_size < 0) {
294 error_report("could not load initial ram disk '%s'",
295 initrd_filename);
296 exit(1);
297 }
298 }
299 if (*initrd_size > 0) {
300 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
301 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24);
302 if (ptr && ldl_p(ptr) == 0x48647253) {
303 stl_p(ptr + 16, INITRD_LOAD_ADDR);
304 stl_p(ptr + 20, *initrd_size);
305 break;
306 }
307 }
308 }
309 }
310 return kernel_size;
311}
312
313static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
314{
315 DeviceState *dev;
316 SysBusDevice *s;
317
318 dev = qdev_create(NULL, TYPE_SUN4M_IOMMU);
319 qdev_prop_set_uint32(dev, "version", version);
320 qdev_init_nofail(dev);
321 s = SYS_BUS_DEVICE(dev);
322 sysbus_connect_irq(s, 0, irq);
323 sysbus_mmio_map(s, 0, addr);
324
325 return s;
326}
327
328static void *sparc32_dma_init(hwaddr dma_base,
329 hwaddr esp_base, qemu_irq espdma_irq,
330 hwaddr le_base, qemu_irq ledma_irq)
331{
332 DeviceState *dma;
333 ESPDMADeviceState *espdma;
334 LEDMADeviceState *ledma;
335 SysBusESPState *esp;
336 SysBusPCNetState *lance;
337
338 dma = qdev_create(NULL, TYPE_SPARC32_DMA);
339 qdev_init_nofail(dma);
340 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
341
342 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
343 OBJECT(dma), "espdma"));
344 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
345
346 esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp"));
347 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
348 scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
349
350 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
351 OBJECT(dma), "ledma"));
352 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
353
354 lance = SYSBUS_PCNET(object_resolve_path_component(
355 OBJECT(ledma), "lance"));
356 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
357
358 return dma;
359}
360
361static DeviceState *slavio_intctl_init(hwaddr addr,
362 hwaddr addrg,
363 qemu_irq **parent_irq)
364{
365 DeviceState *dev;
366 SysBusDevice *s;
367 unsigned int i, j;
368
369 dev = qdev_create(NULL, "slavio_intctl");
370 qdev_init_nofail(dev);
371
372 s = SYS_BUS_DEVICE(dev);
373
374 for (i = 0; i < MAX_CPUS; i++) {
375 for (j = 0; j < MAX_PILS; j++) {
376 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
377 }
378 }
379 sysbus_mmio_map(s, 0, addrg);
380 for (i = 0; i < MAX_CPUS; i++) {
381 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
382 }
383
384 return dev;
385}
386
387#define SYS_TIMER_OFFSET 0x10000ULL
388#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
389
390static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
391 qemu_irq *cpu_irqs, unsigned int num_cpus)
392{
393 DeviceState *dev;
394 SysBusDevice *s;
395 unsigned int i;
396
397 dev = qdev_create(NULL, "slavio_timer");
398 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
399 qdev_init_nofail(dev);
400 s = SYS_BUS_DEVICE(dev);
401 sysbus_connect_irq(s, 0, master_irq);
402 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
403
404 for (i = 0; i < MAX_CPUS; i++) {
405 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
406 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
407 }
408}
409
410static qemu_irq slavio_system_powerdown;
411
412static void slavio_powerdown_req(Notifier *n, void *opaque)
413{
414 qemu_irq_raise(slavio_system_powerdown);
415}
416
417static Notifier slavio_system_powerdown_notifier = {
418 .notify = slavio_powerdown_req
419};
420
421#define MISC_LEDS 0x01600000
422#define MISC_CFG 0x01800000
423#define MISC_DIAG 0x01a00000
424#define MISC_MDM 0x01b00000
425#define MISC_SYS 0x01f00000
426
427static void slavio_misc_init(hwaddr base,
428 hwaddr aux1_base,
429 hwaddr aux2_base, qemu_irq irq,
430 qemu_irq fdc_tc)
431{
432 DeviceState *dev;
433 SysBusDevice *s;
434
435 dev = qdev_create(NULL, "slavio_misc");
436 qdev_init_nofail(dev);
437 s = SYS_BUS_DEVICE(dev);
438 if (base) {
439
440
441 sysbus_mmio_map(s, 0, base + MISC_CFG);
442
443 sysbus_mmio_map(s, 1, base + MISC_DIAG);
444
445 sysbus_mmio_map(s, 2, base + MISC_MDM);
446
447
448 sysbus_mmio_map(s, 3, base + MISC_LEDS);
449
450
451 sysbus_mmio_map(s, 4, base + MISC_SYS);
452 }
453 if (aux1_base) {
454
455 sysbus_mmio_map(s, 5, aux1_base);
456 }
457 if (aux2_base) {
458
459 sysbus_mmio_map(s, 6, aux2_base);
460 }
461 sysbus_connect_irq(s, 0, irq);
462 sysbus_connect_irq(s, 1, fdc_tc);
463 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
464 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
465}
466
467static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
468{
469 DeviceState *dev;
470 SysBusDevice *s;
471
472 dev = qdev_create(NULL, "eccmemctl");
473 qdev_prop_set_uint32(dev, "version", version);
474 qdev_init_nofail(dev);
475 s = SYS_BUS_DEVICE(dev);
476 sysbus_connect_irq(s, 0, irq);
477 sysbus_mmio_map(s, 0, base);
478 if (version == 0) {
479 sysbus_mmio_map(s, 1, base + 0x1000);
480 }
481}
482
483static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
484{
485 DeviceState *dev;
486 SysBusDevice *s;
487
488 dev = qdev_create(NULL, "apc");
489 qdev_init_nofail(dev);
490 s = SYS_BUS_DEVICE(dev);
491
492 sysbus_mmio_map(s, 0, power_base);
493 sysbus_connect_irq(s, 0, cpu_halt);
494}
495
496static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
497 int height, int depth)
498{
499 DeviceState *dev;
500 SysBusDevice *s;
501
502 dev = qdev_create(NULL, "SUNW,tcx");
503 qdev_prop_set_uint32(dev, "vram_size", vram_size);
504 qdev_prop_set_uint16(dev, "width", width);
505 qdev_prop_set_uint16(dev, "height", height);
506 qdev_prop_set_uint16(dev, "depth", depth);
507 qdev_init_nofail(dev);
508 s = SYS_BUS_DEVICE(dev);
509
510
511 sysbus_mmio_map(s, 0, addr);
512
513 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
514
515 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
516
517 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
518
519 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
520
521 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
522
523 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
524
525 if (depth == 8) {
526 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
527 } else {
528 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
529 }
530
531 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
532
533 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
534
535 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
536
537 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
538
539 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
540
541 if (depth == 8) {
542 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
543 }
544
545 sysbus_connect_irq(s, 0, irq);
546}
547
548static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
549 int height, int depth)
550{
551 DeviceState *dev;
552 SysBusDevice *s;
553
554 dev = qdev_create(NULL, "cgthree");
555 qdev_prop_set_uint32(dev, "vram-size", vram_size);
556 qdev_prop_set_uint16(dev, "width", width);
557 qdev_prop_set_uint16(dev, "height", height);
558 qdev_prop_set_uint16(dev, "depth", depth);
559 qdev_init_nofail(dev);
560 s = SYS_BUS_DEVICE(dev);
561
562
563 sysbus_mmio_map(s, 0, addr);
564
565 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
566
567 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
568
569 sysbus_connect_irq(s, 0, irq);
570}
571
572
573
574#define TYPE_MACIO_ID_REGISTER "macio_idreg"
575
576static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
577
578static void idreg_init(hwaddr addr)
579{
580 DeviceState *dev;
581 SysBusDevice *s;
582
583 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
584 qdev_init_nofail(dev);
585 s = SYS_BUS_DEVICE(dev);
586
587 sysbus_mmio_map(s, 0, addr);
588 address_space_write_rom(&address_space_memory, addr,
589 MEMTXATTRS_UNSPECIFIED,
590 idreg_data, sizeof(idreg_data));
591}
592
593#define MACIO_ID_REGISTER(obj) \
594 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
595
596typedef struct IDRegState {
597 SysBusDevice parent_obj;
598
599 MemoryRegion mem;
600} IDRegState;
601
602static void idreg_realize(DeviceState *ds, Error **errp)
603{
604 IDRegState *s = MACIO_ID_REGISTER(ds);
605 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
606 Error *local_err = NULL;
607
608 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
609 sizeof(idreg_data), &local_err);
610 if (local_err) {
611 error_propagate(errp, local_err);
612 return;
613 }
614
615 vmstate_register_ram_global(&s->mem);
616 memory_region_set_readonly(&s->mem, true);
617 sysbus_init_mmio(dev, &s->mem);
618}
619
620static void idreg_class_init(ObjectClass *oc, void *data)
621{
622 DeviceClass *dc = DEVICE_CLASS(oc);
623
624 dc->realize = idreg_realize;
625}
626
627static const TypeInfo idreg_info = {
628 .name = TYPE_MACIO_ID_REGISTER,
629 .parent = TYPE_SYS_BUS_DEVICE,
630 .instance_size = sizeof(IDRegState),
631 .class_init = idreg_class_init,
632};
633
634#define TYPE_TCX_AFX "tcx_afx"
635#define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
636
637typedef struct AFXState {
638 SysBusDevice parent_obj;
639
640 MemoryRegion mem;
641} AFXState;
642
643
644static void afx_init(hwaddr addr)
645{
646 DeviceState *dev;
647 SysBusDevice *s;
648
649 dev = qdev_create(NULL, TYPE_TCX_AFX);
650 qdev_init_nofail(dev);
651 s = SYS_BUS_DEVICE(dev);
652
653 sysbus_mmio_map(s, 0, addr);
654}
655
656static void afx_realize(DeviceState *ds, Error **errp)
657{
658 AFXState *s = TCX_AFX(ds);
659 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
660 Error *local_err = NULL;
661
662 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
663 &local_err);
664 if (local_err) {
665 error_propagate(errp, local_err);
666 return;
667 }
668
669 vmstate_register_ram_global(&s->mem);
670 sysbus_init_mmio(dev, &s->mem);
671}
672
673static void afx_class_init(ObjectClass *oc, void *data)
674{
675 DeviceClass *dc = DEVICE_CLASS(oc);
676
677 dc->realize = afx_realize;
678}
679
680static const TypeInfo afx_info = {
681 .name = TYPE_TCX_AFX,
682 .parent = TYPE_SYS_BUS_DEVICE,
683 .instance_size = sizeof(AFXState),
684 .class_init = afx_class_init,
685};
686
687#define TYPE_OPENPROM "openprom"
688#define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
689
690typedef struct PROMState {
691 SysBusDevice parent_obj;
692
693 MemoryRegion prom;
694} PROMState;
695
696
697static uint64_t translate_prom_address(void *opaque, uint64_t addr)
698{
699 hwaddr *base_addr = (hwaddr *)opaque;
700 return addr + *base_addr - PROM_VADDR;
701}
702
703static void prom_init(hwaddr addr, const char *bios_name)
704{
705 DeviceState *dev;
706 SysBusDevice *s;
707 char *filename;
708 int ret;
709
710 dev = qdev_create(NULL, TYPE_OPENPROM);
711 qdev_init_nofail(dev);
712 s = SYS_BUS_DEVICE(dev);
713
714 sysbus_mmio_map(s, 0, addr);
715
716
717 if (bios_name == NULL) {
718 bios_name = PROM_FILENAME;
719 }
720 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
721 if (filename) {
722 ret = load_elf(filename, NULL,
723 translate_prom_address, &addr, NULL,
724 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
725 if (ret < 0 || ret > PROM_SIZE_MAX) {
726 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
727 }
728 g_free(filename);
729 } else {
730 ret = -1;
731 }
732 if (ret < 0 || ret > PROM_SIZE_MAX) {
733 error_report("could not load prom '%s'", bios_name);
734 exit(1);
735 }
736}
737
738static void prom_realize(DeviceState *ds, Error **errp)
739{
740 PROMState *s = OPENPROM(ds);
741 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
742 Error *local_err = NULL;
743
744 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
745 PROM_SIZE_MAX, &local_err);
746 if (local_err) {
747 error_propagate(errp, local_err);
748 return;
749 }
750
751 vmstate_register_ram_global(&s->prom);
752 memory_region_set_readonly(&s->prom, true);
753 sysbus_init_mmio(dev, &s->prom);
754}
755
756static Property prom_properties[] = {
757 {},
758};
759
760static void prom_class_init(ObjectClass *klass, void *data)
761{
762 DeviceClass *dc = DEVICE_CLASS(klass);
763
764 device_class_set_props(dc, prom_properties);
765 dc->realize = prom_realize;
766}
767
768static const TypeInfo prom_info = {
769 .name = TYPE_OPENPROM,
770 .parent = TYPE_SYS_BUS_DEVICE,
771 .instance_size = sizeof(PROMState),
772 .class_init = prom_class_init,
773};
774
775#define TYPE_SUN4M_MEMORY "memory"
776#define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
777
778typedef struct RamDevice {
779 SysBusDevice parent_obj;
780 HostMemoryBackend *memdev;
781} RamDevice;
782
783
784static void ram_realize(DeviceState *dev, Error **errp)
785{
786 RamDevice *d = SUN4M_RAM(dev);
787 MemoryRegion *ram = host_memory_backend_get_memory(d->memdev);
788
789 sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram);
790}
791
792static void ram_initfn(Object *obj)
793{
794 RamDevice *d = SUN4M_RAM(obj);
795 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND,
796 (Object **)&d->memdev,
797 object_property_allow_set_link,
798 OBJ_PROP_LINK_STRONG, &error_abort);
799 object_property_set_description(obj, "memdev", "Set RAM backend"
800 "Valid value is ID of a hostmem backend",
801 &error_abort);
802}
803
804static void ram_class_init(ObjectClass *klass, void *data)
805{
806 DeviceClass *dc = DEVICE_CLASS(klass);
807
808 dc->realize = ram_realize;
809}
810
811static const TypeInfo ram_info = {
812 .name = TYPE_SUN4M_MEMORY,
813 .parent = TYPE_SYS_BUS_DEVICE,
814 .instance_size = sizeof(RamDevice),
815 .instance_init = ram_initfn,
816 .class_init = ram_class_init,
817};
818
819static void cpu_devinit(const char *cpu_type, unsigned int id,
820 uint64_t prom_addr, qemu_irq **cpu_irqs)
821{
822 CPUState *cs;
823 SPARCCPU *cpu;
824 CPUSPARCState *env;
825
826 cpu = SPARC_CPU(cpu_create(cpu_type));
827 env = &cpu->env;
828
829 cpu_sparc_set_id(env, id);
830 if (id == 0) {
831 qemu_register_reset(main_cpu_reset, cpu);
832 } else {
833 qemu_register_reset(secondary_cpu_reset, cpu);
834 cs = CPU(cpu);
835 cs->halted = 1;
836 }
837 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
838 env->prom_addr = prom_addr;
839}
840
841static void dummy_fdc_tc(void *opaque, int irq, int level)
842{
843}
844
845static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
846 MachineState *machine)
847{
848 DeviceState *slavio_intctl;
849 unsigned int i;
850 void *nvram;
851 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
852 qemu_irq fdc_tc;
853 unsigned long kernel_size;
854 uint32_t initrd_size;
855 DriveInfo *fd[MAX_FD];
856 FWCfgState *fw_cfg;
857 DeviceState *dev;
858 SysBusDevice *s;
859 unsigned int smp_cpus = machine->smp.cpus;
860 unsigned int max_cpus = machine->smp.max_cpus;
861 Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id,
862 TYPE_MEMORY_BACKEND, NULL);
863
864 if (machine->ram_size > hwdef->max_mem) {
865 error_report("Too much memory for this machine: %" PRId64 ","
866 " maximum %" PRId64,
867 machine->ram_size / MiB, hwdef->max_mem / MiB);
868 exit(1);
869 }
870
871
872 for(i = 0; i < smp_cpus; i++) {
873 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
874 }
875
876 for (i = smp_cpus; i < MAX_CPUS; i++)
877 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
878
879
880 dev = qdev_create(NULL, "memory");
881 object_property_set_link(OBJECT(dev), ram_memdev, "memdev", &error_fatal);
882 qdev_init_nofail(dev);
883 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0);
884
885
886 if (!hwdef->ecc_base) {
887 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
888 }
889
890 prom_init(hwdef->slavio_base, bios_name);
891
892 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
893 hwdef->intctl_base + 0x10000ULL,
894 cpu_irqs);
895
896 for (i = 0; i < 32; i++) {
897 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
898 }
899 for (i = 0; i < MAX_CPUS; i++) {
900 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
901 }
902
903 if (hwdef->idreg_base) {
904 idreg_init(hwdef->idreg_base);
905 }
906
907 if (hwdef->afx_base) {
908 afx_init(hwdef->afx_base);
909 }
910
911 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
912
913 if (hwdef->iommu_pad_base) {
914
915
916
917
918 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
919 }
920
921 sparc32_dma_init(hwdef->dma_base,
922 hwdef->esp_base, slavio_irq[18],
923 hwdef->le_base, slavio_irq[16]);
924
925 if (graphic_depth != 8 && graphic_depth != 24) {
926 error_report("Unsupported depth: %d", graphic_depth);
927 exit (1);
928 }
929 if (vga_interface_type != VGA_NONE) {
930 if (vga_interface_type == VGA_CG3) {
931 if (graphic_depth != 8) {
932 error_report("Unsupported depth: %d", graphic_depth);
933 exit(1);
934 }
935
936 if (!(graphic_width == 1024 && graphic_height == 768) &&
937 !(graphic_width == 1152 && graphic_height == 900)) {
938 error_report("Unsupported resolution: %d x %d", graphic_width,
939 graphic_height);
940 exit(1);
941 }
942
943
944 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
945 graphic_width, graphic_height, graphic_depth);
946 } else {
947
948 if (graphic_depth != 8 && graphic_depth != 24) {
949 error_report("Unsupported depth: %d", graphic_depth);
950 exit(1);
951 }
952
953 if (!(graphic_width == 1024 && graphic_height == 768)) {
954 error_report("Unsupported resolution: %d x %d",
955 graphic_width, graphic_height);
956 exit(1);
957 }
958
959 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
960 graphic_width, graphic_height, graphic_depth);
961 }
962 }
963
964 for (i = 0; i < MAX_VSIMMS; i++) {
965
966 if (hwdef->vsimm[i].reg_base) {
967 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
968 }
969 }
970
971 if (hwdef->sx_base) {
972 empty_slot_init(hwdef->sx_base, 0x2000);
973 }
974
975 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
976
977 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
978
979
980
981 dev = qdev_create(NULL, TYPE_ESCC);
982 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
983 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
984 qdev_prop_set_uint32(dev, "it_shift", 1);
985 qdev_prop_set_chr(dev, "chrB", NULL);
986 qdev_prop_set_chr(dev, "chrA", NULL);
987 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
988 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
989 qdev_init_nofail(dev);
990 s = SYS_BUS_DEVICE(dev);
991 sysbus_connect_irq(s, 0, slavio_irq[14]);
992 sysbus_connect_irq(s, 1, slavio_irq[14]);
993 sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
994
995 dev = qdev_create(NULL, TYPE_ESCC);
996 qdev_prop_set_uint32(dev, "disabled", 0);
997 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
998 qdev_prop_set_uint32(dev, "it_shift", 1);
999 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
1000 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
1001 qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
1002 qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
1003 qdev_init_nofail(dev);
1004
1005 s = SYS_BUS_DEVICE(dev);
1006 sysbus_connect_irq(s, 0, slavio_irq[15]);
1007 sysbus_connect_irq(s, 1, slavio_irq[15]);
1008 sysbus_mmio_map(s, 0, hwdef->serial_base);
1009
1010 if (hwdef->apc_base) {
1011 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
1012 }
1013
1014 if (hwdef->fd_base) {
1015
1016 memset(fd, 0, sizeof(fd));
1017 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1018 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1019 &fdc_tc);
1020 } else {
1021 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1022 }
1023
1024 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1025 slavio_irq[30], fdc_tc);
1026
1027 if (hwdef->cs_base) {
1028 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1029 slavio_irq[5]);
1030 }
1031
1032 if (hwdef->dbri_base) {
1033
1034
1035 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1036
1037 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1038 }
1039
1040 if (hwdef->bpp_base) {
1041
1042 empty_slot_init(hwdef->bpp_base, 0x20);
1043 }
1044
1045 initrd_size = 0;
1046 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1047 machine->initrd_filename,
1048 machine->ram_size, &initrd_size);
1049
1050 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1051 machine->boot_order, machine->ram_size, kernel_size,
1052 graphic_width, graphic_height, graphic_depth,
1053 hwdef->nvram_machine_id, "Sun4m");
1054
1055 if (hwdef->ecc_base)
1056 ecc_init(hwdef->ecc_base, slavio_irq[28],
1057 hwdef->ecc_version);
1058
1059 dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
1060 fw_cfg = FW_CFG(dev);
1061 qdev_prop_set_uint32(dev, "data_width", 1);
1062 qdev_prop_set_bit(dev, "dma_enabled", false);
1063 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1064 OBJECT(fw_cfg), NULL);
1065 qdev_init_nofail(dev);
1066 s = SYS_BUS_DEVICE(dev);
1067 sysbus_mmio_map(s, 0, CFG_ADDR);
1068 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
1069
1070 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1071 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1072 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
1073 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1074 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1075 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1076 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1077 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1078 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1079 if (machine->kernel_cmdline) {
1080 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1081 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1082 machine->kernel_cmdline);
1083 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1084 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1085 strlen(machine->kernel_cmdline) + 1);
1086 } else {
1087 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1088 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1089 }
1090 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1091 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1092 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1093 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1094}
1095
1096enum {
1097 ss5_id = 32,
1098 vger_id,
1099 lx_id,
1100 ss4_id,
1101 scls_id,
1102 sbook_id,
1103 ss10_id = 64,
1104 ss20_id,
1105 ss600mp_id,
1106};
1107
1108static const struct sun4m_hwdef sun4m_hwdefs[] = {
1109
1110 {
1111 .iommu_base = 0x10000000,
1112 .iommu_pad_base = 0x10004000,
1113 .iommu_pad_len = 0x0fffb000,
1114 .tcx_base = 0x50000000,
1115 .cs_base = 0x6c000000,
1116 .slavio_base = 0x70000000,
1117 .ms_kb_base = 0x71000000,
1118 .serial_base = 0x71100000,
1119 .nvram_base = 0x71200000,
1120 .fd_base = 0x71400000,
1121 .counter_base = 0x71d00000,
1122 .intctl_base = 0x71e00000,
1123 .idreg_base = 0x78000000,
1124 .dma_base = 0x78400000,
1125 .esp_base = 0x78800000,
1126 .le_base = 0x78c00000,
1127 .apc_base = 0x6a000000,
1128 .afx_base = 0x6e000000,
1129 .aux1_base = 0x71900000,
1130 .aux2_base = 0x71910000,
1131 .nvram_machine_id = 0x80,
1132 .machine_id = ss5_id,
1133 .iommu_version = 0x05000000,
1134 .max_mem = 0x10000000,
1135 },
1136
1137 {
1138 .iommu_base = 0xfe0000000ULL,
1139 .tcx_base = 0xe20000000ULL,
1140 .slavio_base = 0xff0000000ULL,
1141 .ms_kb_base = 0xff1000000ULL,
1142 .serial_base = 0xff1100000ULL,
1143 .nvram_base = 0xff1200000ULL,
1144 .fd_base = 0xff1700000ULL,
1145 .counter_base = 0xff1300000ULL,
1146 .intctl_base = 0xff1400000ULL,
1147 .idreg_base = 0xef0000000ULL,
1148 .dma_base = 0xef0400000ULL,
1149 .esp_base = 0xef0800000ULL,
1150 .le_base = 0xef0c00000ULL,
1151 .apc_base = 0xefa000000ULL,
1152 .aux1_base = 0xff1800000ULL,
1153 .aux2_base = 0xff1a01000ULL,
1154 .ecc_base = 0xf00000000ULL,
1155 .ecc_version = 0x10000000,
1156 .nvram_machine_id = 0x72,
1157 .machine_id = ss10_id,
1158 .iommu_version = 0x03000000,
1159 .max_mem = 0xf00000000ULL,
1160 },
1161
1162 {
1163 .iommu_base = 0xfe0000000ULL,
1164 .tcx_base = 0xe20000000ULL,
1165 .slavio_base = 0xff0000000ULL,
1166 .ms_kb_base = 0xff1000000ULL,
1167 .serial_base = 0xff1100000ULL,
1168 .nvram_base = 0xff1200000ULL,
1169 .counter_base = 0xff1300000ULL,
1170 .intctl_base = 0xff1400000ULL,
1171 .dma_base = 0xef0081000ULL,
1172 .esp_base = 0xef0080000ULL,
1173 .le_base = 0xef0060000ULL,
1174 .apc_base = 0xefa000000ULL,
1175 .aux1_base = 0xff1800000ULL,
1176 .aux2_base = 0xff1a01000ULL,
1177 .ecc_base = 0xf00000000ULL,
1178 .ecc_version = 0x00000000,
1179 .nvram_machine_id = 0x71,
1180 .machine_id = ss600mp_id,
1181 .iommu_version = 0x01000000,
1182 .max_mem = 0xf00000000ULL,
1183 },
1184
1185 {
1186 .iommu_base = 0xfe0000000ULL,
1187 .tcx_base = 0xe20000000ULL,
1188 .slavio_base = 0xff0000000ULL,
1189 .ms_kb_base = 0xff1000000ULL,
1190 .serial_base = 0xff1100000ULL,
1191 .nvram_base = 0xff1200000ULL,
1192 .fd_base = 0xff1700000ULL,
1193 .counter_base = 0xff1300000ULL,
1194 .intctl_base = 0xff1400000ULL,
1195 .idreg_base = 0xef0000000ULL,
1196 .dma_base = 0xef0400000ULL,
1197 .esp_base = 0xef0800000ULL,
1198 .le_base = 0xef0c00000ULL,
1199 .bpp_base = 0xef4800000ULL,
1200 .apc_base = 0xefa000000ULL,
1201 .aux1_base = 0xff1800000ULL,
1202 .aux2_base = 0xff1a01000ULL,
1203 .dbri_base = 0xee0000000ULL,
1204 .sx_base = 0xf80000000ULL,
1205 .vsimm = {
1206 {
1207 .reg_base = 0x9c000000ULL,
1208 .vram_base = 0xfc000000ULL
1209 }, {
1210 .reg_base = 0x90000000ULL,
1211 .vram_base = 0xf0000000ULL
1212 }, {
1213 .reg_base = 0x94000000ULL
1214 }, {
1215 .reg_base = 0x98000000ULL
1216 }
1217 },
1218 .ecc_base = 0xf00000000ULL,
1219 .ecc_version = 0x20000000,
1220 .nvram_machine_id = 0x72,
1221 .machine_id = ss20_id,
1222 .iommu_version = 0x13000000,
1223 .max_mem = 0xf00000000ULL,
1224 },
1225
1226 {
1227 .iommu_base = 0x10000000,
1228 .tcx_base = 0x50000000,
1229 .slavio_base = 0x70000000,
1230 .ms_kb_base = 0x71000000,
1231 .serial_base = 0x71100000,
1232 .nvram_base = 0x71200000,
1233 .fd_base = 0x71400000,
1234 .counter_base = 0x71d00000,
1235 .intctl_base = 0x71e00000,
1236 .idreg_base = 0x78000000,
1237 .dma_base = 0x78400000,
1238 .esp_base = 0x78800000,
1239 .le_base = 0x78c00000,
1240 .apc_base = 0x71300000,
1241 .aux1_base = 0x71900000,
1242 .aux2_base = 0x71910000,
1243 .nvram_machine_id = 0x80,
1244 .machine_id = vger_id,
1245 .iommu_version = 0x05000000,
1246 .max_mem = 0x10000000,
1247 },
1248
1249 {
1250 .iommu_base = 0x10000000,
1251 .iommu_pad_base = 0x10004000,
1252 .iommu_pad_len = 0x0fffb000,
1253 .tcx_base = 0x50000000,
1254 .slavio_base = 0x70000000,
1255 .ms_kb_base = 0x71000000,
1256 .serial_base = 0x71100000,
1257 .nvram_base = 0x71200000,
1258 .fd_base = 0x71400000,
1259 .counter_base = 0x71d00000,
1260 .intctl_base = 0x71e00000,
1261 .idreg_base = 0x78000000,
1262 .dma_base = 0x78400000,
1263 .esp_base = 0x78800000,
1264 .le_base = 0x78c00000,
1265 .aux1_base = 0x71900000,
1266 .aux2_base = 0x71910000,
1267 .nvram_machine_id = 0x80,
1268 .machine_id = lx_id,
1269 .iommu_version = 0x04000000,
1270 .max_mem = 0x10000000,
1271 },
1272
1273 {
1274 .iommu_base = 0x10000000,
1275 .tcx_base = 0x50000000,
1276 .cs_base = 0x6c000000,
1277 .slavio_base = 0x70000000,
1278 .ms_kb_base = 0x71000000,
1279 .serial_base = 0x71100000,
1280 .nvram_base = 0x71200000,
1281 .fd_base = 0x71400000,
1282 .counter_base = 0x71d00000,
1283 .intctl_base = 0x71e00000,
1284 .idreg_base = 0x78000000,
1285 .dma_base = 0x78400000,
1286 .esp_base = 0x78800000,
1287 .le_base = 0x78c00000,
1288 .apc_base = 0x6a000000,
1289 .aux1_base = 0x71900000,
1290 .aux2_base = 0x71910000,
1291 .nvram_machine_id = 0x80,
1292 .machine_id = ss4_id,
1293 .iommu_version = 0x05000000,
1294 .max_mem = 0x10000000,
1295 },
1296
1297 {
1298 .iommu_base = 0x10000000,
1299 .tcx_base = 0x50000000,
1300 .slavio_base = 0x70000000,
1301 .ms_kb_base = 0x71000000,
1302 .serial_base = 0x71100000,
1303 .nvram_base = 0x71200000,
1304 .fd_base = 0x71400000,
1305 .counter_base = 0x71d00000,
1306 .intctl_base = 0x71e00000,
1307 .idreg_base = 0x78000000,
1308 .dma_base = 0x78400000,
1309 .esp_base = 0x78800000,
1310 .le_base = 0x78c00000,
1311 .apc_base = 0x6a000000,
1312 .aux1_base = 0x71900000,
1313 .aux2_base = 0x71910000,
1314 .nvram_machine_id = 0x80,
1315 .machine_id = scls_id,
1316 .iommu_version = 0x05000000,
1317 .max_mem = 0x10000000,
1318 },
1319
1320 {
1321 .iommu_base = 0x10000000,
1322 .tcx_base = 0x50000000,
1323 .slavio_base = 0x70000000,
1324 .ms_kb_base = 0x71000000,
1325 .serial_base = 0x71100000,
1326 .nvram_base = 0x71200000,
1327 .fd_base = 0x71400000,
1328 .counter_base = 0x71d00000,
1329 .intctl_base = 0x71e00000,
1330 .idreg_base = 0x78000000,
1331 .dma_base = 0x78400000,
1332 .esp_base = 0x78800000,
1333 .le_base = 0x78c00000,
1334 .apc_base = 0x6a000000,
1335 .aux1_base = 0x71900000,
1336 .aux2_base = 0x71910000,
1337 .nvram_machine_id = 0x80,
1338 .machine_id = sbook_id,
1339 .iommu_version = 0x05000000,
1340 .max_mem = 0x10000000,
1341 },
1342};
1343
1344
1345static void ss5_init(MachineState *machine)
1346{
1347 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1348}
1349
1350
1351static void ss10_init(MachineState *machine)
1352{
1353 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1354}
1355
1356
1357static void ss600mp_init(MachineState *machine)
1358{
1359 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1360}
1361
1362
1363static void ss20_init(MachineState *machine)
1364{
1365 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1366}
1367
1368
1369static void vger_init(MachineState *machine)
1370{
1371 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1372}
1373
1374
1375static void ss_lx_init(MachineState *machine)
1376{
1377 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1378}
1379
1380
1381static void ss4_init(MachineState *machine)
1382{
1383 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1384}
1385
1386
1387static void scls_init(MachineState *machine)
1388{
1389 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1390}
1391
1392
1393static void sbook_init(MachineState *machine)
1394{
1395 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1396}
1397
1398static void ss5_class_init(ObjectClass *oc, void *data)
1399{
1400 MachineClass *mc = MACHINE_CLASS(oc);
1401
1402 mc->desc = "Sun4m platform, SPARCstation 5";
1403 mc->init = ss5_init;
1404 mc->block_default_type = IF_SCSI;
1405 mc->is_default = true;
1406 mc->default_boot_order = "c";
1407 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1408 mc->default_display = "tcx";
1409 mc->default_ram_id = "sun4m.ram";
1410}
1411
1412static const TypeInfo ss5_type = {
1413 .name = MACHINE_TYPE_NAME("SS-5"),
1414 .parent = TYPE_MACHINE,
1415 .class_init = ss5_class_init,
1416};
1417
1418static void ss10_class_init(ObjectClass *oc, void *data)
1419{
1420 MachineClass *mc = MACHINE_CLASS(oc);
1421
1422 mc->desc = "Sun4m platform, SPARCstation 10";
1423 mc->init = ss10_init;
1424 mc->block_default_type = IF_SCSI;
1425 mc->max_cpus = 4;
1426 mc->default_boot_order = "c";
1427 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1428 mc->default_display = "tcx";
1429 mc->default_ram_id = "sun4m.ram";
1430}
1431
1432static const TypeInfo ss10_type = {
1433 .name = MACHINE_TYPE_NAME("SS-10"),
1434 .parent = TYPE_MACHINE,
1435 .class_init = ss10_class_init,
1436};
1437
1438static void ss600mp_class_init(ObjectClass *oc, void *data)
1439{
1440 MachineClass *mc = MACHINE_CLASS(oc);
1441
1442 mc->desc = "Sun4m platform, SPARCserver 600MP";
1443 mc->init = ss600mp_init;
1444 mc->block_default_type = IF_SCSI;
1445 mc->max_cpus = 4;
1446 mc->default_boot_order = "c";
1447 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1448 mc->default_display = "tcx";
1449 mc->default_ram_id = "sun4m.ram";
1450}
1451
1452static const TypeInfo ss600mp_type = {
1453 .name = MACHINE_TYPE_NAME("SS-600MP"),
1454 .parent = TYPE_MACHINE,
1455 .class_init = ss600mp_class_init,
1456};
1457
1458static void ss20_class_init(ObjectClass *oc, void *data)
1459{
1460 MachineClass *mc = MACHINE_CLASS(oc);
1461
1462 mc->desc = "Sun4m platform, SPARCstation 20";
1463 mc->init = ss20_init;
1464 mc->block_default_type = IF_SCSI;
1465 mc->max_cpus = 4;
1466 mc->default_boot_order = "c";
1467 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1468 mc->default_display = "tcx";
1469 mc->default_ram_id = "sun4m.ram";
1470}
1471
1472static const TypeInfo ss20_type = {
1473 .name = MACHINE_TYPE_NAME("SS-20"),
1474 .parent = TYPE_MACHINE,
1475 .class_init = ss20_class_init,
1476};
1477
1478static void voyager_class_init(ObjectClass *oc, void *data)
1479{
1480 MachineClass *mc = MACHINE_CLASS(oc);
1481
1482 mc->desc = "Sun4m platform, SPARCstation Voyager";
1483 mc->init = vger_init;
1484 mc->block_default_type = IF_SCSI;
1485 mc->default_boot_order = "c";
1486 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1487 mc->default_display = "tcx";
1488 mc->default_ram_id = "sun4m.ram";
1489}
1490
1491static const TypeInfo voyager_type = {
1492 .name = MACHINE_TYPE_NAME("Voyager"),
1493 .parent = TYPE_MACHINE,
1494 .class_init = voyager_class_init,
1495};
1496
1497static void ss_lx_class_init(ObjectClass *oc, void *data)
1498{
1499 MachineClass *mc = MACHINE_CLASS(oc);
1500
1501 mc->desc = "Sun4m platform, SPARCstation LX";
1502 mc->init = ss_lx_init;
1503 mc->block_default_type = IF_SCSI;
1504 mc->default_boot_order = "c";
1505 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1506 mc->default_display = "tcx";
1507 mc->default_ram_id = "sun4m.ram";
1508}
1509
1510static const TypeInfo ss_lx_type = {
1511 .name = MACHINE_TYPE_NAME("LX"),
1512 .parent = TYPE_MACHINE,
1513 .class_init = ss_lx_class_init,
1514};
1515
1516static void ss4_class_init(ObjectClass *oc, void *data)
1517{
1518 MachineClass *mc = MACHINE_CLASS(oc);
1519
1520 mc->desc = "Sun4m platform, SPARCstation 4";
1521 mc->init = ss4_init;
1522 mc->block_default_type = IF_SCSI;
1523 mc->default_boot_order = "c";
1524 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1525 mc->default_display = "tcx";
1526 mc->default_ram_id = "sun4m.ram";
1527}
1528
1529static const TypeInfo ss4_type = {
1530 .name = MACHINE_TYPE_NAME("SS-4"),
1531 .parent = TYPE_MACHINE,
1532 .class_init = ss4_class_init,
1533};
1534
1535static void scls_class_init(ObjectClass *oc, void *data)
1536{
1537 MachineClass *mc = MACHINE_CLASS(oc);
1538
1539 mc->desc = "Sun4m platform, SPARCClassic";
1540 mc->init = scls_init;
1541 mc->block_default_type = IF_SCSI;
1542 mc->default_boot_order = "c";
1543 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1544 mc->default_display = "tcx";
1545 mc->default_ram_id = "sun4m.ram";
1546}
1547
1548static const TypeInfo scls_type = {
1549 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1550 .parent = TYPE_MACHINE,
1551 .class_init = scls_class_init,
1552};
1553
1554static void sbook_class_init(ObjectClass *oc, void *data)
1555{
1556 MachineClass *mc = MACHINE_CLASS(oc);
1557
1558 mc->desc = "Sun4m platform, SPARCbook";
1559 mc->init = sbook_init;
1560 mc->block_default_type = IF_SCSI;
1561 mc->default_boot_order = "c";
1562 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1563 mc->default_display = "tcx";
1564 mc->default_ram_id = "sun4m.ram";
1565}
1566
1567static const TypeInfo sbook_type = {
1568 .name = MACHINE_TYPE_NAME("SPARCbook"),
1569 .parent = TYPE_MACHINE,
1570 .class_init = sbook_class_init,
1571};
1572
1573static void sun4m_register_types(void)
1574{
1575 type_register_static(&idreg_info);
1576 type_register_static(&afx_info);
1577 type_register_static(&prom_info);
1578 type_register_static(&ram_info);
1579
1580 type_register_static(&ss5_type);
1581 type_register_static(&ss10_type);
1582 type_register_static(&ss600mp_type);
1583 type_register_static(&ss20_type);
1584 type_register_static(&voyager_type);
1585 type_register_static(&ss_lx_type);
1586 type_register_static(&ss4_type);
1587 type_register_static(&scls_type);
1588 type_register_static(&sbook_type);
1589}
1590
1591type_init(sun4m_register_types)
1592
