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18#include "qemu/osdep.h"
19#include "hw/qdev-properties.h"
20#include "hw/usb/hcd-ehci.h"
21#include "migration/vmstate.h"
22#include "qemu/module.h"
23
24static const VMStateDescription vmstate_ehci_sysbus = {
25 .name = "ehci-sysbus",
26 .version_id = 2,
27 .minimum_version_id = 1,
28 .fields = (VMStateField[]) {
29 VMSTATE_STRUCT(ehci, EHCISysBusState, 2, vmstate_ehci, EHCIState),
30 VMSTATE_END_OF_LIST()
31 }
32};
33
34static Property ehci_sysbus_properties[] = {
35 DEFINE_PROP_UINT32("maxframes", EHCISysBusState, ehci.maxframes, 128),
36 DEFINE_PROP_BOOL("companion-enable", EHCISysBusState, ehci.companion_enable,
37 false),
38 DEFINE_PROP_END_OF_LIST(),
39};
40
41static void usb_ehci_sysbus_realize(DeviceState *dev, Error **errp)
42{
43 SysBusDevice *d = SYS_BUS_DEVICE(dev);
44 EHCISysBusState *i = SYS_BUS_EHCI(dev);
45 EHCIState *s = &i->ehci;
46
47 usb_ehci_realize(s, dev, errp);
48 sysbus_init_irq(d, &s->irq);
49}
50
51static void usb_ehci_sysbus_reset(DeviceState *dev)
52{
53 SysBusDevice *d = SYS_BUS_DEVICE(dev);
54 EHCISysBusState *i = SYS_BUS_EHCI(d);
55 EHCIState *s = &i->ehci;
56
57 ehci_reset(s);
58}
59
60static void ehci_sysbus_init(Object *obj)
61{
62 SysBusDevice *d = SYS_BUS_DEVICE(obj);
63 EHCISysBusState *i = SYS_BUS_EHCI(obj);
64 SysBusEHCIClass *sec = SYS_BUS_EHCI_GET_CLASS(obj);
65 EHCIState *s = &i->ehci;
66
67 s->capsbase = sec->capsbase;
68 s->opregbase = sec->opregbase;
69 s->portscbase = sec->portscbase;
70 s->portnr = sec->portnr;
71 s->as = &address_space_memory;
72
73 usb_ehci_init(s, DEVICE(obj));
74 sysbus_init_mmio(d, &s->mem);
75}
76
77static void ehci_sysbus_class_init(ObjectClass *klass, void *data)
78{
79 DeviceClass *dc = DEVICE_CLASS(klass);
80 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(klass);
81
82 sec->portscbase = 0x44;
83 sec->portnr = NB_PORTS;
84
85 dc->realize = usb_ehci_sysbus_realize;
86 dc->vmsd = &vmstate_ehci_sysbus;
87 device_class_set_props(dc, ehci_sysbus_properties);
88 dc->reset = usb_ehci_sysbus_reset;
89 set_bit(DEVICE_CATEGORY_USB, dc->categories);
90}
91
92static const TypeInfo ehci_type_info = {
93 .name = TYPE_SYS_BUS_EHCI,
94 .parent = TYPE_SYS_BUS_DEVICE,
95 .instance_size = sizeof(EHCISysBusState),
96 .instance_init = ehci_sysbus_init,
97 .abstract = true,
98 .class_init = ehci_sysbus_class_init,
99 .class_size = sizeof(SysBusEHCIClass),
100};
101
102static void ehci_platform_class_init(ObjectClass *oc, void *data)
103{
104 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
105 DeviceClass *dc = DEVICE_CLASS(oc);
106
107 sec->capsbase = 0x0;
108 sec->opregbase = 0x20;
109 set_bit(DEVICE_CATEGORY_USB, dc->categories);
110}
111
112static const TypeInfo ehci_platform_type_info = {
113 .name = TYPE_PLATFORM_EHCI,
114 .parent = TYPE_SYS_BUS_EHCI,
115 .class_init = ehci_platform_class_init,
116};
117
118static void ehci_exynos4210_class_init(ObjectClass *oc, void *data)
119{
120 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
121 DeviceClass *dc = DEVICE_CLASS(oc);
122
123 sec->capsbase = 0x0;
124 sec->opregbase = 0x10;
125 set_bit(DEVICE_CATEGORY_USB, dc->categories);
126}
127
128static const TypeInfo ehci_exynos4210_type_info = {
129 .name = TYPE_EXYNOS4210_EHCI,
130 .parent = TYPE_SYS_BUS_EHCI,
131 .class_init = ehci_exynos4210_class_init,
132};
133
134static void ehci_aw_h3_class_init(ObjectClass *oc, void *data)
135{
136 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
137 DeviceClass *dc = DEVICE_CLASS(oc);
138
139 sec->capsbase = 0x0;
140 sec->opregbase = 0x10;
141 set_bit(DEVICE_CATEGORY_USB, dc->categories);
142}
143
144static const TypeInfo ehci_aw_h3_type_info = {
145 .name = TYPE_AW_H3_EHCI,
146 .parent = TYPE_SYS_BUS_EHCI,
147 .class_init = ehci_aw_h3_class_init,
148};
149
150static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
151{
152 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
153 DeviceClass *dc = DEVICE_CLASS(oc);
154
155 sec->capsbase = 0x100;
156 sec->opregbase = 0x140;
157 set_bit(DEVICE_CATEGORY_USB, dc->categories);
158}
159
160static const TypeInfo ehci_tegra2_type_info = {
161 .name = TYPE_TEGRA2_EHCI,
162 .parent = TYPE_SYS_BUS_EHCI,
163 .class_init = ehci_tegra2_class_init,
164};
165
166static void ehci_ppc4xx_init(Object *o)
167{
168 EHCISysBusState *s = SYS_BUS_EHCI(o);
169
170 s->ehci.companion_enable = true;
171}
172
173static void ehci_ppc4xx_class_init(ObjectClass *oc, void *data)
174{
175 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
176 DeviceClass *dc = DEVICE_CLASS(oc);
177
178 sec->capsbase = 0x0;
179 sec->opregbase = 0x10;
180 set_bit(DEVICE_CATEGORY_USB, dc->categories);
181}
182
183static const TypeInfo ehci_ppc4xx_type_info = {
184 .name = TYPE_PPC4xx_EHCI,
185 .parent = TYPE_SYS_BUS_EHCI,
186 .class_init = ehci_ppc4xx_class_init,
187 .instance_init = ehci_ppc4xx_init,
188};
189
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197
198
199enum FUSBH200EHCIRegs {
200 FUSBH200_REG_EOF_ASTR = 0x34,
201 FUSBH200_REG_BMCSR = 0x40,
202};
203
204static uint64_t fusbh200_ehci_read(void *opaque, hwaddr addr, unsigned size)
205{
206 EHCIState *s = opaque;
207 hwaddr off = s->opregbase + s->portscbase + 4 * s->portnr + addr;
208
209 switch (off) {
210 case FUSBH200_REG_EOF_ASTR:
211 return 0x00000041;
212 case FUSBH200_REG_BMCSR:
213
214 return (2 << 9) | (1 << 8) | (1 << 3);
215 }
216
217 return 0;
218}
219
220static void fusbh200_ehci_write(void *opaque, hwaddr addr, uint64_t val,
221 unsigned size)
222{
223}
224
225static const MemoryRegionOps fusbh200_ehci_mmio_ops = {
226 .read = fusbh200_ehci_read,
227 .write = fusbh200_ehci_write,
228 .valid.min_access_size = 4,
229 .valid.max_access_size = 4,
230 .endianness = DEVICE_LITTLE_ENDIAN,
231};
232
233static void fusbh200_ehci_init(Object *obj)
234{
235 EHCISysBusState *i = SYS_BUS_EHCI(obj);
236 FUSBH200EHCIState *f = FUSBH200_EHCI(obj);
237 EHCIState *s = &i->ehci;
238
239 memory_region_init_io(&f->mem_vendor, OBJECT(f), &fusbh200_ehci_mmio_ops, s,
240 "fusbh200", 0x4c);
241 memory_region_add_subregion(&s->mem,
242 s->opregbase + s->portscbase + 4 * s->portnr,
243 &f->mem_vendor);
244}
245
246static void fusbh200_ehci_class_init(ObjectClass *oc, void *data)
247{
248 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
249 DeviceClass *dc = DEVICE_CLASS(oc);
250
251 sec->capsbase = 0x0;
252 sec->opregbase = 0x10;
253 sec->portscbase = 0x20;
254 sec->portnr = 1;
255 set_bit(DEVICE_CATEGORY_USB, dc->categories);
256}
257
258static const TypeInfo ehci_fusbh200_type_info = {
259 .name = TYPE_FUSBH200_EHCI,
260 .parent = TYPE_SYS_BUS_EHCI,
261 .instance_size = sizeof(FUSBH200EHCIState),
262 .instance_init = fusbh200_ehci_init,
263 .class_init = fusbh200_ehci_class_init,
264};
265
266static void ehci_sysbus_register_types(void)
267{
268 type_register_static(&ehci_type_info);
269 type_register_static(&ehci_platform_type_info);
270 type_register_static(&ehci_exynos4210_type_info);
271 type_register_static(&ehci_aw_h3_type_info);
272 type_register_static(&ehci_tegra2_type_info);
273 type_register_static(&ehci_ppc4xx_type_info);
274 type_register_static(&ehci_fusbh200_type_info);
275}
276
277type_init(ehci_sysbus_register_types)
278
