LXR qemu/include/hw/pci-host/pnv

   1/*
   2 * QEMU PowerPC PowerNV (POWER9) PHB4 model
   3 *
   4 * Copyright (c) 2018-2020, IBM Corporation.
   5 *
   6 * This code is licensed under the GPL version 2 or later. See the
   7 * COPYING file in the top-level directory.
   8 */
   9
  10#ifndef PCI_HOST_PNV_PHB4_H
  11#define PCI_HOST_PNV_PHB4_H
  12
  13#include "hw/pci/pcie_host.h"
  14#include "hw/pci/pcie_port.h"
  15#include "hw/ppc/xive.h"
  16
  17typedef struct PnvPhb4PecState PnvPhb4PecState;
  18typedef struct PnvPhb4PecStack PnvPhb4PecStack;
  19typedef struct PnvPHB4 PnvPHB4;
  20typedef struct PnvChip PnvChip;
  21
  22/*
  23 * We have one such address space wrapper per possible device under
  24 * the PHB since they need to be assigned statically at qemu device
  25 * creation time. The relationship to a PE is done later
  26 * dynamically. This means we can potentially create a lot of these
  27 * guys. Q35 stores them as some kind of radix tree but we never
  28 * really need to do fast lookups so instead we simply keep a QLIST of
  29 * them for now, we can add the radix if needed later on.
  30 *
  31 * We do cache the PE number to speed things up a bit though.
  32 */
  33typedef struct PnvPhb4DMASpace {
  34    PCIBus *bus;
  35    uint8_t devfn;
  36    int pe_num;         /* Cached PE number */
  37#define PHB_INVALID_PE (-1)
  38    PnvPHB4 *phb;
  39    AddressSpace dma_as;
  40    IOMMUMemoryRegion dma_mr;
  41    MemoryRegion msi32_mr;
  42    MemoryRegion msi64_mr;
  43    QLIST_ENTRY(PnvPhb4DMASpace) list;
  44} PnvPhb4DMASpace;
  45
  46/*
  47 * PHB4 PCIe Root port
  48 */
  49#define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root-bus"
  50#define TYPE_PNV_PHB4_ROOT_PORT "pnv-phb4-root-port"
  51
  52typedef struct PnvPHB4RootPort {
  53    PCIESlot parent_obj;
  54} PnvPHB4RootPort;
  55
  56/*
  57 * PHB4 PCIe Host Bridge for PowerNV machines (POWER9)
  58 */
  59#define TYPE_PNV_PHB4 "pnv-phb4"
  60#define PNV_PHB4(obj) OBJECT_CHECK(PnvPHB4, (obj), TYPE_PNV_PHB4)
  61
  62#define PNV_PHB4_MAX_LSIs          8
  63#define PNV_PHB4_MAX_INTs          4096
  64#define PNV_PHB4_MAX_MIST          (PNV_PHB4_MAX_INTs >> 2)
  65#define PNV_PHB4_MAX_MMIO_WINDOWS  32
  66#define PNV_PHB4_MIN_MMIO_WINDOWS  16
  67#define PNV_PHB4_NUM_REGS          (0x3000 >> 3)
  68#define PNV_PHB4_MAX_PEs           512
  69#define PNV_PHB4_MAX_TVEs          (PNV_PHB4_MAX_PEs * 2)
  70#define PNV_PHB4_MAX_PEEVs         (PNV_PHB4_MAX_PEs / 64)
  71#define PNV_PHB4_MAX_MBEs          (PNV_PHB4_MAX_MMIO_WINDOWS * 2)
  72
  73#define PNV_PHB4_VERSION           0x000000a400000002ull
  74#define PNV_PHB4_DEVICE_ID         0x04c1
  75
  76#define PCI_MMIO_TOTAL_SIZE        (0x1ull << 60)
  77
  78struct PnvPHB4 {
  79    PCIExpressHost parent_obj;
  80
  81    PnvPHB4RootPort root;
  82
  83    uint32_t chip_id;
  84    uint32_t phb_id;
  85
  86    uint64_t version;
  87    uint16_t device_id;
  88
  89    char bus_path[8];
  90
  91    /* Main register images */
  92    uint64_t regs[PNV_PHB4_NUM_REGS];
  93    MemoryRegion mr_regs;
  94
  95    /* Extra SCOM-only register */
  96    uint64_t scom_hv_ind_addr_reg;
  97
  98    /*
  99     * Geometry of the PHB. There are two types, small and big PHBs, a
 100     * number of resources (number of PEs, windows etc...) are doubled
 101     * for a big PHB
 102     */
 103    bool big_phb;
 104
 105    /* Memory regions for MMIO space */
 106    MemoryRegion mr_mmio[PNV_PHB4_MAX_MMIO_WINDOWS];
 107
 108    /* PCI side space */
 109    MemoryRegion pci_mmio;
 110    MemoryRegion pci_io;
 111
 112    /* On-chip IODA tables */
 113    uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs];
 114    uint64_t ioda_MIST[PNV_PHB4_MAX_MIST];
 115    uint64_t ioda_TVT[PNV_PHB4_MAX_TVEs];
 116    uint64_t ioda_MBT[PNV_PHB4_MAX_MBEs];
 117    uint64_t ioda_MDT[PNV_PHB4_MAX_PEs];
 118    uint64_t ioda_PEEV[PNV_PHB4_MAX_PEEVs];
 119
 120    /*
 121     * The internal PESTA/B is 2 bits per PE split into two tables, we
 122     * store them in a single array here to avoid wasting space.
 123     */
 124    uint8_t  ioda_PEST_AB[PNV_PHB4_MAX_PEs];
 125
 126    /* P9 Interrupt generation */
 127    XiveSource xsrc;
 128    qemu_irq *qirqs;
 129
 130    PnvPhb4PecStack *stack;
 131
 132    QLIST_HEAD(, PnvPhb4DMASpace) dma_spaces;
 133};
 134
 135void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon);
 136void pnv_phb4_update_regions(PnvPhb4PecStack *stack);
 137extern const MemoryRegionOps pnv_phb4_xscom_ops;
 138
 139/*
 140 * PHB4 PEC (PCI Express Controller)
 141 */
 142#define TYPE_PNV_PHB4_PEC "pnv-phb4-pec"
 143#define PNV_PHB4_PEC(obj) \
 144    OBJECT_CHECK(PnvPhb4PecState, (obj), TYPE_PNV_PHB4_PEC)
 145
 146#define TYPE_PNV_PHB4_PEC_STACK "pnv-phb4-pec-stack"
 147#define PNV_PHB4_PEC_STACK(obj) \
 148    OBJECT_CHECK(PnvPhb4PecStack, (obj), TYPE_PNV_PHB4_PEC_STACK)
 149
 150/* Per-stack data */
 151struct PnvPhb4PecStack {
 152    DeviceState parent;
 153
 154    /* My own stack number */
 155    uint32_t stack_no;
 156
 157    /* Nest registers */
 158#define PHB4_PEC_NEST_STK_REGS_COUNT  0x17
 159    uint64_t nest_regs[PHB4_PEC_NEST_STK_REGS_COUNT];
 160    MemoryRegion nest_regs_mr;
 161
 162    /* PCI registers (excluding pass-through) */
 163#define PHB4_PEC_PCI_STK_REGS_COUNT  0xf
 164    uint64_t pci_regs[PHB4_PEC_PCI_STK_REGS_COUNT];
 165    MemoryRegion pci_regs_mr;
 166
 167    /* PHB pass-through XSCOM */
 168    MemoryRegion phb_regs_mr;
 169
 170    /* Memory windows from PowerBus to PHB */
 171    MemoryRegion mmbar0;
 172    MemoryRegion mmbar1;
 173    MemoryRegion phbbar;
 174    MemoryRegion intbar;
 175    uint64_t mmio0_base;
 176    uint64_t mmio0_size;
 177    uint64_t mmio1_base;
 178    uint64_t mmio1_size;
 179
 180    /* The owner PEC */
 181    PnvPhb4PecState *pec;
 182
 183    /* The actual PHB */
 184    PnvPHB4 phb;
 185};
 186
 187struct PnvPhb4PecState {
 188    DeviceState parent;
 189
 190    /* PEC number in chip */
 191    uint32_t index;
 192    uint32_t chip_id;
 193
 194    MemoryRegion *system_memory;
 195
 196    /* Nest registers, excuding per-stack */
 197#define PHB4_PEC_NEST_REGS_COUNT    0xf
 198    uint64_t nest_regs[PHB4_PEC_NEST_REGS_COUNT];
 199    MemoryRegion nest_regs_mr;
 200
 201    /* PCI registers, excluding per-stack */
 202#define PHB4_PEC_PCI_REGS_COUNT     0x2
 203    uint64_t pci_regs[PHB4_PEC_PCI_REGS_COUNT];
 204    MemoryRegion pci_regs_mr;
 205
 206    /* Stacks */
 207    #define PHB4_PEC_MAX_STACKS     3
 208    uint32_t num_stacks;
 209    PnvPhb4PecStack stacks[PHB4_PEC_MAX_STACKS];
 210};
 211
 212#define PNV_PHB4_PEC_CLASS(klass) \
 213     OBJECT_CLASS_CHECK(PnvPhb4PecClass, (klass), TYPE_PNV_PHB4_PEC)
 214#define PNV_PHB4_PEC_GET_CLASS(obj) \
 215     OBJECT_GET_CLASS(PnvPhb4PecClass, (obj), TYPE_PNV_PHB4_PEC)
 216
 217typedef struct PnvPhb4PecClass {
 218    DeviceClass parent_class;
 219
 220    uint32_t (*xscom_nest_base)(PnvPhb4PecState *pec);
 221    uint32_t xscom_nest_size;
 222    uint32_t (*xscom_pci_base)(PnvPhb4PecState *pec);
 223    uint32_t xscom_pci_size;
 224    const char *compat;
 225    int compat_size;
 226    const char *stk_compat;
 227    int stk_compat_size;
 228} PnvPhb4PecClass;
 229
 230#endif /* PCI_HOST_PNV_PHB4_H */
 231