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20#ifndef I386_CPU_H
21#define I386_CPU_H
22
23#include "sysemu/tcg.h"
24#include "cpu-qom.h"
25#include "hyperv-proto.h"
26#include "exec/cpu-defs.h"
27#include "qapi/qapi-types-common.h"
28
29
30#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
31
32
33#define TARGET_MAX_INSN_SIZE 16
34
35
36
37#define TARGET_HAS_PRECISE_SMC
38
39#ifdef TARGET_X86_64
40#define I386_ELF_MACHINE EM_X86_64
41#define ELF_MACHINE_UNAME "x86_64"
42#else
43#define I386_ELF_MACHINE EM_386
44#define ELF_MACHINE_UNAME "i686"
45#endif
46
47enum {
48 R_EAX = 0,
49 R_ECX = 1,
50 R_EDX = 2,
51 R_EBX = 3,
52 R_ESP = 4,
53 R_EBP = 5,
54 R_ESI = 6,
55 R_EDI = 7,
56 R_R8 = 8,
57 R_R9 = 9,
58 R_R10 = 10,
59 R_R11 = 11,
60 R_R12 = 12,
61 R_R13 = 13,
62 R_R14 = 14,
63 R_R15 = 15,
64
65 R_AL = 0,
66 R_CL = 1,
67 R_DL = 2,
68 R_BL = 3,
69 R_AH = 4,
70 R_CH = 5,
71 R_DH = 6,
72 R_BH = 7,
73};
74
75typedef enum X86Seg {
76 R_ES = 0,
77 R_CS = 1,
78 R_SS = 2,
79 R_DS = 3,
80 R_FS = 4,
81 R_GS = 5,
82 R_LDTR = 6,
83 R_TR = 7,
84} X86Seg;
85
86
87#define DESC_G_SHIFT 23
88#define DESC_G_MASK (1 << DESC_G_SHIFT)
89#define DESC_B_SHIFT 22
90#define DESC_B_MASK (1 << DESC_B_SHIFT)
91#define DESC_L_SHIFT 21
92#define DESC_L_MASK (1 << DESC_L_SHIFT)
93#define DESC_AVL_SHIFT 20
94#define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
95#define DESC_P_SHIFT 15
96#define DESC_P_MASK (1 << DESC_P_SHIFT)
97#define DESC_DPL_SHIFT 13
98#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
99#define DESC_S_SHIFT 12
100#define DESC_S_MASK (1 << DESC_S_SHIFT)
101#define DESC_TYPE_SHIFT 8
102#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
103#define DESC_A_MASK (1 << 8)
104
105#define DESC_CS_MASK (1 << 11)
106#define DESC_C_MASK (1 << 10)
107#define DESC_R_MASK (1 << 9)
108
109#define DESC_E_MASK (1 << 10)
110#define DESC_W_MASK (1 << 9)
111
112#define DESC_TSS_BUSY_MASK (1 << 9)
113
114
115#define CC_C 0x0001
116#define CC_P 0x0004
117#define CC_A 0x0010
118#define CC_Z 0x0040
119#define CC_S 0x0080
120#define CC_O 0x0800
121
122#define TF_SHIFT 8
123#define IOPL_SHIFT 12
124#define VM_SHIFT 17
125
126#define TF_MASK 0x00000100
127#define IF_MASK 0x00000200
128#define DF_MASK 0x00000400
129#define IOPL_MASK 0x00003000
130#define NT_MASK 0x00004000
131#define RF_MASK 0x00010000
132#define VM_MASK 0x00020000
133#define AC_MASK 0x00040000
134#define VIF_MASK 0x00080000
135#define VIP_MASK 0x00100000
136#define ID_MASK 0x00200000
137
138
139
140
141
142
143#define HF_CPL_SHIFT 0
144
145#define HF_INHIBIT_IRQ_SHIFT 3
146
147#define HF_CS32_SHIFT 4
148#define HF_SS32_SHIFT 5
149
150#define HF_ADDSEG_SHIFT 6
151
152#define HF_PE_SHIFT 7
153#define HF_TF_SHIFT 8
154#define HF_MP_SHIFT 9
155#define HF_EM_SHIFT 10
156#define HF_TS_SHIFT 11
157#define HF_IOPL_SHIFT 12
158#define HF_LMA_SHIFT 14
159#define HF_CS64_SHIFT 15
160#define HF_RF_SHIFT 16
161#define HF_VM_SHIFT 17
162#define HF_AC_SHIFT 18
163#define HF_SMM_SHIFT 19
164#define HF_SVME_SHIFT 20
165#define HF_GUEST_SHIFT 21
166#define HF_OSFXSR_SHIFT 22
167#define HF_SMAP_SHIFT 23
168#define HF_IOBPT_SHIFT 24
169#define HF_MPX_EN_SHIFT 25
170#define HF_MPX_IU_SHIFT 26
171
172#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
173#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
174#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
175#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
176#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
177#define HF_PE_MASK (1 << HF_PE_SHIFT)
178#define HF_TF_MASK (1 << HF_TF_SHIFT)
179#define HF_MP_MASK (1 << HF_MP_SHIFT)
180#define HF_EM_MASK (1 << HF_EM_SHIFT)
181#define HF_TS_MASK (1 << HF_TS_SHIFT)
182#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
183#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
184#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
185#define HF_RF_MASK (1 << HF_RF_SHIFT)
186#define HF_VM_MASK (1 << HF_VM_SHIFT)
187#define HF_AC_MASK (1 << HF_AC_SHIFT)
188#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
189#define HF_SVME_MASK (1 << HF_SVME_SHIFT)
190#define HF_GUEST_MASK (1 << HF_GUEST_SHIFT)
191#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
192#define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
193#define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
194#define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
195#define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
196
197
198
199#define HF2_GIF_SHIFT 0
200#define HF2_HIF_SHIFT 1
201#define HF2_NMI_SHIFT 2
202#define HF2_VINTR_SHIFT 3
203#define HF2_SMM_INSIDE_NMI_SHIFT 4
204#define HF2_MPX_PR_SHIFT 5
205#define HF2_NPT_SHIFT 6
206#define HF2_IGNNE_SHIFT 7
207
208#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
209#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
210#define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
211#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
212#define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
213#define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
214#define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
215#define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT)
216
217#define CR0_PE_SHIFT 0
218#define CR0_MP_SHIFT 1
219
220#define CR0_PE_MASK (1U << 0)
221#define CR0_MP_MASK (1U << 1)
222#define CR0_EM_MASK (1U << 2)
223#define CR0_TS_MASK (1U << 3)
224#define CR0_ET_MASK (1U << 4)
225#define CR0_NE_MASK (1U << 5)
226#define CR0_WP_MASK (1U << 16)
227#define CR0_AM_MASK (1U << 18)
228#define CR0_PG_MASK (1U << 31)
229
230#define CR4_VME_MASK (1U << 0)
231#define CR4_PVI_MASK (1U << 1)
232#define CR4_TSD_MASK (1U << 2)
233#define CR4_DE_MASK (1U << 3)
234#define CR4_PSE_MASK (1U << 4)
235#define CR4_PAE_MASK (1U << 5)
236#define CR4_MCE_MASK (1U << 6)
237#define CR4_PGE_MASK (1U << 7)
238#define CR4_PCE_MASK (1U << 8)
239#define CR4_OSFXSR_SHIFT 9
240#define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
241#define CR4_OSXMMEXCPT_MASK (1U << 10)
242#define CR4_LA57_MASK (1U << 12)
243#define CR4_VMXE_MASK (1U << 13)
244#define CR4_SMXE_MASK (1U << 14)
245#define CR4_FSGSBASE_MASK (1U << 16)
246#define CR4_PCIDE_MASK (1U << 17)
247#define CR4_OSXSAVE_MASK (1U << 18)
248#define CR4_SMEP_MASK (1U << 20)
249#define CR4_SMAP_MASK (1U << 21)
250#define CR4_PKE_MASK (1U << 22)
251
252#define DR6_BD (1 << 13)
253#define DR6_BS (1 << 14)
254#define DR6_BT (1 << 15)
255#define DR6_FIXED_1 0xffff0ff0
256
257#define DR7_GD (1 << 13)
258#define DR7_TYPE_SHIFT 16
259#define DR7_LEN_SHIFT 18
260#define DR7_FIXED_1 0x00000400
261#define DR7_GLOBAL_BP_MASK 0xaa
262#define DR7_LOCAL_BP_MASK 0x55
263#define DR7_MAX_BP 4
264#define DR7_TYPE_BP_INST 0x0
265#define DR7_TYPE_DATA_WR 0x1
266#define DR7_TYPE_IO_RW 0x2
267#define DR7_TYPE_DATA_RW 0x3
268
269#define PG_PRESENT_BIT 0
270#define PG_RW_BIT 1
271#define PG_USER_BIT 2
272#define PG_PWT_BIT 3
273#define PG_PCD_BIT 4
274#define PG_ACCESSED_BIT 5
275#define PG_DIRTY_BIT 6
276#define PG_PSE_BIT 7
277#define PG_GLOBAL_BIT 8
278#define PG_PSE_PAT_BIT 12
279#define PG_PKRU_BIT 59
280#define PG_NX_BIT 63
281
282#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
283#define PG_RW_MASK (1 << PG_RW_BIT)
284#define PG_USER_MASK (1 << PG_USER_BIT)
285#define PG_PWT_MASK (1 << PG_PWT_BIT)
286#define PG_PCD_MASK (1 << PG_PCD_BIT)
287#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
288#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
289#define PG_PSE_MASK (1 << PG_PSE_BIT)
290#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
291#define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
292#define PG_ADDRESS_MASK 0x000ffffffffff000LL
293#define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
294#define PG_HI_USER_MASK 0x7ff0000000000000LL
295#define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
296#define PG_NX_MASK (1ULL << PG_NX_BIT)
297
298#define PG_ERROR_W_BIT 1
299
300#define PG_ERROR_P_MASK 0x01
301#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
302#define PG_ERROR_U_MASK 0x04
303#define PG_ERROR_RSVD_MASK 0x08
304#define PG_ERROR_I_D_MASK 0x10
305#define PG_ERROR_PK_MASK 0x20
306
307#define MCG_CTL_P (1ULL<<8)
308#define MCG_SER_P (1ULL<<24)
309#define MCG_LMCE_P (1ULL<<27)
310
311#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
312#define MCE_BANKS_DEF 10
313
314#define MCG_CAP_BANKS_MASK 0xff
315
316#define MCG_STATUS_RIPV (1ULL<<0)
317#define MCG_STATUS_EIPV (1ULL<<1)
318#define MCG_STATUS_MCIP (1ULL<<2)
319#define MCG_STATUS_LMCE (1ULL<<3)
320
321#define MCG_EXT_CTL_LMCE_EN (1ULL<<0)
322
323#define MCI_STATUS_VAL (1ULL<<63)
324#define MCI_STATUS_OVER (1ULL<<62)
325#define MCI_STATUS_UC (1ULL<<61)
326#define MCI_STATUS_EN (1ULL<<60)
327#define MCI_STATUS_MISCV (1ULL<<59)
328#define MCI_STATUS_ADDRV (1ULL<<58)
329#define MCI_STATUS_PCC (1ULL<<57)
330#define MCI_STATUS_S (1ULL<<56)
331#define MCI_STATUS_AR (1ULL<<55)
332
333
334#define MCM_ADDR_SEGOFF 0
335#define MCM_ADDR_LINEAR 1
336#define MCM_ADDR_PHYS 2
337#define MCM_ADDR_MEM 3
338#define MCM_ADDR_GENERIC 7
339
340#define MSR_IA32_TSC 0x10
341#define MSR_IA32_APICBASE 0x1b
342#define MSR_IA32_APICBASE_BSP (1<<8)
343#define MSR_IA32_APICBASE_ENABLE (1<<11)
344#define MSR_IA32_APICBASE_EXTD (1 << 10)
345#define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
346#define MSR_IA32_FEATURE_CONTROL 0x0000003a
347#define MSR_TSC_ADJUST 0x0000003b
348#define MSR_IA32_SPEC_CTRL 0x48
349#define MSR_VIRT_SSBD 0xc001011f
350#define MSR_IA32_PRED_CMD 0x49
351#define MSR_IA32_UCODE_REV 0x8b
352#define MSR_IA32_CORE_CAPABILITY 0xcf
353
354#define MSR_IA32_ARCH_CAPABILITIES 0x10a
355#define ARCH_CAP_TSX_CTRL_MSR (1<<7)
356
357#define MSR_IA32_TSX_CTRL 0x122
358#define MSR_IA32_TSCDEADLINE 0x6e0
359
360#define FEATURE_CONTROL_LOCKED (1<<0)
361#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
362#define FEATURE_CONTROL_LMCE (1<<20)
363
364#define MSR_P6_PERFCTR0 0xc1
365
366#define MSR_IA32_SMBASE 0x9e
367#define MSR_SMI_COUNT 0x34
368#define MSR_MTRRcap 0xfe
369#define MSR_MTRRcap_VCNT 8
370#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
371#define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
372
373#define MSR_IA32_SYSENTER_CS 0x174
374#define MSR_IA32_SYSENTER_ESP 0x175
375#define MSR_IA32_SYSENTER_EIP 0x176
376
377#define MSR_MCG_CAP 0x179
378#define MSR_MCG_STATUS 0x17a
379#define MSR_MCG_CTL 0x17b
380#define MSR_MCG_EXT_CTL 0x4d0
381
382#define MSR_P6_EVNTSEL0 0x186
383
384#define MSR_IA32_PERF_STATUS 0x198
385
386#define MSR_IA32_MISC_ENABLE 0x1a0
387
388#define MSR_IA32_MISC_ENABLE_DEFAULT 1
389#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
390
391#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
392#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
393
394#define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
395
396#define MSR_MTRRfix64K_00000 0x250
397#define MSR_MTRRfix16K_80000 0x258
398#define MSR_MTRRfix16K_A0000 0x259
399#define MSR_MTRRfix4K_C0000 0x268
400#define MSR_MTRRfix4K_C8000 0x269
401#define MSR_MTRRfix4K_D0000 0x26a
402#define MSR_MTRRfix4K_D8000 0x26b
403#define MSR_MTRRfix4K_E0000 0x26c
404#define MSR_MTRRfix4K_E8000 0x26d
405#define MSR_MTRRfix4K_F0000 0x26e
406#define MSR_MTRRfix4K_F8000 0x26f
407
408#define MSR_PAT 0x277
409
410#define MSR_MTRRdefType 0x2ff
411
412#define MSR_CORE_PERF_FIXED_CTR0 0x309
413#define MSR_CORE_PERF_FIXED_CTR1 0x30a
414#define MSR_CORE_PERF_FIXED_CTR2 0x30b
415#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
416#define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
417#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
418#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
419
420#define MSR_MC0_CTL 0x400
421#define MSR_MC0_STATUS 0x401
422#define MSR_MC0_ADDR 0x402
423#define MSR_MC0_MISC 0x403
424
425#define MSR_IA32_RTIT_OUTPUT_BASE 0x560
426#define MSR_IA32_RTIT_OUTPUT_MASK 0x561
427#define MSR_IA32_RTIT_CTL 0x570
428#define MSR_IA32_RTIT_STATUS 0x571
429#define MSR_IA32_RTIT_CR3_MATCH 0x572
430#define MSR_IA32_RTIT_ADDR0_A 0x580
431#define MSR_IA32_RTIT_ADDR0_B 0x581
432#define MSR_IA32_RTIT_ADDR1_A 0x582
433#define MSR_IA32_RTIT_ADDR1_B 0x583
434#define MSR_IA32_RTIT_ADDR2_A 0x584
435#define MSR_IA32_RTIT_ADDR2_B 0x585
436#define MSR_IA32_RTIT_ADDR3_A 0x586
437#define MSR_IA32_RTIT_ADDR3_B 0x587
438#define MAX_RTIT_ADDRS 8
439
440#define MSR_EFER 0xc0000080
441
442#define MSR_EFER_SCE (1 << 0)
443#define MSR_EFER_LME (1 << 8)
444#define MSR_EFER_LMA (1 << 10)
445#define MSR_EFER_NXE (1 << 11)
446#define MSR_EFER_SVME (1 << 12)
447#define MSR_EFER_FFXSR (1 << 14)
448
449#define MSR_STAR 0xc0000081
450#define MSR_LSTAR 0xc0000082
451#define MSR_CSTAR 0xc0000083
452#define MSR_FMASK 0xc0000084
453#define MSR_FSBASE 0xc0000100
454#define MSR_GSBASE 0xc0000101
455#define MSR_KERNELGSBASE 0xc0000102
456#define MSR_TSC_AUX 0xc0000103
457
458#define MSR_VM_HSAVE_PA 0xc0010117
459
460#define MSR_IA32_BNDCFGS 0x00000d90
461#define MSR_IA32_XSS 0x00000da0
462#define MSR_IA32_UMWAIT_CONTROL 0xe1
463
464#define MSR_IA32_VMX_BASIC 0x00000480
465#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
466#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
467#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
468#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
469#define MSR_IA32_VMX_MISC 0x00000485
470#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
471#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
472#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
473#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
474#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
475#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
476#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
477#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
478#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
479#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
480#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
481#define MSR_IA32_VMX_VMFUNC 0x00000491
482
483#define XSTATE_FP_BIT 0
484#define XSTATE_SSE_BIT 1
485#define XSTATE_YMM_BIT 2
486#define XSTATE_BNDREGS_BIT 3
487#define XSTATE_BNDCSR_BIT 4
488#define XSTATE_OPMASK_BIT 5
489#define XSTATE_ZMM_Hi256_BIT 6
490#define XSTATE_Hi16_ZMM_BIT 7
491#define XSTATE_PKRU_BIT 9
492
493#define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
494#define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
495#define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
496#define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
497#define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
498#define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
499#define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
500#define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
501#define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
502
503
504typedef enum FeatureWord {
505 FEAT_1_EDX,
506 FEAT_1_ECX,
507 FEAT_7_0_EBX,
508 FEAT_7_0_ECX,
509 FEAT_7_0_EDX,
510 FEAT_7_1_EAX,
511 FEAT_8000_0001_EDX,
512 FEAT_8000_0001_ECX,
513 FEAT_8000_0007_EDX,
514 FEAT_8000_0008_EBX,
515 FEAT_C000_0001_EDX,
516 FEAT_KVM,
517 FEAT_KVM_HINTS,
518 FEAT_HYPERV_EAX,
519 FEAT_HYPERV_EBX,
520 FEAT_HYPERV_EDX,
521 FEAT_HV_RECOMM_EAX,
522 FEAT_HV_NESTED_EAX,
523 FEAT_SVM,
524 FEAT_XSAVE,
525 FEAT_6_EAX,
526 FEAT_XSAVE_COMP_LO,
527 FEAT_XSAVE_COMP_HI,
528 FEAT_ARCH_CAPABILITIES,
529 FEAT_CORE_CAPABILITY,
530 FEAT_VMX_PROCBASED_CTLS,
531 FEAT_VMX_SECONDARY_CTLS,
532 FEAT_VMX_PINBASED_CTLS,
533 FEAT_VMX_EXIT_CTLS,
534 FEAT_VMX_ENTRY_CTLS,
535 FEAT_VMX_MISC,
536 FEAT_VMX_EPT_VPID_CAPS,
537 FEAT_VMX_BASIC,
538 FEAT_VMX_VMFUNC,
539 FEATURE_WORDS,
540} FeatureWord;
541
542typedef uint64_t FeatureWordArray[FEATURE_WORDS];
543
544
545#define CPUID_FP87 (1U << 0)
546#define CPUID_VME (1U << 1)
547#define CPUID_DE (1U << 2)
548#define CPUID_PSE (1U << 3)
549#define CPUID_TSC (1U << 4)
550#define CPUID_MSR (1U << 5)
551#define CPUID_PAE (1U << 6)
552#define CPUID_MCE (1U << 7)
553#define CPUID_CX8 (1U << 8)
554#define CPUID_APIC (1U << 9)
555#define CPUID_SEP (1U << 11)
556#define CPUID_MTRR (1U << 12)
557#define CPUID_PGE (1U << 13)
558#define CPUID_MCA (1U << 14)
559#define CPUID_CMOV (1U << 15)
560#define CPUID_PAT (1U << 16)
561#define CPUID_PSE36 (1U << 17)
562#define CPUID_PN (1U << 18)
563#define CPUID_CLFLUSH (1U << 19)
564#define CPUID_DTS (1U << 21)
565#define CPUID_ACPI (1U << 22)
566#define CPUID_MMX (1U << 23)
567#define CPUID_FXSR (1U << 24)
568#define CPUID_SSE (1U << 25)
569#define CPUID_SSE2 (1U << 26)
570#define CPUID_SS (1U << 27)
571#define CPUID_HT (1U << 28)
572#define CPUID_TM (1U << 29)
573#define CPUID_IA64 (1U << 30)
574#define CPUID_PBE (1U << 31)
575
576#define CPUID_EXT_SSE3 (1U << 0)
577#define CPUID_EXT_PCLMULQDQ (1U << 1)
578#define CPUID_EXT_DTES64 (1U << 2)
579#define CPUID_EXT_MONITOR (1U << 3)
580#define CPUID_EXT_DSCPL (1U << 4)
581#define CPUID_EXT_VMX (1U << 5)
582#define CPUID_EXT_SMX (1U << 6)
583#define CPUID_EXT_EST (1U << 7)
584#define CPUID_EXT_TM2 (1U << 8)
585#define CPUID_EXT_SSSE3 (1U << 9)
586#define CPUID_EXT_CID (1U << 10)
587#define CPUID_EXT_FMA (1U << 12)
588#define CPUID_EXT_CX16 (1U << 13)
589#define CPUID_EXT_XTPR (1U << 14)
590#define CPUID_EXT_PDCM (1U << 15)
591#define CPUID_EXT_PCID (1U << 17)
592#define CPUID_EXT_DCA (1U << 18)
593#define CPUID_EXT_SSE41 (1U << 19)
594#define CPUID_EXT_SSE42 (1U << 20)
595#define CPUID_EXT_X2APIC (1U << 21)
596#define CPUID_EXT_MOVBE (1U << 22)
597#define CPUID_EXT_POPCNT (1U << 23)
598#define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
599#define CPUID_EXT_AES (1U << 25)
600#define CPUID_EXT_XSAVE (1U << 26)
601#define CPUID_EXT_OSXSAVE (1U << 27)
602#define CPUID_EXT_AVX (1U << 28)
603#define CPUID_EXT_F16C (1U << 29)
604#define CPUID_EXT_RDRAND (1U << 30)
605#define CPUID_EXT_HYPERVISOR (1U << 31)
606
607#define CPUID_EXT2_FPU (1U << 0)
608#define CPUID_EXT2_VME (1U << 1)
609#define CPUID_EXT2_DE (1U << 2)
610#define CPUID_EXT2_PSE (1U << 3)
611#define CPUID_EXT2_TSC (1U << 4)
612#define CPUID_EXT2_MSR (1U << 5)
613#define CPUID_EXT2_PAE (1U << 6)
614#define CPUID_EXT2_MCE (1U << 7)
615#define CPUID_EXT2_CX8 (1U << 8)
616#define CPUID_EXT2_APIC (1U << 9)
617#define CPUID_EXT2_SYSCALL (1U << 11)
618#define CPUID_EXT2_MTRR (1U << 12)
619#define CPUID_EXT2_PGE (1U << 13)
620#define CPUID_EXT2_MCA (1U << 14)
621#define CPUID_EXT2_CMOV (1U << 15)
622#define CPUID_EXT2_PAT (1U << 16)
623#define CPUID_EXT2_PSE36 (1U << 17)
624#define CPUID_EXT2_MP (1U << 19)
625#define CPUID_EXT2_NX (1U << 20)
626#define CPUID_EXT2_MMXEXT (1U << 22)
627#define CPUID_EXT2_MMX (1U << 23)
628#define CPUID_EXT2_FXSR (1U << 24)
629#define CPUID_EXT2_FFXSR (1U << 25)
630#define CPUID_EXT2_PDPE1GB (1U << 26)
631#define CPUID_EXT2_RDTSCP (1U << 27)
632#define CPUID_EXT2_LM (1U << 29)
633#define CPUID_EXT2_3DNOWEXT (1U << 30)
634#define CPUID_EXT2_3DNOW (1U << 31)
635
636
637#define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
638 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
639 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
640 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
641 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
642 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
643 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
644 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
645 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
646
647#define CPUID_EXT3_LAHF_LM (1U << 0)
648#define CPUID_EXT3_CMP_LEG (1U << 1)
649#define CPUID_EXT3_SVM (1U << 2)
650#define CPUID_EXT3_EXTAPIC (1U << 3)
651#define CPUID_EXT3_CR8LEG (1U << 4)
652#define CPUID_EXT3_ABM (1U << 5)
653#define CPUID_EXT3_SSE4A (1U << 6)
654#define CPUID_EXT3_MISALIGNSSE (1U << 7)
655#define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
656#define CPUID_EXT3_OSVW (1U << 9)
657#define CPUID_EXT3_IBS (1U << 10)
658#define CPUID_EXT3_XOP (1U << 11)
659#define CPUID_EXT3_SKINIT (1U << 12)
660#define CPUID_EXT3_WDT (1U << 13)
661#define CPUID_EXT3_LWP (1U << 15)
662#define CPUID_EXT3_FMA4 (1U << 16)
663#define CPUID_EXT3_TCE (1U << 17)
664#define CPUID_EXT3_NODEID (1U << 19)
665#define CPUID_EXT3_TBM (1U << 21)
666#define CPUID_EXT3_TOPOEXT (1U << 22)
667#define CPUID_EXT3_PERFCORE (1U << 23)
668#define CPUID_EXT3_PERFNB (1U << 24)
669
670#define CPUID_SVM_NPT (1U << 0)
671#define CPUID_SVM_LBRV (1U << 1)
672#define CPUID_SVM_SVMLOCK (1U << 2)
673#define CPUID_SVM_NRIPSAVE (1U << 3)
674#define CPUID_SVM_TSCSCALE (1U << 4)
675#define CPUID_SVM_VMCBCLEAN (1U << 5)
676#define CPUID_SVM_FLUSHASID (1U << 6)
677#define CPUID_SVM_DECODEASSIST (1U << 7)
678#define CPUID_SVM_PAUSEFILTER (1U << 10)
679#define CPUID_SVM_PFTHRESHOLD (1U << 12)
680
681
682#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
683
684#define CPUID_7_0_EBX_BMI1 (1U << 3)
685
686#define CPUID_7_0_EBX_HLE (1U << 4)
687
688#define CPUID_7_0_EBX_AVX2 (1U << 5)
689
690#define CPUID_7_0_EBX_SMEP (1U << 7)
691
692#define CPUID_7_0_EBX_BMI2 (1U << 8)
693
694#define CPUID_7_0_EBX_ERMS (1U << 9)
695
696#define CPUID_7_0_EBX_INVPCID (1U << 10)
697
698#define CPUID_7_0_EBX_RTM (1U << 11)
699
700#define CPUID_7_0_EBX_MPX (1U << 14)
701
702#define CPUID_7_0_EBX_AVX512F (1U << 16)
703
704#define CPUID_7_0_EBX_AVX512DQ (1U << 17)
705
706#define CPUID_7_0_EBX_RDSEED (1U << 18)
707
708#define CPUID_7_0_EBX_ADX (1U << 19)
709
710#define CPUID_7_0_EBX_SMAP (1U << 20)
711
712#define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
713
714#define CPUID_7_0_EBX_PCOMMIT (1U << 22)
715
716#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
717
718#define CPUID_7_0_EBX_CLWB (1U << 24)
719
720#define CPUID_7_0_EBX_INTEL_PT (1U << 25)
721
722#define CPUID_7_0_EBX_AVX512PF (1U << 26)
723
724#define CPUID_7_0_EBX_AVX512ER (1U << 27)
725
726#define CPUID_7_0_EBX_AVX512CD (1U << 28)
727
728#define CPUID_7_0_EBX_SHA_NI (1U << 29)
729
730#define CPUID_7_0_EBX_AVX512BW (1U << 30)
731
732#define CPUID_7_0_EBX_AVX512VL (1U << 31)
733
734
735#define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
736
737#define CPUID_7_0_ECX_UMIP (1U << 2)
738
739#define CPUID_7_0_ECX_PKU (1U << 3)
740
741#define CPUID_7_0_ECX_OSPKE (1U << 4)
742
743#define CPUID_7_0_ECX_WAITPKG (1U << 5)
744
745#define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6)
746
747#define CPUID_7_0_ECX_GFNI (1U << 8)
748
749#define CPUID_7_0_ECX_VAES (1U << 9)
750
751#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
752
753#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
754
755#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
756
757#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
758
759#define CPUID_7_0_ECX_LA57 (1U << 16)
760
761#define CPUID_7_0_ECX_RDPID (1U << 22)
762
763#define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
764
765#define CPUID_7_0_ECX_MOVDIRI (1U << 27)
766
767#define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
768
769
770#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
771
772#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
773
774#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
775
776#define CPUID_7_0_EDX_STIBP (1U << 27)
777
778#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
779
780#define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
781
782#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
783
784
785#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
786
787
788#define CPUID_8000_0008_EBX_CLZERO (1U << 0)
789
790#define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2)
791
792#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
793
794#define CPUID_8000_0008_EBX_IBPB (1U << 12)
795
796#define CPUID_8000_0008_EBX_STIBP (1U << 15)
797
798#define CPUID_XSAVE_XSAVEOPT (1U << 0)
799#define CPUID_XSAVE_XSAVEC (1U << 1)
800#define CPUID_XSAVE_XGETBV1 (1U << 2)
801#define CPUID_XSAVE_XSAVES (1U << 3)
802
803#define CPUID_6_EAX_ARAT (1U << 2)
804
805
806#define CPUID_APM_INVTSC (1U << 8)
807
808#define CPUID_VENDOR_SZ 12
809
810#define CPUID_VENDOR_INTEL_1 0x756e6547
811#define CPUID_VENDOR_INTEL_2 0x49656e69
812#define CPUID_VENDOR_INTEL_3 0x6c65746e
813#define CPUID_VENDOR_INTEL "GenuineIntel"
814
815#define CPUID_VENDOR_AMD_1 0x68747541
816#define CPUID_VENDOR_AMD_2 0x69746e65
817#define CPUID_VENDOR_AMD_3 0x444d4163
818#define CPUID_VENDOR_AMD "AuthenticAMD"
819
820#define CPUID_VENDOR_VIA "CentaurHauls"
821
822#define CPUID_VENDOR_HYGON "HygonGenuine"
823
824#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
825 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
826 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
827#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
828 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
829 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
830
831#define CPUID_MWAIT_IBE (1U << 1)
832#define CPUID_MWAIT_EMX (1U << 0)
833
834
835#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
836#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
837#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
838#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
839
840
841#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
842#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
843#define MSR_ARCH_CAP_RSBA (1U << 2)
844#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
845#define MSR_ARCH_CAP_SSB_NO (1U << 4)
846#define MSR_ARCH_CAP_MDS_NO (1U << 5)
847#define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
848#define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
849#define MSR_ARCH_CAP_TAA_NO (1U << 8)
850
851#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
852
853
854#define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull
855#define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32)
856#define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32)
857#define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49)
858#define MSR_VMX_BASIC_INS_OUTS (1ULL << 54)
859#define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55)
860
861#define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full
862#define MSR_VMX_MISC_STORE_LMA (1ULL << 5)
863#define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6)
864#define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7)
865#define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8)
866#define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull
867#define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29)
868#define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30)
869
870#define MSR_VMX_EPT_EXECONLY (1ULL << 0)
871#define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6)
872#define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7)
873#define MSR_VMX_EPT_UC (1ULL << 8)
874#define MSR_VMX_EPT_WB (1ULL << 14)
875#define MSR_VMX_EPT_2MB (1ULL << 16)
876#define MSR_VMX_EPT_1GB (1ULL << 17)
877#define MSR_VMX_EPT_INVEPT (1ULL << 20)
878#define MSR_VMX_EPT_AD_BITS (1ULL << 21)
879#define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22)
880#define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25)
881#define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26)
882#define MSR_VMX_EPT_INVVPID (1ULL << 32)
883#define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40)
884#define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41)
885#define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42)
886#define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
887
888#define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0)
889
890
891
892#define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
893#define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008
894#define VMX_CPU_BASED_HLT_EXITING 0x00000080
895#define VMX_CPU_BASED_INVLPG_EXITING 0x00000200
896#define VMX_CPU_BASED_MWAIT_EXITING 0x00000400
897#define VMX_CPU_BASED_RDPMC_EXITING 0x00000800
898#define VMX_CPU_BASED_RDTSC_EXITING 0x00001000
899#define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000
900#define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000
901#define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000
902#define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000
903#define VMX_CPU_BASED_TPR_SHADOW 0x00200000
904#define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
905#define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000
906#define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000
907#define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000
908#define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
909#define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000
910#define VMX_CPU_BASED_MONITOR_EXITING 0x20000000
911#define VMX_CPU_BASED_PAUSE_EXITING 0x40000000
912#define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
913
914#define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
915#define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002
916#define VMX_SECONDARY_EXEC_DESC 0x00000004
917#define VMX_SECONDARY_EXEC_RDTSCP 0x00000008
918#define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
919#define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020
920#define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040
921#define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
922#define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
923#define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
924#define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
925#define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800
926#define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
927#define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
928#define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000
929#define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000
930#define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000
931#define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000
932#define VMX_SECONDARY_EXEC_XSAVES 0x00100000
933
934#define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001
935#define VMX_PIN_BASED_NMI_EXITING 0x00000008
936#define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020
937#define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
938#define VMX_PIN_BASED_POSTED_INTR 0x00000080
939
940#define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
941#define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
942#define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
943#define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
944#define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000
945#define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000
946#define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000
947#define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000
948#define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
949#define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000
950#define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000
951#define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
952
953#define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
954#define VMX_VM_ENTRY_IA32E_MODE 0x00000200
955#define VMX_VM_ENTRY_SMM 0x00000400
956#define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
957#define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
958#define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000
959#define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000
960#define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000
961#define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000
962#define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
963
964
965#define HYPERV_FEAT_RELAXED 0
966#define HYPERV_FEAT_VAPIC 1
967#define HYPERV_FEAT_TIME 2
968#define HYPERV_FEAT_CRASH 3
969#define HYPERV_FEAT_RESET 4
970#define HYPERV_FEAT_VPINDEX 5
971#define HYPERV_FEAT_RUNTIME 6
972#define HYPERV_FEAT_SYNIC 7
973#define HYPERV_FEAT_STIMER 8
974#define HYPERV_FEAT_FREQUENCIES 9
975#define HYPERV_FEAT_REENLIGHTENMENT 10
976#define HYPERV_FEAT_TLBFLUSH 11
977#define HYPERV_FEAT_EVMCS 12
978#define HYPERV_FEAT_IPI 13
979#define HYPERV_FEAT_STIMER_DIRECT 14
980
981#ifndef HYPERV_SPINLOCK_NEVER_RETRY
982#define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
983#endif
984
985#define EXCP00_DIVZ 0
986#define EXCP01_DB 1
987#define EXCP02_NMI 2
988#define EXCP03_INT3 3
989#define EXCP04_INTO 4
990#define EXCP05_BOUND 5
991#define EXCP06_ILLOP 6
992#define EXCP07_PREX 7
993#define EXCP08_DBLE 8
994#define EXCP09_XERR 9
995#define EXCP0A_TSS 10
996#define EXCP0B_NOSEG 11
997#define EXCP0C_STACK 12
998#define EXCP0D_GPF 13
999#define EXCP0E_PAGE 14
1000#define EXCP10_COPR 16
1001#define EXCP11_ALGN 17
1002#define EXCP12_MCHK 18
1003
1004#define EXCP_VMEXIT 0x100
1005#define EXCP_SYSCALL 0x101
1006#define EXCP_VSYSCALL 0x102
1007
1008
1009#define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
1010#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
1011#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
1012#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
1013#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
1014#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
1015#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
1016
1017
1018#define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
1019
1020
1021
1022
1023
1024
1025
1026
1027typedef enum {
1028 CC_OP_DYNAMIC,
1029 CC_OP_EFLAGS,
1030
1031 CC_OP_MULB,
1032 CC_OP_MULW,
1033 CC_OP_MULL,
1034 CC_OP_MULQ,
1035
1036 CC_OP_ADDB,
1037 CC_OP_ADDW,
1038 CC_OP_ADDL,
1039 CC_OP_ADDQ,
1040
1041 CC_OP_ADCB,
1042 CC_OP_ADCW,
1043 CC_OP_ADCL,
1044 CC_OP_ADCQ,
1045
1046 CC_OP_SUBB,
1047 CC_OP_SUBW,
1048 CC_OP_SUBL,
1049 CC_OP_SUBQ,
1050
1051 CC_OP_SBBB,
1052 CC_OP_SBBW,
1053 CC_OP_SBBL,
1054 CC_OP_SBBQ,
1055
1056 CC_OP_LOGICB,
1057 CC_OP_LOGICW,
1058 CC_OP_LOGICL,
1059 CC_OP_LOGICQ,
1060
1061 CC_OP_INCB,
1062 CC_OP_INCW,
1063 CC_OP_INCL,
1064 CC_OP_INCQ,
1065
1066 CC_OP_DECB,
1067 CC_OP_DECW,
1068 CC_OP_DECL,
1069 CC_OP_DECQ,
1070
1071 CC_OP_SHLB,
1072 CC_OP_SHLW,
1073 CC_OP_SHLL,
1074 CC_OP_SHLQ,
1075
1076 CC_OP_SARB,
1077 CC_OP_SARW,
1078 CC_OP_SARL,
1079 CC_OP_SARQ,
1080
1081 CC_OP_BMILGB,
1082 CC_OP_BMILGW,
1083 CC_OP_BMILGL,
1084 CC_OP_BMILGQ,
1085
1086 CC_OP_ADCX,
1087 CC_OP_ADOX,
1088 CC_OP_ADCOX,
1089
1090 CC_OP_CLR,
1091 CC_OP_POPCNT,
1092
1093 CC_OP_NB,
1094} CCOp;
1095
1096typedef struct SegmentCache {
1097 uint32_t selector;
1098 target_ulong base;
1099 uint32_t limit;
1100 uint32_t flags;
1101} SegmentCache;
1102
1103#define MMREG_UNION(n, bits) \
1104 union n { \
1105 uint8_t _b_##n[(bits)/8]; \
1106 uint16_t _w_##n[(bits)/16]; \
1107 uint32_t _l_##n[(bits)/32]; \
1108 uint64_t _q_##n[(bits)/64]; \
1109 float32 _s_##n[(bits)/32]; \
1110 float64 _d_##n[(bits)/64]; \
1111 }
1112
1113typedef union {
1114 uint8_t _b[16];
1115 uint16_t _w[8];
1116 uint32_t _l[4];
1117 uint64_t _q[2];
1118} XMMReg;
1119
1120typedef union {
1121 uint8_t _b[32];
1122 uint16_t _w[16];
1123 uint32_t _l[8];
1124 uint64_t _q[4];
1125} YMMReg;
1126
1127typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
1128typedef MMREG_UNION(MMXReg, 64) MMXReg;
1129
1130typedef struct BNDReg {
1131 uint64_t lb;
1132 uint64_t ub;
1133} BNDReg;
1134
1135typedef struct BNDCSReg {
1136 uint64_t cfgu;
1137 uint64_t sts;
1138} BNDCSReg;
1139
1140#define BNDCFG_ENABLE 1ULL
1141#define BNDCFG_BNDPRESERVE 2ULL
1142#define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
1143
1144#ifdef HOST_WORDS_BIGENDIAN
1145#define ZMM_B(n) _b_ZMMReg[63 - (n)]
1146#define ZMM_W(n) _w_ZMMReg[31 - (n)]
1147#define ZMM_L(n) _l_ZMMReg[15 - (n)]
1148#define ZMM_S(n) _s_ZMMReg[15 - (n)]
1149#define ZMM_Q(n) _q_ZMMReg[7 - (n)]
1150#define ZMM_D(n) _d_ZMMReg[7 - (n)]
1151
1152#define MMX_B(n) _b_MMXReg[7 - (n)]
1153#define MMX_W(n) _w_MMXReg[3 - (n)]
1154#define MMX_L(n) _l_MMXReg[1 - (n)]
1155#define MMX_S(n) _s_MMXReg[1 - (n)]
1156#else
1157#define ZMM_B(n) _b_ZMMReg[n]
1158#define ZMM_W(n) _w_ZMMReg[n]
1159#define ZMM_L(n) _l_ZMMReg[n]
1160#define ZMM_S(n) _s_ZMMReg[n]
1161#define ZMM_Q(n) _q_ZMMReg[n]
1162#define ZMM_D(n) _d_ZMMReg[n]
1163
1164#define MMX_B(n) _b_MMXReg[n]
1165#define MMX_W(n) _w_MMXReg[n]
1166#define MMX_L(n) _l_MMXReg[n]
1167#define MMX_S(n) _s_MMXReg[n]
1168#endif
1169#define MMX_Q(n) _q_MMXReg[n]
1170
1171typedef union {
1172 floatx80 d __attribute__((aligned(16)));
1173 MMXReg mmx;
1174} FPReg;
1175
1176typedef struct {
1177 uint64_t base;
1178 uint64_t mask;
1179} MTRRVar;
1180
1181#define CPU_NB_REGS64 16
1182#define CPU_NB_REGS32 8
1183
1184#ifdef TARGET_X86_64
1185#define CPU_NB_REGS CPU_NB_REGS64
1186#else
1187#define CPU_NB_REGS CPU_NB_REGS32
1188#endif
1189
1190#define MAX_FIXED_COUNTERS 3
1191#define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
1192
1193#define TARGET_INSN_START_EXTRA_WORDS 1
1194
1195#define NB_OPMASK_REGS 8
1196
1197
1198
1199
1200#define UNASSIGNED_APIC_ID 0xFFFFFFFF
1201
1202typedef union X86LegacyXSaveArea {
1203 struct {
1204 uint16_t fcw;
1205 uint16_t fsw;
1206 uint8_t ftw;
1207 uint8_t reserved;
1208 uint16_t fpop;
1209 uint64_t fpip;
1210 uint64_t fpdp;
1211 uint32_t mxcsr;
1212 uint32_t mxcsr_mask;
1213 FPReg fpregs[8];
1214 uint8_t xmm_regs[16][16];
1215 };
1216 uint8_t data[512];
1217} X86LegacyXSaveArea;
1218
1219typedef struct X86XSaveHeader {
1220 uint64_t xstate_bv;
1221 uint64_t xcomp_bv;
1222 uint64_t reserve0;
1223 uint8_t reserved[40];
1224} X86XSaveHeader;
1225
1226
1227typedef struct XSaveAVX {
1228 uint8_t ymmh[16][16];
1229} XSaveAVX;
1230
1231
1232typedef struct XSaveBNDREG {
1233 BNDReg bnd_regs[4];
1234} XSaveBNDREG;
1235
1236
1237typedef union XSaveBNDCSR {
1238 BNDCSReg bndcsr;
1239 uint8_t data[64];
1240} XSaveBNDCSR;
1241
1242
1243typedef struct XSaveOpmask {
1244 uint64_t opmask_regs[NB_OPMASK_REGS];
1245} XSaveOpmask;
1246
1247
1248typedef struct XSaveZMM_Hi256 {
1249 uint8_t zmm_hi256[16][32];
1250} XSaveZMM_Hi256;
1251
1252
1253typedef struct XSaveHi16_ZMM {
1254 uint8_t hi16_zmm[16][64];
1255} XSaveHi16_ZMM;
1256
1257
1258typedef struct XSavePKRU {
1259 uint32_t pkru;
1260 uint32_t padding;
1261} XSavePKRU;
1262
1263typedef struct X86XSaveArea {
1264 X86LegacyXSaveArea legacy;
1265 X86XSaveHeader header;
1266
1267
1268
1269
1270 XSaveAVX avx_state;
1271 uint8_t padding[960 - 576 - sizeof(XSaveAVX)];
1272
1273 XSaveBNDREG bndreg_state;
1274 XSaveBNDCSR bndcsr_state;
1275
1276 XSaveOpmask opmask_state;
1277 XSaveZMM_Hi256 zmm_hi256_state;
1278 XSaveHi16_ZMM hi16_zmm_state;
1279
1280 XSavePKRU pkru_state;
1281} X86XSaveArea;
1282
1283QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240);
1284QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1285QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0);
1286QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1287QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400);
1288QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1289QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440);
1290QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1291QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480);
1292QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1293QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680);
1294QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1295QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80);
1296QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1297
1298typedef enum TPRAccess {
1299 TPR_ACCESS_READ,
1300 TPR_ACCESS_WRITE,
1301} TPRAccess;
1302
1303
1304
1305enum CacheType {
1306 DATA_CACHE,
1307 INSTRUCTION_CACHE,
1308 UNIFIED_CACHE
1309};
1310
1311typedef struct CPUCacheInfo {
1312 enum CacheType type;
1313 uint8_t level;
1314
1315 uint32_t size;
1316
1317 uint16_t line_size;
1318
1319
1320
1321
1322 uint8_t associativity;
1323
1324 uint8_t partitions;
1325
1326 uint32_t sets;
1327
1328
1329
1330
1331
1332 uint8_t lines_per_tag;
1333
1334
1335 bool self_init;
1336
1337
1338
1339
1340
1341 bool no_invd_sharing;
1342
1343
1344
1345
1346 bool inclusive;
1347
1348
1349
1350
1351 bool complex_indexing;
1352} CPUCacheInfo;
1353
1354
1355typedef struct CPUCaches {
1356 CPUCacheInfo *l1d_cache;
1357 CPUCacheInfo *l1i_cache;
1358 CPUCacheInfo *l2_cache;
1359 CPUCacheInfo *l3_cache;
1360} CPUCaches;
1361
1362typedef struct CPUX86State {
1363
1364 target_ulong regs[CPU_NB_REGS];
1365 target_ulong eip;
1366 target_ulong eflags;
1367
1368
1369
1370
1371 target_ulong cc_dst;
1372 target_ulong cc_src;
1373 target_ulong cc_src2;
1374 uint32_t cc_op;
1375 int32_t df;
1376 uint32_t hflags;
1377
1378 uint32_t hflags2;
1379
1380
1381 SegmentCache segs[6];
1382 SegmentCache ldt;
1383 SegmentCache tr;
1384 SegmentCache gdt;
1385 SegmentCache idt;
1386
1387 target_ulong cr[5];
1388 int32_t a20_mask;
1389
1390 BNDReg bnd_regs[4];
1391 BNDCSReg bndcs_regs;
1392 uint64_t msr_bndcfgs;
1393 uint64_t efer;
1394
1395
1396 struct {} start_init_save;
1397
1398
1399 unsigned int fpstt;
1400 uint16_t fpus;
1401 uint16_t fpuc;
1402 uint8_t fptags[8];
1403 FPReg fpregs[8];
1404
1405 uint16_t fpop;
1406 uint64_t fpip;
1407 uint64_t fpdp;
1408
1409
1410 float_status fp_status;
1411 floatx80 ft0;
1412
1413 float_status mmx_status;
1414 float_status sse_status;
1415 uint32_t mxcsr;
1416 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
1417 ZMMReg xmm_t0;
1418 MMXReg mmx_t0;
1419
1420 XMMReg ymmh_regs[CPU_NB_REGS];
1421
1422 uint64_t opmask_regs[NB_OPMASK_REGS];
1423 YMMReg zmmh_regs[CPU_NB_REGS];
1424 ZMMReg hi16_zmm_regs[CPU_NB_REGS];
1425
1426
1427 uint32_t sysenter_cs;
1428 target_ulong sysenter_esp;
1429 target_ulong sysenter_eip;
1430 uint64_t star;
1431
1432 uint64_t vm_hsave;
1433
1434#ifdef TARGET_X86_64
1435 target_ulong lstar;
1436 target_ulong cstar;
1437 target_ulong fmask;
1438 target_ulong kernelgsbase;
1439#endif
1440
1441 uint64_t tsc;
1442 uint64_t tsc_adjust;
1443 uint64_t tsc_deadline;
1444 uint64_t tsc_aux;
1445
1446 uint64_t xcr0;
1447
1448 uint64_t mcg_status;
1449 uint64_t msr_ia32_misc_enable;
1450 uint64_t msr_ia32_feature_control;
1451
1452 uint64_t msr_fixed_ctr_ctrl;
1453 uint64_t msr_global_ctrl;
1454 uint64_t msr_global_status;
1455 uint64_t msr_global_ovf_ctrl;
1456 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1457 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1458 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1459
1460 uint64_t pat;
1461 uint32_t smbase;
1462 uint64_t msr_smi_count;
1463
1464 uint32_t pkru;
1465 uint32_t tsx_ctrl;
1466
1467 uint64_t spec_ctrl;
1468 uint64_t virt_ssbd;
1469
1470
1471 struct {} end_init_save;
1472
1473 uint64_t system_time_msr;
1474 uint64_t wall_clock_msr;
1475 uint64_t steal_time_msr;
1476 uint64_t async_pf_en_msr;
1477 uint64_t pv_eoi_en_msr;
1478 uint64_t poll_control_msr;
1479
1480
1481 uint64_t msr_hv_hypercall;
1482 uint64_t msr_hv_guest_os_id;
1483 uint64_t msr_hv_tsc;
1484
1485
1486 uint64_t msr_hv_vapic;
1487 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1488 uint64_t msr_hv_runtime;
1489 uint64_t msr_hv_synic_control;
1490 uint64_t msr_hv_synic_evt_page;
1491 uint64_t msr_hv_synic_msg_page;
1492 uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1493 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1494 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1495 uint64_t msr_hv_reenlightenment_control;
1496 uint64_t msr_hv_tsc_emulation_control;
1497 uint64_t msr_hv_tsc_emulation_status;
1498
1499 uint64_t msr_rtit_ctrl;
1500 uint64_t msr_rtit_status;
1501 uint64_t msr_rtit_output_base;
1502 uint64_t msr_rtit_output_mask;
1503 uint64_t msr_rtit_cr3_match;
1504 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1505
1506
1507 int error_code;
1508 int exception_is_int;
1509 target_ulong exception_next_eip;
1510 target_ulong dr[8];
1511 union {
1512 struct CPUBreakpoint *cpu_breakpoint[4];
1513 struct CPUWatchpoint *cpu_watchpoint[4];
1514 };
1515 int old_exception;
1516
1517 uint64_t vm_vmcb;
1518 uint64_t tsc_offset;
1519 uint64_t intercept;
1520 uint16_t intercept_cr_read;
1521 uint16_t intercept_cr_write;
1522 uint16_t intercept_dr_read;
1523 uint16_t intercept_dr_write;
1524 uint32_t intercept_exceptions;
1525 uint64_t nested_cr3;
1526 uint32_t nested_pg_mode;
1527 uint8_t v_tpr;
1528
1529
1530 uint8_t nmi_injected;
1531 uint8_t nmi_pending;
1532
1533 uintptr_t retaddr;
1534
1535
1536 struct {} end_reset_fields;
1537
1538
1539
1540
1541
1542 uint32_t cpuid_level_func7;
1543
1544 uint32_t cpuid_min_level_func7;
1545
1546 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1547
1548 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1549
1550 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1551 uint32_t cpuid_vendor1;
1552 uint32_t cpuid_vendor2;
1553 uint32_t cpuid_vendor3;
1554 uint32_t cpuid_version;
1555 FeatureWordArray features;
1556
1557 FeatureWordArray user_features;
1558 uint32_t cpuid_model[12];
1559
1560
1561
1562
1563 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1564
1565
1566 uint64_t mtrr_fixed[11];
1567 uint64_t mtrr_deftype;
1568 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1569
1570
1571 uint32_t mp_state;
1572 int32_t exception_nr;
1573 int32_t interrupt_injected;
1574 uint8_t soft_interrupt;
1575 uint8_t exception_pending;
1576 uint8_t exception_injected;
1577 uint8_t has_error_code;
1578 uint8_t exception_has_payload;
1579 uint64_t exception_payload;
1580 uint32_t ins_len;
1581 uint32_t sipi_vector;
1582 bool tsc_valid;
1583 int64_t tsc_khz;
1584 int64_t user_tsc_khz;
1585#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1586 void *xsave_buf;
1587#endif
1588#if defined(CONFIG_KVM)
1589 struct kvm_nested_state *nested_state;
1590#endif
1591#if defined(CONFIG_HVF)
1592 HVFX86EmulatorState *hvf_emul;
1593#endif
1594
1595 uint64_t mcg_cap;
1596 uint64_t mcg_ctl;
1597 uint64_t mcg_ext_ctl;
1598 uint64_t mce_banks[MCE_BANKS_DEF*4];
1599 uint64_t xstate_bv;
1600
1601
1602 uint16_t fpus_vmstate;
1603 uint16_t fptag_vmstate;
1604 uint16_t fpregs_format_vmstate;
1605
1606 uint64_t xss;
1607 uint32_t umwait;
1608
1609 TPRAccess tpr_access_type;
1610
1611 unsigned nr_dies;
1612 unsigned nr_nodes;
1613 unsigned pkg_offset;
1614} CPUX86State;
1615
1616struct kvm_msrs;
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627struct X86CPU {
1628
1629 CPUState parent_obj;
1630
1631
1632 CPUNegativeOffsetState neg;
1633 CPUX86State env;
1634
1635 uint64_t ucode_rev;
1636
1637 uint32_t hyperv_spinlock_attempts;
1638 char *hyperv_vendor_id;
1639 bool hyperv_synic_kvm_only;
1640 uint64_t hyperv_features;
1641 bool hyperv_passthrough;
1642 OnOffAuto hyperv_no_nonarch_cs;
1643
1644 bool check_cpuid;
1645 bool enforce_cpuid;
1646
1647
1648
1649
1650
1651 bool force_features;
1652 bool expose_kvm;
1653 bool expose_tcg;
1654 bool migratable;
1655 bool migrate_smi_count;
1656 bool max_features;
1657 uint32_t apic_id;
1658
1659
1660
1661 bool vmware_cpuid_freq;
1662
1663
1664 bool cache_info_passthrough;
1665
1666
1667
1668 struct {
1669 uint32_t eax;
1670 uint32_t ebx;
1671 uint32_t ecx;
1672 uint32_t edx;
1673 } mwait;
1674
1675
1676 FeatureWordArray filtered_features;
1677
1678
1679
1680
1681
1682
1683 bool enable_pmu;
1684
1685
1686
1687
1688
1689 bool enable_lmce;
1690
1691
1692
1693
1694
1695 bool enable_l3_cache;
1696
1697
1698
1699
1700 bool legacy_cache;
1701
1702
1703 bool enable_cpuid_0xb;
1704
1705
1706 bool full_cpuid_auto_level;
1707
1708
1709 bool intel_pt_auto_level;
1710
1711
1712 bool fill_mtrr_mask;
1713
1714
1715 bool host_phys_bits;
1716
1717
1718 uint8_t host_phys_bits_limit;
1719
1720
1721 bool kvm_no_smi_migration;
1722
1723
1724 uint32_t phys_bits;
1725
1726
1727
1728 struct DeviceState *apic_state;
1729 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
1730 Notifier machine_done;
1731
1732 struct kvm_msrs *kvm_msr_buf;
1733
1734 int32_t node_id;
1735 int32_t socket_id;
1736 int32_t die_id;
1737 int32_t core_id;
1738 int32_t thread_id;
1739
1740 int32_t hv_max_vps;
1741};
1742
1743
1744#ifndef CONFIG_USER_ONLY
1745extern VMStateDescription vmstate_x86_cpu;
1746#endif
1747
1748
1749
1750
1751
1752void x86_cpu_do_interrupt(CPUState *cpu);
1753bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
1754int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
1755
1756int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
1757 int cpuid, void *opaque);
1758int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
1759 int cpuid, void *opaque);
1760int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1761 void *opaque);
1762int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1763 void *opaque);
1764
1765void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
1766 Error **errp);
1767
1768void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
1769
1770hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1771 MemTxAttrs *attrs);
1772
1773int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1774int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1775
1776void x86_cpu_exec_enter(CPUState *cpu);
1777void x86_cpu_exec_exit(CPUState *cpu);
1778
1779void x86_cpu_list(void);
1780int cpu_x86_support_mca_broadcast(CPUX86State *env);
1781
1782int cpu_get_pic_interrupt(CPUX86State *s);
1783
1784void x86_register_ferr_irq(qemu_irq irq);
1785void cpu_set_ignne(void);
1786
1787void cpu_sync_bndcs_hflags(CPUX86State *env);
1788
1789
1790
1791static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1792 int seg_reg, unsigned int selector,
1793 target_ulong base,
1794 unsigned int limit,
1795 unsigned int flags)
1796{
1797 SegmentCache *sc;
1798 unsigned int new_hflags;
1799
1800 sc = &env->segs[seg_reg];
1801 sc->selector = selector;
1802 sc->base = base;
1803 sc->limit = limit;
1804 sc->flags = flags;
1805
1806
1807 {
1808 if (seg_reg == R_CS) {
1809#ifdef TARGET_X86_64
1810 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1811
1812 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1813 env->hflags &= ~(HF_ADDSEG_MASK);
1814 } else
1815#endif
1816 {
1817
1818 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1819 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1820 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1821 new_hflags;
1822 }
1823 }
1824 if (seg_reg == R_SS) {
1825 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1826#if HF_CPL_MASK != 3
1827#error HF_CPL_MASK is hardcoded
1828#endif
1829 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1830
1831 cpu_sync_bndcs_hflags(env);
1832 }
1833 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1834 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1835 if (env->hflags & HF_CS64_MASK) {
1836
1837 } else if (!(env->cr[0] & CR0_PE_MASK) ||
1838 (env->eflags & VM_MASK) ||
1839 !(env->hflags & HF_CS32_MASK)) {
1840
1841
1842
1843
1844
1845 new_hflags |= HF_ADDSEG_MASK;
1846 } else {
1847 new_hflags |= ((env->segs[R_DS].base |
1848 env->segs[R_ES].base |
1849 env->segs[R_SS].base) != 0) <<
1850 HF_ADDSEG_SHIFT;
1851 }
1852 env->hflags = (env->hflags &
1853 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1854 }
1855}
1856
1857static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1858 uint8_t sipi_vector)
1859{
1860 CPUState *cs = CPU(cpu);
1861 CPUX86State *env = &cpu->env;
1862
1863 env->eip = 0;
1864 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1865 sipi_vector << 12,
1866 env->segs[R_CS].limit,
1867 env->segs[R_CS].flags);
1868 cs->halted = 0;
1869}
1870
1871int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1872 target_ulong *base, unsigned int *limit,
1873 unsigned int *flags);
1874
1875
1876
1877
1878
1879
1880
1881void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1882void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1883void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1884void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);
1885void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);
1886
1887
1888
1889
1890int cpu_x86_signal_handler(int host_signum, void *pinfo,
1891 void *puc);
1892
1893
1894void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1895 uint32_t *eax, uint32_t *ebx,
1896 uint32_t *ecx, uint32_t *edx);
1897void cpu_clear_apic_feature(CPUX86State *env);
1898void host_cpuid(uint32_t function, uint32_t count,
1899 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1900void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
1901bool cpu_x86_use_epyc_apic_id_encoding(const char *cpu_type);
1902
1903
1904bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
1905 MMUAccessType access_type, int mmu_idx,
1906 bool probe, uintptr_t retaddr);
1907void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1908
1909#ifndef CONFIG_USER_ONLY
1910static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
1911{
1912 return !!attrs.secure;
1913}
1914
1915static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
1916{
1917 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
1918}
1919
1920uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
1921uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
1922uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
1923uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
1924void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
1925void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
1926void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
1927void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
1928void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
1929#endif
1930
1931void breakpoint_handler(CPUState *cs);
1932
1933
1934void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1935void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1936void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1937void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
1938
1939
1940uint64_t cpu_get_tsc(CPUX86State *env);
1941
1942
1943
1944# if defined(TARGET_X86_64)
1945# define TCG_PHYS_ADDR_BITS 40
1946# else
1947# define TCG_PHYS_ADDR_BITS 36
1948# endif
1949
1950#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
1951
1952#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
1953#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
1954#define CPU_RESOLVING_TYPE TYPE_X86_CPU
1955
1956#ifdef TARGET_X86_64
1957#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
1958#else
1959#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
1960#endif
1961
1962#define cpu_signal_handler cpu_x86_signal_handler
1963#define cpu_list x86_cpu_list
1964
1965
1966#define MMU_KSMAP_IDX 0
1967#define MMU_USER_IDX 1
1968#define MMU_KNOSMAP_IDX 2
1969static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
1970{
1971 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1972 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1973 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1974}
1975
1976static inline int cpu_mmu_index_kernel(CPUX86State *env)
1977{
1978 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
1979 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
1980 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1981}
1982
1983#define CC_DST (env->cc_dst)
1984#define CC_SRC (env->cc_src)
1985#define CC_SRC2 (env->cc_src2)
1986#define CC_OP (env->cc_op)
1987
1988
1989static inline target_long lshift(target_long x, int n)
1990{
1991 if (n >= 0) {
1992 return x << n;
1993 } else {
1994 return x >> (-n);
1995 }
1996}
1997
1998
1999#define FT0 (env->ft0)
2000#define ST0 (env->fpregs[env->fpstt].d)
2001#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
2002#define ST1 ST(1)
2003
2004
2005void tcg_x86_init(void);
2006
2007typedef CPUX86State CPUArchState;
2008typedef X86CPU ArchCPU;
2009
2010#include "exec/cpu-all.h"
2011#include "svm.h"
2012
2013#if !defined(CONFIG_USER_ONLY)
2014#include "hw/i386/apic.h"
2015#endif
2016
2017static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
2018 target_ulong *cs_base, uint32_t *flags)
2019{
2020 *cs_base = env->segs[R_CS].base;
2021 *pc = *cs_base + env->eip;
2022 *flags = env->hflags |
2023 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
2024}
2025
2026void do_cpu_init(X86CPU *cpu);
2027void do_cpu_sipi(X86CPU *cpu);
2028
2029#define MCE_INJECT_BROADCAST 1
2030#define MCE_INJECT_UNCOND_AO 2
2031
2032void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
2033 uint64_t status, uint64_t mcg_status, uint64_t addr,
2034 uint64_t misc, int flags);
2035
2036
2037void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
2038void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
2039 uintptr_t retaddr);
2040void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
2041 int error_code);
2042void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
2043 int error_code, uintptr_t retaddr);
2044void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
2045 int error_code, int next_eip_addend);
2046
2047
2048extern const uint8_t parity_table[256];
2049uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
2050
2051static inline uint32_t cpu_compute_eflags(CPUX86State *env)
2052{
2053 uint32_t eflags = env->eflags;
2054 if (tcg_enabled()) {
2055 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
2056 }
2057 return eflags;
2058}
2059
2060
2061
2062
2063static inline void cpu_load_eflags(CPUX86State *env, int eflags,
2064 int update_mask)
2065{
2066 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
2067 CC_OP = CC_OP_EFLAGS;
2068 env->df = 1 - (2 * ((eflags >> 10) & 1));
2069 env->eflags = (env->eflags & ~update_mask) |
2070 (eflags & update_mask) | 0x2;
2071}
2072
2073
2074
2075static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
2076{
2077 env->efer = val;
2078 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
2079 if (env->efer & MSR_EFER_LMA) {
2080 env->hflags |= HF_LMA_MASK;
2081 }
2082 if (env->efer & MSR_EFER_SVME) {
2083 env->hflags |= HF_SVME_MASK;
2084 }
2085}
2086
2087static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
2088{
2089 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
2090}
2091
2092static inline int32_t x86_get_a20_mask(CPUX86State *env)
2093{
2094 if (env->hflags & HF_SMM_MASK) {
2095 return -1;
2096 } else {
2097 return env->a20_mask;
2098 }
2099}
2100
2101static inline bool cpu_has_vmx(CPUX86State *env)
2102{
2103 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX;
2104}
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122static inline bool cpu_vmx_maybe_enabled(CPUX86State *env)
2123{
2124 return cpu_has_vmx(env) &&
2125 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK));
2126}
2127
2128
2129void update_fp_status(CPUX86State *env);
2130void update_mxcsr_status(CPUX86State *env);
2131
2132static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
2133{
2134 env->mxcsr = mxcsr;
2135 if (tcg_enabled()) {
2136 update_mxcsr_status(env);
2137 }
2138}
2139
2140static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
2141{
2142 env->fpuc = fpuc;
2143 if (tcg_enabled()) {
2144 update_fp_status(env);
2145 }
2146}
2147
2148
2149void helper_lock_init(void);
2150
2151
2152void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2153 uint64_t param, uintptr_t retaddr);
2154void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
2155 uint64_t exit_info_1, uintptr_t retaddr);
2156void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
2157
2158
2159void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
2160
2161
2162void do_smm_enter(X86CPU *cpu);
2163
2164
2165void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
2166void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
2167 TPRAccess access);
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178void x86_cpu_change_kvm_default(const char *prop, const char *value);
2179
2180
2181
2182
2183#define CPU_VERSION_LATEST -1
2184
2185
2186
2187
2188
2189#define CPU_VERSION_AUTO -2
2190
2191
2192#define CPU_VERSION_LEGACY 0
2193
2194typedef int X86CPUVersion;
2195
2196
2197
2198
2199
2200void x86_cpu_set_default_version(X86CPUVersion version);
2201
2202
2203const char *get_register_name_32(unsigned int reg);
2204
2205void enable_compat_apic_id_mode(void);
2206
2207#define APIC_DEFAULT_ADDRESS 0xfee00000
2208#define APIC_SPACE_SIZE 0x100000
2209
2210void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
2211
2212
2213bool cpu_is_bsp(X86CPU *cpu);
2214
2215void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf);
2216void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf);
2217void x86_update_hflags(CPUX86State* env);
2218
2219static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat)
2220{
2221 return !!(cpu->hyperv_features & BIT(feat));
2222}
2223
2224#if defined(TARGET_X86_64) && \
2225 defined(CONFIG_USER_ONLY) && \
2226 defined(CONFIG_LINUX)
2227# define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20)
2228#endif
2229
2230#endif
2231