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22#include "qemu/osdep.h"
23#include "hw/irq.h"
24#include "hw/acpi/acpi.h"
25#include "hw/nvram/fw_cfg.h"
26#include "qemu/config-file.h"
27#include "qapi/error.h"
28#include "qapi/opts-visitor.h"
29#include "qapi/qapi-events-run-state.h"
30#include "qapi/qapi-visit-misc.h"
31#include "qemu/error-report.h"
32#include "qemu/module.h"
33#include "qemu/option.h"
34#include "sysemu/runstate.h"
35
36struct acpi_table_header {
37 uint16_t _length;
38
39 char sig[4]
40 QEMU_NONSTRING;
41 uint32_t length;
42 uint8_t revision;
43 uint8_t checksum;
44 char oem_id[6]
45 QEMU_NONSTRING;
46 char oem_table_id[8]
47 QEMU_NONSTRING;
48 uint32_t oem_revision;
49 char asl_compiler_id[4]
50 QEMU_NONSTRING;
51 uint32_t asl_compiler_revision;
52} QEMU_PACKED;
53
54#define ACPI_TABLE_HDR_SIZE sizeof(struct acpi_table_header)
55#define ACPI_TABLE_PFX_SIZE sizeof(uint16_t)
56
57static const char unsigned dfl_hdr[ACPI_TABLE_HDR_SIZE - ACPI_TABLE_PFX_SIZE] =
58 "QEMU\0\0\0\0\1\0"
59 "QEMUQEQEMUQEMU\1\0\0\0"
60 "QEMU\1\0\0\0"
61 ;
62
63char unsigned *acpi_tables;
64size_t acpi_tables_len;
65
66static QemuOptsList qemu_acpi_opts = {
67 .name = "acpi",
68 .implied_opt_name = "data",
69 .head = QTAILQ_HEAD_INITIALIZER(qemu_acpi_opts.head),
70 .desc = { { 0 } }
71};
72
73static void acpi_register_config(void)
74{
75 qemu_add_opts(&qemu_acpi_opts);
76}
77
78opts_init(acpi_register_config);
79
80static int acpi_checksum(const uint8_t *data, int len)
81{
82 int sum, i;
83 sum = 0;
84 for (i = 0; i < len; i++) {
85 sum += data[i];
86 }
87 return (-sum) & 0xff;
88}
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107static void acpi_table_install(const char unsigned *blob, size_t bloblen,
108 bool has_header,
109 const struct AcpiTableOptions *hdrs,
110 Error **errp)
111{
112 size_t body_start;
113 const char unsigned *hdr_src;
114 size_t body_size, acpi_payload_size;
115 struct acpi_table_header *ext_hdr;
116 unsigned changed_fields;
117
118
119
120
121 if (has_header) {
122
123
124
125
126
127
128
129
130 body_start = sizeof dfl_hdr;
131
132 if (bloblen < body_start) {
133 error_setg(errp, "ACPI table claiming to have header is too "
134 "short, available: %zu, expected: %zu", bloblen,
135 body_start);
136 return;
137 }
138 hdr_src = blob;
139 } else {
140
141
142
143
144
145
146
147
148 body_start = 0;
149 hdr_src = dfl_hdr;
150 }
151 body_size = bloblen - body_start;
152 acpi_payload_size = sizeof dfl_hdr + body_size;
153
154 if (acpi_payload_size > UINT16_MAX) {
155 error_setg(errp, "ACPI table too big, requested: %zu, max: %u",
156 acpi_payload_size, (unsigned)UINT16_MAX);
157 return;
158 }
159
160
161 if (acpi_tables == NULL) {
162 acpi_tables_len = sizeof(uint16_t);
163 acpi_tables = g_malloc0(acpi_tables_len);
164 }
165
166 acpi_tables = g_realloc(acpi_tables, acpi_tables_len +
167 ACPI_TABLE_PFX_SIZE +
168 sizeof dfl_hdr + body_size);
169
170 ext_hdr = (struct acpi_table_header *)(acpi_tables + acpi_tables_len);
171 acpi_tables_len += ACPI_TABLE_PFX_SIZE;
172
173 memcpy(acpi_tables + acpi_tables_len, hdr_src, sizeof dfl_hdr);
174 acpi_tables_len += sizeof dfl_hdr;
175
176 if (blob != NULL) {
177 memcpy(acpi_tables + acpi_tables_len, blob + body_start, body_size);
178 acpi_tables_len += body_size;
179 }
180
181
182 stw_le_p(acpi_tables, lduw_le_p(acpi_tables) + 1u);
183
184
185 changed_fields = 0;
186 ext_hdr->_length = cpu_to_le16(acpi_payload_size);
187
188 if (hdrs->has_sig) {
189 strncpy(ext_hdr->sig, hdrs->sig, sizeof ext_hdr->sig);
190 ++changed_fields;
191 }
192
193 if (has_header && le32_to_cpu(ext_hdr->length) != acpi_payload_size) {
194 warn_report("ACPI table has wrong length, header says "
195 "%" PRIu32 ", actual size %zu bytes",
196 le32_to_cpu(ext_hdr->length), acpi_payload_size);
197 }
198 ext_hdr->length = cpu_to_le32(acpi_payload_size);
199
200 if (hdrs->has_rev) {
201 ext_hdr->revision = hdrs->rev;
202 ++changed_fields;
203 }
204
205 ext_hdr->checksum = 0;
206
207 if (hdrs->has_oem_id) {
208 strncpy(ext_hdr->oem_id, hdrs->oem_id, sizeof ext_hdr->oem_id);
209 ++changed_fields;
210 }
211 if (hdrs->has_oem_table_id) {
212 strncpy(ext_hdr->oem_table_id, hdrs->oem_table_id,
213 sizeof ext_hdr->oem_table_id);
214 ++changed_fields;
215 }
216 if (hdrs->has_oem_rev) {
217 ext_hdr->oem_revision = cpu_to_le32(hdrs->oem_rev);
218 ++changed_fields;
219 }
220 if (hdrs->has_asl_compiler_id) {
221 strncpy(ext_hdr->asl_compiler_id, hdrs->asl_compiler_id,
222 sizeof ext_hdr->asl_compiler_id);
223 ++changed_fields;
224 }
225 if (hdrs->has_asl_compiler_rev) {
226 ext_hdr->asl_compiler_revision = cpu_to_le32(hdrs->asl_compiler_rev);
227 ++changed_fields;
228 }
229
230 if (!has_header && changed_fields == 0) {
231 warn_report("ACPI table: no headers are specified");
232 }
233
234
235 ext_hdr->checksum = acpi_checksum((const char unsigned *)ext_hdr +
236 ACPI_TABLE_PFX_SIZE, acpi_payload_size);
237}
238
239void acpi_table_add(const QemuOpts *opts, Error **errp)
240{
241 AcpiTableOptions *hdrs = NULL;
242 Error *err = NULL;
243 char **pathnames = NULL;
244 char **cur;
245 size_t bloblen = 0;
246 char unsigned *blob = NULL;
247
248 {
249 Visitor *v;
250
251 v = opts_visitor_new(opts);
252 visit_type_AcpiTableOptions(v, NULL, &hdrs, &err);
253 visit_free(v);
254 }
255
256 if (err) {
257 goto out;
258 }
259 if (hdrs->has_file == hdrs->has_data) {
260 error_setg(&err, "'-acpitable' requires one of 'data' or 'file'");
261 goto out;
262 }
263
264 pathnames = g_strsplit(hdrs->has_file ? hdrs->file : hdrs->data, ":", 0);
265 if (pathnames == NULL || pathnames[0] == NULL) {
266 error_setg(&err, "'-acpitable' requires at least one pathname");
267 goto out;
268 }
269
270
271 for (cur = pathnames; *cur; ++cur) {
272 int fd = open(*cur, O_RDONLY | O_BINARY);
273
274 if (fd < 0) {
275 error_setg(&err, "can't open file %s: %s", *cur, strerror(errno));
276 goto out;
277 }
278
279 for (;;) {
280 char unsigned data[8192];
281 ssize_t r;
282
283 r = read(fd, data, sizeof data);
284 if (r == 0) {
285 break;
286 } else if (r > 0) {
287 blob = g_realloc(blob, bloblen + r);
288 memcpy(blob + bloblen, data, r);
289 bloblen += r;
290 } else if (errno != EINTR) {
291 error_setg(&err, "can't read file %s: %s",
292 *cur, strerror(errno));
293 close(fd);
294 goto out;
295 }
296 }
297
298 close(fd);
299 }
300
301 acpi_table_install(blob, bloblen, hdrs->has_file, hdrs, &err);
302
303out:
304 g_free(blob);
305 g_strfreev(pathnames);
306 qapi_free_AcpiTableOptions(hdrs);
307
308 error_propagate(errp, err);
309}
310
311unsigned acpi_table_len(void *current)
312{
313 struct acpi_table_header *hdr = current - sizeof(hdr->_length);
314 return hdr->_length;
315}
316
317static
318void *acpi_table_hdr(void *h)
319{
320 struct acpi_table_header *hdr = h;
321 return &hdr->sig;
322}
323
324uint8_t *acpi_table_first(void)
325{
326 if (!acpi_tables) {
327 return NULL;
328 }
329 return acpi_table_hdr(acpi_tables + ACPI_TABLE_PFX_SIZE);
330}
331
332uint8_t *acpi_table_next(uint8_t *current)
333{
334 uint8_t *next = current + acpi_table_len(current);
335
336 if (next - acpi_tables >= acpi_tables_len) {
337 return NULL;
338 } else {
339 return acpi_table_hdr(next);
340 }
341}
342
343int acpi_get_slic_oem(AcpiSlicOem *oem)
344{
345 uint8_t *u;
346
347 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
348 struct acpi_table_header *hdr = (void *)(u - sizeof(hdr->_length));
349
350 if (memcmp(hdr->sig, "SLIC", 4) == 0) {
351 oem->id = hdr->oem_id;
352 oem->table_id = hdr->oem_table_id;
353 return 0;
354 }
355 }
356 return -1;
357}
358
359static void acpi_notify_wakeup(Notifier *notifier, void *data)
360{
361 ACPIREGS *ar = container_of(notifier, ACPIREGS, wakeup);
362 WakeupReason *reason = data;
363
364 switch (*reason) {
365 case QEMU_WAKEUP_REASON_RTC:
366 ar->pm1.evt.sts |=
367 (ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_RT_CLOCK_STATUS);
368 break;
369 case QEMU_WAKEUP_REASON_PMTIMER:
370 ar->pm1.evt.sts |=
371 (ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_TIMER_STATUS);
372 break;
373 case QEMU_WAKEUP_REASON_OTHER:
374
375
376 ar->pm1.evt.sts |=
377 (ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_POWER_BUTTON_STATUS);
378 break;
379 default:
380 break;
381 }
382}
383
384
385uint16_t acpi_pm1_evt_get_sts(ACPIREGS *ar)
386{
387
388
389 int64_t d = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
390 if (d >= muldiv64(ar->tmr.overflow_time,
391 NANOSECONDS_PER_SECOND, PM_TIMER_FREQUENCY)) {
392 ar->pm1.evt.sts |= ACPI_BITMASK_TIMER_STATUS;
393 }
394 return ar->pm1.evt.sts;
395}
396
397static void acpi_pm1_evt_write_sts(ACPIREGS *ar, uint16_t val)
398{
399 uint16_t pm1_sts = acpi_pm1_evt_get_sts(ar);
400 if (pm1_sts & val & ACPI_BITMASK_TIMER_STATUS) {
401
402 acpi_pm_tmr_calc_overflow_time(ar);
403 }
404 ar->pm1.evt.sts &= ~val;
405}
406
407static void acpi_pm1_evt_write_en(ACPIREGS *ar, uint16_t val)
408{
409 ar->pm1.evt.en = val;
410 qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_RTC,
411 val & ACPI_BITMASK_RT_CLOCK_ENABLE);
412 qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_PMTIMER,
413 val & ACPI_BITMASK_TIMER_ENABLE);
414}
415
416void acpi_pm1_evt_power_down(ACPIREGS *ar)
417{
418 if (ar->pm1.evt.en & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
419 ar->pm1.evt.sts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
420 ar->tmr.update_sci(ar);
421 }
422}
423
424void acpi_pm1_evt_reset(ACPIREGS *ar)
425{
426 ar->pm1.evt.sts = 0;
427 ar->pm1.evt.en = 0;
428 qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_RTC, 0);
429 qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_PMTIMER, 0);
430}
431
432static uint64_t acpi_pm_evt_read(void *opaque, hwaddr addr, unsigned width)
433{
434 ACPIREGS *ar = opaque;
435 switch (addr) {
436 case 0:
437 return acpi_pm1_evt_get_sts(ar);
438 case 2:
439 return ar->pm1.evt.en;
440 default:
441 return 0;
442 }
443}
444
445static void acpi_pm_evt_write(void *opaque, hwaddr addr, uint64_t val,
446 unsigned width)
447{
448 ACPIREGS *ar = opaque;
449 switch (addr) {
450 case 0:
451 acpi_pm1_evt_write_sts(ar, val);
452 ar->pm1.evt.update_sci(ar);
453 break;
454 case 2:
455 acpi_pm1_evt_write_en(ar, val);
456 ar->pm1.evt.update_sci(ar);
457 break;
458 }
459}
460
461static const MemoryRegionOps acpi_pm_evt_ops = {
462 .read = acpi_pm_evt_read,
463 .write = acpi_pm_evt_write,
464 .impl.min_access_size = 2,
465 .valid.min_access_size = 1,
466 .valid.max_access_size = 2,
467 .endianness = DEVICE_LITTLE_ENDIAN,
468};
469
470void acpi_pm1_evt_init(ACPIREGS *ar, acpi_update_sci_fn update_sci,
471 MemoryRegion *parent)
472{
473 ar->pm1.evt.update_sci = update_sci;
474 memory_region_init_io(&ar->pm1.evt.io, memory_region_owner(parent),
475 &acpi_pm_evt_ops, ar, "acpi-evt", 4);
476 memory_region_add_subregion(parent, 0, &ar->pm1.evt.io);
477}
478
479
480void acpi_pm_tmr_update(ACPIREGS *ar, bool enable)
481{
482 int64_t expire_time;
483
484
485 if (enable) {
486 expire_time = muldiv64(ar->tmr.overflow_time, NANOSECONDS_PER_SECOND,
487 PM_TIMER_FREQUENCY);
488 timer_mod(ar->tmr.timer, expire_time);
489 } else {
490 timer_del(ar->tmr.timer);
491 }
492}
493
494static inline int64_t acpi_pm_tmr_get_clock(void)
495{
496 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), PM_TIMER_FREQUENCY,
497 NANOSECONDS_PER_SECOND);
498}
499
500void acpi_pm_tmr_calc_overflow_time(ACPIREGS *ar)
501{
502 int64_t d = acpi_pm_tmr_get_clock();
503 ar->tmr.overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
504}
505
506static uint32_t acpi_pm_tmr_get(ACPIREGS *ar)
507{
508 uint32_t d = acpi_pm_tmr_get_clock();
509 return d & 0xffffff;
510}
511
512static void acpi_pm_tmr_timer(void *opaque)
513{
514 ACPIREGS *ar = opaque;
515
516 qemu_system_wakeup_request(QEMU_WAKEUP_REASON_PMTIMER, NULL);
517 ar->tmr.update_sci(ar);
518}
519
520static uint64_t acpi_pm_tmr_read(void *opaque, hwaddr addr, unsigned width)
521{
522 return acpi_pm_tmr_get(opaque);
523}
524
525static void acpi_pm_tmr_write(void *opaque, hwaddr addr, uint64_t val,
526 unsigned width)
527{
528
529}
530
531static const MemoryRegionOps acpi_pm_tmr_ops = {
532 .read = acpi_pm_tmr_read,
533 .write = acpi_pm_tmr_write,
534 .impl.min_access_size = 4,
535 .valid.min_access_size = 1,
536 .valid.max_access_size = 4,
537 .endianness = DEVICE_LITTLE_ENDIAN,
538};
539
540void acpi_pm_tmr_init(ACPIREGS *ar, acpi_update_sci_fn update_sci,
541 MemoryRegion *parent)
542{
543 ar->tmr.update_sci = update_sci;
544 ar->tmr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, acpi_pm_tmr_timer, ar);
545 memory_region_init_io(&ar->tmr.io, memory_region_owner(parent),
546 &acpi_pm_tmr_ops, ar, "acpi-tmr", 4);
547 memory_region_add_subregion(parent, 8, &ar->tmr.io);
548}
549
550void acpi_pm_tmr_reset(ACPIREGS *ar)
551{
552 ar->tmr.overflow_time = 0;
553 timer_del(ar->tmr.timer);
554}
555
556
557static void acpi_pm1_cnt_write(ACPIREGS *ar, uint16_t val)
558{
559 ar->pm1.cnt.cnt = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
560
561 if (val & ACPI_BITMASK_SLEEP_ENABLE) {
562
563 uint16_t sus_typ = (val >> 10) & 7;
564 switch(sus_typ) {
565 case 0:
566 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
567 break;
568 case 1:
569 qemu_system_suspend_request();
570 break;
571 default:
572 if (sus_typ == ar->pm1.cnt.s4_val) {
573 qapi_event_send_suspend_disk();
574 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
575 }
576 break;
577 }
578 }
579}
580
581void acpi_pm1_cnt_update(ACPIREGS *ar,
582 bool sci_enable, bool sci_disable)
583{
584
585 if (sci_enable) {
586 ar->pm1.cnt.cnt |= ACPI_BITMASK_SCI_ENABLE;
587 } else if (sci_disable) {
588 ar->pm1.cnt.cnt &= ~ACPI_BITMASK_SCI_ENABLE;
589 }
590}
591
592static uint64_t acpi_pm_cnt_read(void *opaque, hwaddr addr, unsigned width)
593{
594 ACPIREGS *ar = opaque;
595 return ar->pm1.cnt.cnt;
596}
597
598static void acpi_pm_cnt_write(void *opaque, hwaddr addr, uint64_t val,
599 unsigned width)
600{
601 acpi_pm1_cnt_write(opaque, val);
602}
603
604static const MemoryRegionOps acpi_pm_cnt_ops = {
605 .read = acpi_pm_cnt_read,
606 .write = acpi_pm_cnt_write,
607 .impl.min_access_size = 2,
608 .valid.min_access_size = 1,
609 .valid.max_access_size = 2,
610 .endianness = DEVICE_LITTLE_ENDIAN,
611};
612
613void acpi_pm1_cnt_init(ACPIREGS *ar, MemoryRegion *parent,
614 bool disable_s3, bool disable_s4, uint8_t s4_val)
615{
616 FWCfgState *fw_cfg;
617
618 ar->pm1.cnt.s4_val = s4_val;
619 ar->wakeup.notify = acpi_notify_wakeup;
620 qemu_register_wakeup_notifier(&ar->wakeup);
621
622
623
624
625 qemu_register_wakeup_support();
626
627 memory_region_init_io(&ar->pm1.cnt.io, memory_region_owner(parent),
628 &acpi_pm_cnt_ops, ar, "acpi-cnt", 2);
629 memory_region_add_subregion(parent, 4, &ar->pm1.cnt.io);
630
631 fw_cfg = fw_cfg_find();
632 if (fw_cfg) {
633 uint8_t suspend[6] = {128, 0, 0, 129, 128, 128};
634 suspend[3] = 1 | ((!disable_s3) << 7);
635 suspend[4] = s4_val | ((!disable_s4) << 7);
636
637 fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6);
638 }
639}
640
641void acpi_pm1_cnt_reset(ACPIREGS *ar)
642{
643 ar->pm1.cnt.cnt = 0;
644}
645
646
647void acpi_gpe_init(ACPIREGS *ar, uint8_t len)
648{
649 ar->gpe.len = len;
650
651
652
653
654 ar->gpe.sts = g_malloc0(len);
655 ar->gpe.en = g_malloc0(len);
656}
657
658void acpi_gpe_reset(ACPIREGS *ar)
659{
660 memset(ar->gpe.sts, 0, ar->gpe.len / 2);
661 memset(ar->gpe.en, 0, ar->gpe.len / 2);
662}
663
664static uint8_t *acpi_gpe_ioport_get_ptr(ACPIREGS *ar, uint32_t addr)
665{
666 uint8_t *cur = NULL;
667
668 if (addr < ar->gpe.len / 2) {
669 cur = ar->gpe.sts + addr;
670 } else if (addr < ar->gpe.len) {
671 cur = ar->gpe.en + addr - ar->gpe.len / 2;
672 } else {
673 abort();
674 }
675
676 return cur;
677}
678
679void acpi_gpe_ioport_writeb(ACPIREGS *ar, uint32_t addr, uint32_t val)
680{
681 uint8_t *cur;
682
683 cur = acpi_gpe_ioport_get_ptr(ar, addr);
684 if (addr < ar->gpe.len / 2) {
685
686 *cur = (*cur) & ~val;
687 } else if (addr < ar->gpe.len) {
688
689 *cur = val;
690 } else {
691 abort();
692 }
693}
694
695uint32_t acpi_gpe_ioport_readb(ACPIREGS *ar, uint32_t addr)
696{
697 uint8_t *cur;
698 uint32_t val;
699
700 cur = acpi_gpe_ioport_get_ptr(ar, addr);
701 val = 0;
702 if (cur != NULL) {
703 val = *cur;
704 }
705
706 return val;
707}
708
709void acpi_send_gpe_event(ACPIREGS *ar, qemu_irq irq,
710 AcpiEventStatusBits status)
711{
712 ar->gpe.sts[0] |= status;
713 acpi_update_sci(ar, irq);
714}
715
716void acpi_update_sci(ACPIREGS *regs, qemu_irq irq)
717{
718 int sci_level, pm1a_sts;
719
720 pm1a_sts = acpi_pm1_evt_get_sts(regs);
721
722 sci_level = ((pm1a_sts &
723 regs->pm1.evt.en & ACPI_BITMASK_PM1_COMMON_ENABLED) != 0) ||
724 ((regs->gpe.sts[0] & regs->gpe.en[0]) != 0);
725
726 qemu_set_irq(irq, sci_level);
727
728
729 acpi_pm_tmr_update(regs,
730 (regs->pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
731 !(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
732}
733