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25#include "qemu/osdep.h"
26#include "qemu/units.h"
27#include "qapi/error.h"
28#include "qemu-common.h"
29#include "cpu.h"
30#include "hw/ppc/ppc.h"
31#include "ppc405.h"
32#include "hw/rtc/m48t59.h"
33#include "hw/block/flash.h"
34#include "sysemu/sysemu.h"
35#include "sysemu/qtest.h"
36#include "sysemu/reset.h"
37#include "sysemu/block-backend.h"
38#include "hw/boards.h"
39#include "qemu/log.h"
40#include "qemu/error-report.h"
41#include "hw/loader.h"
42#include "exec/address-spaces.h"
43#include "qemu/cutils.h"
44
45#define BIOS_FILENAME "ppc405_rom.bin"
46#define BIOS_SIZE (2 * MiB)
47
48#define KERNEL_LOAD_ADDR 0x00000000
49#define INITRD_LOAD_ADDR 0x01800000
50
51#define USE_FLASH_BIOS
52
53
54
55
56
57
58
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60
61
62
63typedef struct ref405ep_fpga_t ref405ep_fpga_t;
64struct ref405ep_fpga_t {
65 uint8_t reg0;
66 uint8_t reg1;
67};
68
69static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
70{
71 ref405ep_fpga_t *fpga;
72 uint32_t ret;
73
74 fpga = opaque;
75 switch (addr) {
76 case 0x0:
77 ret = fpga->reg0;
78 break;
79 case 0x1:
80 ret = fpga->reg1;
81 break;
82 default:
83 ret = 0;
84 break;
85 }
86
87 return ret;
88}
89
90static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
91 unsigned size)
92{
93 ref405ep_fpga_t *fpga;
94
95 fpga = opaque;
96 switch (addr) {
97 case 0x0:
98
99 break;
100 case 0x1:
101 fpga->reg1 = value;
102 break;
103 default:
104 break;
105 }
106}
107
108static const MemoryRegionOps ref405ep_fpga_ops = {
109 .read = ref405ep_fpga_readb,
110 .write = ref405ep_fpga_writeb,
111 .impl.min_access_size = 1,
112 .impl.max_access_size = 1,
113 .valid.min_access_size = 1,
114 .valid.max_access_size = 4,
115 .endianness = DEVICE_BIG_ENDIAN,
116};
117
118static void ref405ep_fpga_reset (void *opaque)
119{
120 ref405ep_fpga_t *fpga;
121
122 fpga = opaque;
123 fpga->reg0 = 0x00;
124 fpga->reg1 = 0x0F;
125}
126
127static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
128{
129 ref405ep_fpga_t *fpga;
130 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
131
132 fpga = g_malloc0(sizeof(ref405ep_fpga_t));
133 memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
134 "fpga", 0x00000100);
135 memory_region_add_subregion(sysmem, base, fpga_memory);
136 qemu_register_reset(&ref405ep_fpga_reset, fpga);
137}
138
139static void ref405ep_init(MachineState *machine)
140{
141 MachineClass *mc = MACHINE_GET_CLASS(machine);
142 const char *kernel_filename = machine->kernel_filename;
143 const char *kernel_cmdline = machine->kernel_cmdline;
144 const char *initrd_filename = machine->initrd_filename;
145 char *filename;
146 ppc4xx_bd_info_t bd;
147 CPUPPCState *env;
148 qemu_irq *pic;
149 MemoryRegion *bios;
150 MemoryRegion *sram = g_new(MemoryRegion, 1);
151 ram_addr_t bdloc;
152 MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
153 hwaddr ram_bases[2], ram_sizes[2];
154 target_ulong sram_size;
155 long bios_size;
156
157
158 target_ulong kernel_base, initrd_base;
159 long kernel_size, initrd_size;
160 int linux_boot;
161 int len;
162 DriveInfo *dinfo;
163 MemoryRegion *sysmem = get_system_memory();
164
165 if (machine->ram_size != mc->default_ram_size) {
166 char *sz = size_to_str(mc->default_ram_size);
167 error_report("Invalid RAM size, should be %s", sz);
168 g_free(sz);
169 exit(EXIT_FAILURE);
170 }
171
172
173 memory_region_init_alias(&ram_memories[0], NULL, "ef405ep.ram.alias",
174 machine->ram, 0, machine->ram_size);
175 ram_bases[0] = 0;
176 ram_sizes[0] = machine->ram_size;
177 memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
178 ram_bases[1] = 0x00000000;
179 ram_sizes[1] = 0x00000000;
180 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
181 33333333, &pic, kernel_filename == NULL ? 0 : 1);
182
183 sram_size = 512 * KiB;
184 memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
185 &error_fatal);
186 memory_region_add_subregion(sysmem, 0xFFF00000, sram);
187
188#ifdef USE_FLASH_BIOS
189 dinfo = drive_get(IF_PFLASH, 0, 0);
190 if (dinfo) {
191 bios_size = 8 * MiB;
192 pflash_cfi02_register((uint32_t)(-bios_size),
193 "ef405ep.bios", bios_size,
194 blk_by_legacy_dinfo(dinfo),
195 64 * KiB, 1,
196 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
197 1);
198 } else
199#endif
200 {
201 bios = g_new(MemoryRegion, 1);
202 memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
203 &error_fatal);
204
205 if (bios_name == NULL)
206 bios_name = BIOS_FILENAME;
207 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
208 if (filename) {
209 bios_size = load_image_size(filename,
210 memory_region_get_ram_ptr(bios),
211 BIOS_SIZE);
212 g_free(filename);
213 if (bios_size < 0) {
214 error_report("Could not load PowerPC BIOS '%s'", bios_name);
215 exit(1);
216 }
217 bios_size = (bios_size + 0xfff) & ~0xfff;
218 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
219 } else if (!qtest_enabled() || kernel_filename != NULL) {
220 error_report("Could not load PowerPC BIOS '%s'", bios_name);
221 exit(1);
222 } else {
223
224 bios_size = -1;
225 }
226 }
227
228 ref405ep_fpga_init(sysmem, 0xF0300000);
229
230 m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8);
231
232 linux_boot = (kernel_filename != NULL);
233 if (linux_boot) {
234 memset(&bd, 0, sizeof(bd));
235 bd.bi_memstart = 0x00000000;
236 bd.bi_memsize = machine->ram_size;
237 bd.bi_flashstart = -bios_size;
238 bd.bi_flashsize = -bios_size;
239 bd.bi_flashoffset = 0;
240 bd.bi_sramstart = 0xFFF00000;
241 bd.bi_sramsize = sram_size;
242 bd.bi_bootflags = 0;
243 bd.bi_intfreq = 133333333;
244 bd.bi_busfreq = 33333333;
245 bd.bi_baudrate = 115200;
246 bd.bi_s_version[0] = 'Q';
247 bd.bi_s_version[1] = 'M';
248 bd.bi_s_version[2] = 'U';
249 bd.bi_s_version[3] = '\0';
250 bd.bi_r_version[0] = 'Q';
251 bd.bi_r_version[1] = 'E';
252 bd.bi_r_version[2] = 'M';
253 bd.bi_r_version[3] = 'U';
254 bd.bi_r_version[4] = '\0';
255 bd.bi_procfreq = 133333333;
256 bd.bi_plb_busfreq = 33333333;
257 bd.bi_pci_busfreq = 33333333;
258 bd.bi_opbfreq = 33333333;
259 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
260 env->gpr[3] = bdloc;
261 kernel_base = KERNEL_LOAD_ADDR;
262
263 kernel_size = load_image_targphys(kernel_filename, kernel_base,
264 machine->ram_size - kernel_base);
265 if (kernel_size < 0) {
266 error_report("could not load kernel '%s'", kernel_filename);
267 exit(1);
268 }
269 printf("Load kernel size %ld at " TARGET_FMT_lx,
270 kernel_size, kernel_base);
271
272 if (initrd_filename) {
273 initrd_base = INITRD_LOAD_ADDR;
274 initrd_size = load_image_targphys(initrd_filename, initrd_base,
275 machine->ram_size - initrd_base);
276 if (initrd_size < 0) {
277 error_report("could not load initial ram disk '%s'",
278 initrd_filename);
279 exit(1);
280 }
281 } else {
282 initrd_base = 0;
283 initrd_size = 0;
284 }
285 env->gpr[4] = initrd_base;
286 env->gpr[5] = initrd_size;
287 if (kernel_cmdline != NULL) {
288 len = strlen(kernel_cmdline);
289 bdloc -= ((len + 255) & ~255);
290 cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
291 env->gpr[6] = bdloc;
292 env->gpr[7] = bdloc + len;
293 } else {
294 env->gpr[6] = 0;
295 env->gpr[7] = 0;
296 }
297 env->nip = KERNEL_LOAD_ADDR;
298 } else {
299 kernel_base = 0;
300 kernel_size = 0;
301 initrd_base = 0;
302 initrd_size = 0;
303 bdloc = 0;
304 }
305}
306
307static void ref405ep_class_init(ObjectClass *oc, void *data)
308{
309 MachineClass *mc = MACHINE_CLASS(oc);
310
311 mc->desc = "ref405ep";
312 mc->init = ref405ep_init;
313 mc->default_ram_size = 0x08000000;
314 mc->default_ram_id = "ef405ep.ram";
315}
316
317static const TypeInfo ref405ep_type = {
318 .name = MACHINE_TYPE_NAME("ref405ep"),
319 .parent = TYPE_MACHINE,
320 .class_init = ref405ep_class_init,
321};
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342typedef struct taihu_cpld_t taihu_cpld_t;
343struct taihu_cpld_t {
344 uint8_t reg0;
345 uint8_t reg1;
346};
347
348static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size)
349{
350 taihu_cpld_t *cpld;
351 uint32_t ret;
352
353 cpld = opaque;
354 switch (addr) {
355 case 0x0:
356 ret = cpld->reg0;
357 break;
358 case 0x1:
359 ret = cpld->reg1;
360 break;
361 default:
362 ret = 0;
363 break;
364 }
365
366 return ret;
367}
368
369static void taihu_cpld_write(void *opaque, hwaddr addr,
370 uint64_t value, unsigned size)
371{
372 taihu_cpld_t *cpld;
373
374 cpld = opaque;
375 switch (addr) {
376 case 0x0:
377
378 break;
379 case 0x1:
380 cpld->reg1 = value;
381 break;
382 default:
383 break;
384 }
385}
386
387static const MemoryRegionOps taihu_cpld_ops = {
388 .read = taihu_cpld_read,
389 .write = taihu_cpld_write,
390 .impl = {
391 .min_access_size = 1,
392 .max_access_size = 1,
393 },
394 .endianness = DEVICE_NATIVE_ENDIAN,
395};
396
397static void taihu_cpld_reset (void *opaque)
398{
399 taihu_cpld_t *cpld;
400
401 cpld = opaque;
402 cpld->reg0 = 0x01;
403 cpld->reg1 = 0x80;
404}
405
406static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
407{
408 taihu_cpld_t *cpld;
409 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
410
411 cpld = g_malloc0(sizeof(taihu_cpld_t));
412 memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100);
413 memory_region_add_subregion(sysmem, base, cpld_memory);
414 qemu_register_reset(&taihu_cpld_reset, cpld);
415}
416
417static void taihu_405ep_init(MachineState *machine)
418{
419 MachineClass *mc = MACHINE_GET_CLASS(machine);
420 const char *kernel_filename = machine->kernel_filename;
421 const char *initrd_filename = machine->initrd_filename;
422 char *filename;
423 qemu_irq *pic;
424 MemoryRegion *sysmem = get_system_memory();
425 MemoryRegion *bios;
426 MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
427 hwaddr ram_bases[2], ram_sizes[2];
428 long bios_size;
429 target_ulong kernel_base, initrd_base;
430 long kernel_size, initrd_size;
431 int linux_boot;
432 int fl_idx;
433 DriveInfo *dinfo;
434
435 if (machine->ram_size != mc->default_ram_size) {
436 char *sz = size_to_str(mc->default_ram_size);
437 error_report("Invalid RAM size, should be %s", sz);
438 g_free(sz);
439 exit(EXIT_FAILURE);
440 }
441
442 ram_bases[0] = 0;
443 ram_sizes[0] = 0x04000000;
444 memory_region_init_alias(&ram_memories[0], NULL,
445 "taihu_405ep.ram-0", machine->ram, ram_bases[0],
446 ram_sizes[0]);
447 ram_bases[1] = 0x04000000;
448 ram_sizes[1] = 0x04000000;
449 memory_region_init_alias(&ram_memories[1], NULL,
450 "taihu_405ep.ram-1", machine->ram, ram_bases[1],
451 ram_sizes[1]);
452 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
453 33333333, &pic, kernel_filename == NULL ? 0 : 1);
454
455 fl_idx = 0;
456#if defined(USE_FLASH_BIOS)
457 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
458 if (dinfo) {
459 bios_size = 2 * MiB;
460 pflash_cfi02_register(0xFFE00000,
461 "taihu_405ep.bios", bios_size,
462 blk_by_legacy_dinfo(dinfo),
463 64 * KiB, 1,
464 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
465 1);
466 fl_idx++;
467 } else
468#endif
469 {
470 if (bios_name == NULL)
471 bios_name = BIOS_FILENAME;
472 bios = g_new(MemoryRegion, 1);
473 memory_region_init_rom(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
474 &error_fatal);
475 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
476 if (filename) {
477 bios_size = load_image_size(filename,
478 memory_region_get_ram_ptr(bios),
479 BIOS_SIZE);
480 g_free(filename);
481 if (bios_size < 0) {
482 error_report("Could not load PowerPC BIOS '%s'", bios_name);
483 exit(1);
484 }
485 bios_size = (bios_size + 0xfff) & ~0xfff;
486 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
487 } else if (!qtest_enabled()) {
488 error_report("Could not load PowerPC BIOS '%s'", bios_name);
489 exit(1);
490 }
491 }
492
493 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
494 if (dinfo) {
495 bios_size = 32 * MiB;
496 pflash_cfi02_register(0xfc000000, "taihu_405ep.flash", bios_size,
497 blk_by_legacy_dinfo(dinfo),
498 64 * KiB, 1,
499 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
500 1);
501 fl_idx++;
502 }
503
504 taihu_cpld_init(sysmem, 0x50100000);
505
506 linux_boot = (kernel_filename != NULL);
507 if (linux_boot) {
508 kernel_base = KERNEL_LOAD_ADDR;
509
510 kernel_size = load_image_targphys(kernel_filename, kernel_base,
511 machine->ram_size - kernel_base);
512 if (kernel_size < 0) {
513 error_report("could not load kernel '%s'", kernel_filename);
514 exit(1);
515 }
516
517 if (initrd_filename) {
518 initrd_base = INITRD_LOAD_ADDR;
519 initrd_size = load_image_targphys(initrd_filename, initrd_base,
520 machine->ram_size - initrd_base);
521 if (initrd_size < 0) {
522 error_report("could not load initial ram disk '%s'",
523 initrd_filename);
524 exit(1);
525 }
526 } else {
527 initrd_base = 0;
528 initrd_size = 0;
529 }
530 } else {
531 kernel_base = 0;
532 kernel_size = 0;
533 initrd_base = 0;
534 initrd_size = 0;
535 }
536}
537
538static void taihu_class_init(ObjectClass *oc, void *data)
539{
540 MachineClass *mc = MACHINE_CLASS(oc);
541
542 mc->desc = "taihu";
543 mc->init = taihu_405ep_init;
544 mc->default_ram_size = 0x08000000;
545 mc->default_ram_id = "taihu_405ep.ram";
546}
547
548static const TypeInfo taihu_type = {
549 .name = MACHINE_TYPE_NAME("taihu"),
550 .parent = TYPE_MACHINE,
551 .class_init = taihu_class_init,
552};
553
554static void ppc405_machine_init(void)
555{
556 type_register_static(&ref405ep_type);
557 type_register_static(&taihu_type);
558}
559
560type_init(ppc405_machine_init)
561
