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22#include "qemu/osdep.h"
23
24#include "qemu/module.h"
25#include "qemu/timer.h"
26#include "sysemu/watchdog.h"
27#include "hw/pci/pci.h"
28#include "migration/vmstate.h"
29
30
31
32#ifdef I6300ESB_DEBUG
33#define i6300esb_debug(fs,...) \
34 fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
35#else
36#define i6300esb_debug(fs,...)
37#endif
38
39
40#define ESB_CONFIG_REG 0x60
41#define ESB_LOCK_REG 0x68
42
43
44#define ESB_TIMER1_REG 0x00
45#define ESB_TIMER2_REG 0x04
46#define ESB_GINTSR_REG 0x08
47#define ESB_RELOAD_REG 0x0c
48
49
50#define ESB_WDT_FUNC (0x01 << 2)
51#define ESB_WDT_ENABLE (0x01 << 1)
52#define ESB_WDT_LOCK (0x01 << 0)
53
54
55#define ESB_WDT_REBOOT (0x01 << 5)
56#define ESB_WDT_FREQ (0x01 << 2)
57#define ESB_WDT_INTTYPE (0x11 << 0)
58
59
60#define ESB_WDT_RELOAD (0x01 << 8)
61
62
63#define ESB_UNLOCK1 0x80
64#define ESB_UNLOCK2 0x86
65
66
67struct I6300State {
68 PCIDevice dev;
69 MemoryRegion io_mem;
70
71 int reboot_enabled;
72
73
74
75 int clock_scale;
76#define CLOCK_SCALE_1KHZ 0
77#define CLOCK_SCALE_1MHZ 1
78
79 int int_type;
80#define INT_TYPE_IRQ 0
81#define INT_TYPE_SMI 2
82#define INT_TYPE_DISABLED 3
83
84 int free_run;
85 int locked;
86 int enabled;
87
88 QEMUTimer *timer;
89
90 uint32_t timer1_preload;
91 uint32_t timer2_preload;
92 int stage;
93
94 int unlock_state;
95
96
97
98
99 int previous_reboot_flag;
100
101
102};
103
104typedef struct I6300State I6300State;
105
106#define TYPE_WATCHDOG_I6300ESB_DEVICE "i6300esb"
107#define WATCHDOG_I6300ESB_DEVICE(obj) \
108 OBJECT_CHECK(I6300State, (obj), TYPE_WATCHDOG_I6300ESB_DEVICE)
109
110
111
112
113static void i6300esb_restart_timer(I6300State *d, int stage)
114{
115 int64_t timeout;
116
117 if (!d->enabled)
118 return;
119
120 d->stage = stage;
121
122 if (d->stage <= 1)
123 timeout = d->timer1_preload;
124 else
125 timeout = d->timer2_preload;
126
127 if (d->clock_scale == CLOCK_SCALE_1KHZ)
128 timeout <<= 15;
129 else
130 timeout <<= 5;
131
132
133
134 timeout = timeout * 30;
135
136 i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);
137
138 timer_mod(d->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);
139}
140
141
142static void i6300esb_disable_timer(I6300State *d)
143{
144 i6300esb_debug("timer disabled\n");
145
146 timer_del(d->timer);
147}
148
149static void i6300esb_reset(DeviceState *dev)
150{
151 PCIDevice *pdev = PCI_DEVICE(dev);
152 I6300State *d = WATCHDOG_I6300ESB_DEVICE(pdev);
153
154 i6300esb_debug("I6300State = %p\n", d);
155
156 i6300esb_disable_timer(d);
157
158
159
160 d->reboot_enabled = 1;
161 d->clock_scale = CLOCK_SCALE_1KHZ;
162 d->int_type = INT_TYPE_IRQ;
163 d->free_run = 0;
164 d->locked = 0;
165 d->enabled = 0;
166 d->timer1_preload = 0xfffff;
167 d->timer2_preload = 0xfffff;
168 d->stage = 1;
169 d->unlock_state = 0;
170}
171
172
173
174
175
176
177
178
179static void i6300esb_timer_expired(void *vp)
180{
181 I6300State *d = vp;
182
183 i6300esb_debug("stage %d\n", d->stage);
184
185 if (d->stage == 1) {
186
187 switch (d->int_type) {
188 case INT_TYPE_IRQ:
189 fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
190 break;
191 case INT_TYPE_SMI:
192 fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
193 break;
194 }
195
196
197 i6300esb_restart_timer(d, 2);
198 } else {
199
200 if (d->reboot_enabled) {
201 d->previous_reboot_flag = 1;
202 watchdog_perform_action();
203 i6300esb_reset(DEVICE(d));
204 }
205
206
207 if (d->free_run)
208 i6300esb_restart_timer(d, 1);
209 }
210}
211
212static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
213 uint32_t data, int len)
214{
215 I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
216 int old;
217
218 i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);
219
220 if (addr == ESB_CONFIG_REG && len == 2) {
221 d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
222 d->clock_scale =
223 (data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
224 d->int_type = (data & ESB_WDT_INTTYPE);
225 } else if (addr == ESB_LOCK_REG && len == 1) {
226 if (!d->locked) {
227 d->locked = (data & ESB_WDT_LOCK) != 0;
228 d->free_run = (data & ESB_WDT_FUNC) != 0;
229 old = d->enabled;
230 d->enabled = (data & ESB_WDT_ENABLE) != 0;
231 if (!old && d->enabled)
232 i6300esb_restart_timer(d, 1);
233 else if (!d->enabled)
234 i6300esb_disable_timer(d);
235 }
236 } else {
237 pci_default_write_config(dev, addr, data, len);
238 }
239}
240
241static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
242{
243 I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
244 uint32_t data;
245
246 i6300esb_debug ("addr = %x, len = %d\n", addr, len);
247
248 if (addr == ESB_CONFIG_REG && len == 2) {
249 data =
250 (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) |
251 (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) |
252 d->int_type;
253 return data;
254 } else if (addr == ESB_LOCK_REG && len == 1) {
255 data =
256 (d->free_run ? ESB_WDT_FUNC : 0) |
257 (d->locked ? ESB_WDT_LOCK : 0) |
258 (d->enabled ? ESB_WDT_ENABLE : 0);
259 return data;
260 } else {
261 return pci_default_read_config(dev, addr, len);
262 }
263}
264
265static uint32_t i6300esb_mem_readb(void *vp, hwaddr addr)
266{
267 i6300esb_debug ("addr = %x\n", (int) addr);
268
269 return 0;
270}
271
272static uint32_t i6300esb_mem_readw(void *vp, hwaddr addr)
273{
274 uint32_t data = 0;
275 I6300State *d = vp;
276
277 i6300esb_debug("addr = %x\n", (int) addr);
278
279 if (addr == 0xc) {
280
281
282
283
284 data = d->previous_reboot_flag ? 0x1200 : 0;
285 }
286
287 return data;
288}
289
290static uint32_t i6300esb_mem_readl(void *vp, hwaddr addr)
291{
292 i6300esb_debug("addr = %x\n", (int) addr);
293
294 return 0;
295}
296
297static void i6300esb_mem_writeb(void *vp, hwaddr addr, uint32_t val)
298{
299 I6300State *d = vp;
300
301 i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
302
303 if (addr == 0xc && val == 0x80)
304 d->unlock_state = 1;
305 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
306 d->unlock_state = 2;
307}
308
309static void i6300esb_mem_writew(void *vp, hwaddr addr, uint32_t val)
310{
311 I6300State *d = vp;
312
313 i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
314
315 if (addr == 0xc && val == 0x80)
316 d->unlock_state = 1;
317 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
318 d->unlock_state = 2;
319 else {
320 if (d->unlock_state == 2) {
321 if (addr == 0xc) {
322 if ((val & 0x100) != 0)
323
324
325
326 i6300esb_restart_timer(d, 1);
327
328
329
330
331
332 if ((val & 0x200) != 0 || (val & 0x1000) != 0) {
333 d->previous_reboot_flag = 0;
334 }
335 }
336
337 d->unlock_state = 0;
338 }
339 }
340}
341
342static void i6300esb_mem_writel(void *vp, hwaddr addr, uint32_t val)
343{
344 I6300State *d = vp;
345
346 i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);
347
348 if (addr == 0xc && val == 0x80)
349 d->unlock_state = 1;
350 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
351 d->unlock_state = 2;
352 else {
353 if (d->unlock_state == 2) {
354 if (addr == 0)
355 d->timer1_preload = val & 0xfffff;
356 else if (addr == 4)
357 d->timer2_preload = val & 0xfffff;
358
359 d->unlock_state = 0;
360 }
361 }
362}
363
364static uint64_t i6300esb_mem_readfn(void *opaque, hwaddr addr, unsigned size)
365{
366 switch (size) {
367 case 1:
368 return i6300esb_mem_readb(opaque, addr);
369 case 2:
370 return i6300esb_mem_readw(opaque, addr);
371 case 4:
372 return i6300esb_mem_readl(opaque, addr);
373 default:
374 g_assert_not_reached();
375 }
376}
377
378static void i6300esb_mem_writefn(void *opaque, hwaddr addr,
379 uint64_t value, unsigned size)
380{
381 switch (size) {
382 case 1:
383 i6300esb_mem_writeb(opaque, addr, value);
384 break;
385 case 2:
386 i6300esb_mem_writew(opaque, addr, value);
387 break;
388 case 4:
389 i6300esb_mem_writel(opaque, addr, value);
390 break;
391 default:
392 g_assert_not_reached();
393 }
394}
395
396static const MemoryRegionOps i6300esb_ops = {
397 .read = i6300esb_mem_readfn,
398 .write = i6300esb_mem_writefn,
399 .valid.min_access_size = 1,
400 .valid.max_access_size = 4,
401 .endianness = DEVICE_LITTLE_ENDIAN,
402};
403
404static const VMStateDescription vmstate_i6300esb = {
405 .name = "i6300esb_wdt",
406
407
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410
411
412
413
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416
417
418
419
420 .version_id = 10000,
421 .minimum_version_id = 1,
422 .fields = (VMStateField[]) {
423 VMSTATE_PCI_DEVICE(dev, I6300State),
424 VMSTATE_INT32(reboot_enabled, I6300State),
425 VMSTATE_INT32(clock_scale, I6300State),
426 VMSTATE_INT32(int_type, I6300State),
427 VMSTATE_INT32(free_run, I6300State),
428 VMSTATE_INT32(locked, I6300State),
429 VMSTATE_INT32(enabled, I6300State),
430 VMSTATE_TIMER_PTR(timer, I6300State),
431 VMSTATE_UINT32(timer1_preload, I6300State),
432 VMSTATE_UINT32(timer2_preload, I6300State),
433 VMSTATE_INT32(stage, I6300State),
434 VMSTATE_INT32(unlock_state, I6300State),
435 VMSTATE_INT32(previous_reboot_flag, I6300State),
436 VMSTATE_END_OF_LIST()
437 }
438};
439
440static void i6300esb_realize(PCIDevice *dev, Error **errp)
441{
442 I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
443
444 i6300esb_debug("I6300State = %p\n", d);
445
446 d->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, i6300esb_timer_expired, d);
447 d->previous_reboot_flag = 0;
448
449 memory_region_init_io(&d->io_mem, OBJECT(d), &i6300esb_ops, d,
450 "i6300esb", 0x10);
451 pci_register_bar(&d->dev, 0, 0, &d->io_mem);
452}
453
454static void i6300esb_exit(PCIDevice *dev)
455{
456 I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
457
458 timer_del(d->timer);
459 timer_free(d->timer);
460}
461
462static WatchdogTimerModel model = {
463 .wdt_name = "i6300esb",
464 .wdt_description = "Intel 6300ESB",
465};
466
467static void i6300esb_class_init(ObjectClass *klass, void *data)
468{
469 DeviceClass *dc = DEVICE_CLASS(klass);
470 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
471
472 k->config_read = i6300esb_config_read;
473 k->config_write = i6300esb_config_write;
474 k->realize = i6300esb_realize;
475 k->exit = i6300esb_exit;
476 k->vendor_id = PCI_VENDOR_ID_INTEL;
477 k->device_id = PCI_DEVICE_ID_INTEL_ESB_9;
478 k->class_id = PCI_CLASS_SYSTEM_OTHER;
479 dc->reset = i6300esb_reset;
480 dc->vmsd = &vmstate_i6300esb;
481 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
482}
483
484static const TypeInfo i6300esb_info = {
485 .name = TYPE_WATCHDOG_I6300ESB_DEVICE,
486 .parent = TYPE_PCI_DEVICE,
487 .instance_size = sizeof(I6300State),
488 .class_init = i6300esb_class_init,
489 .interfaces = (InterfaceInfo[]) {
490 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
491 { },
492 },
493};
494
495static void i6300esb_register_types(void)
496{
497 watchdog_add_model(&model);
498 type_register_static(&i6300esb_info);
499}
500
501type_init(i6300esb_register_types)
502