qemu/linux-user/ppc/signal.c
<<
>>
Prefs
   1/*
   2 *  Emulation of Linux signals
   3 *
   4 *  Copyright (c) 2003 Fabrice Bellard
   5 *
   6 *  This program is free software; you can redistribute it and/or modify
   7 *  it under the terms of the GNU General Public License as published by
   8 *  the Free Software Foundation; either version 2 of the License, or
   9 *  (at your option) any later version.
  10 *
  11 *  This program is distributed in the hope that it will be useful,
  12 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 *  GNU General Public License for more details.
  15 *
  16 *  You should have received a copy of the GNU General Public License
  17 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19#include "qemu/osdep.h"
  20#include "qemu.h"
  21#include "signal-common.h"
  22#include "linux-user/trace.h"
  23
  24/* Size of dummy stack frame allocated when calling signal handler.
  25   See arch/powerpc/include/asm/ptrace.h.  */
  26#if defined(TARGET_PPC64)
  27#define SIGNAL_FRAMESIZE 128
  28#else
  29#define SIGNAL_FRAMESIZE 64
  30#endif
  31
  32/* See arch/powerpc/include/asm/ucontext.h.  Only used for 32-bit PPC;
  33   on 64-bit PPC, sigcontext and mcontext are one and the same.  */
  34struct target_mcontext {
  35    target_ulong mc_gregs[48];
  36    /* Includes fpscr.  */
  37    uint64_t mc_fregs[33];
  38
  39#if defined(TARGET_PPC64)
  40    /* Pointer to the vector regs */
  41    target_ulong v_regs;
  42    /*
  43     * On ppc64, this mcontext structure is naturally *unaligned*,
  44     * or rather it is aligned on a 8 bytes boundary but not on
  45     * a 16 byte boundary.  This pad fixes it up.  This is why we
  46     * cannot use ppc_avr_t, which would force alignment.  This is
  47     * also why the vector regs are referenced in the ABI by the
  48     * v_regs pointer above so any amount of padding can be added here.
  49     */
  50    target_ulong pad;
  51    /* VSCR and VRSAVE are saved separately.  Also reserve space for VSX. */
  52    struct {
  53        uint64_t altivec[34 + 16][2];
  54    } mc_vregs;
  55#else
  56    target_ulong mc_pad[2];
  57
  58    /* We need to handle Altivec and SPE at the same time, which no
  59       kernel needs to do.  Fortunately, the kernel defines this bit to
  60       be Altivec-register-large all the time, rather than trying to
  61       twiddle it based on the specific platform.  */
  62    union {
  63        /* SPE vector registers.  One extra for SPEFSCR.  */
  64        uint32_t spe[33];
  65        /*
  66         * Altivec vector registers.  One extra for VRSAVE.
  67         * On ppc32, we are already aligned to 16 bytes.  We could
  68         * use ppc_avr_t, but choose to share the same type as ppc64.
  69         */
  70        uint64_t altivec[33][2];
  71    } mc_vregs;
  72#endif
  73};
  74
  75/* See arch/powerpc/include/asm/sigcontext.h.  */
  76struct target_sigcontext {
  77    target_ulong _unused[4];
  78    int32_t signal;
  79#if defined(TARGET_PPC64)
  80    int32_t pad0;
  81#endif
  82    target_ulong handler;
  83    target_ulong oldmask;
  84    target_ulong regs;      /* struct pt_regs __user * */
  85#if defined(TARGET_PPC64)
  86    struct target_mcontext mcontext;
  87#endif
  88};
  89
  90/* Indices for target_mcontext.mc_gregs, below.
  91   See arch/powerpc/include/asm/ptrace.h for details.  */
  92enum {
  93    TARGET_PT_R0 = 0,
  94    TARGET_PT_R1 = 1,
  95    TARGET_PT_R2 = 2,
  96    TARGET_PT_R3 = 3,
  97    TARGET_PT_R4 = 4,
  98    TARGET_PT_R5 = 5,
  99    TARGET_PT_R6 = 6,
 100    TARGET_PT_R7 = 7,
 101    TARGET_PT_R8 = 8,
 102    TARGET_PT_R9 = 9,
 103    TARGET_PT_R10 = 10,
 104    TARGET_PT_R11 = 11,
 105    TARGET_PT_R12 = 12,
 106    TARGET_PT_R13 = 13,
 107    TARGET_PT_R14 = 14,
 108    TARGET_PT_R15 = 15,
 109    TARGET_PT_R16 = 16,
 110    TARGET_PT_R17 = 17,
 111    TARGET_PT_R18 = 18,
 112    TARGET_PT_R19 = 19,
 113    TARGET_PT_R20 = 20,
 114    TARGET_PT_R21 = 21,
 115    TARGET_PT_R22 = 22,
 116    TARGET_PT_R23 = 23,
 117    TARGET_PT_R24 = 24,
 118    TARGET_PT_R25 = 25,
 119    TARGET_PT_R26 = 26,
 120    TARGET_PT_R27 = 27,
 121    TARGET_PT_R28 = 28,
 122    TARGET_PT_R29 = 29,
 123    TARGET_PT_R30 = 30,
 124    TARGET_PT_R31 = 31,
 125    TARGET_PT_NIP = 32,
 126    TARGET_PT_MSR = 33,
 127    TARGET_PT_ORIG_R3 = 34,
 128    TARGET_PT_CTR = 35,
 129    TARGET_PT_LNK = 36,
 130    TARGET_PT_XER = 37,
 131    TARGET_PT_CCR = 38,
 132    /* Yes, there are two registers with #39.  One is 64-bit only.  */
 133    TARGET_PT_MQ = 39,
 134    TARGET_PT_SOFTE = 39,
 135    TARGET_PT_TRAP = 40,
 136    TARGET_PT_DAR = 41,
 137    TARGET_PT_DSISR = 42,
 138    TARGET_PT_RESULT = 43,
 139    TARGET_PT_REGS_COUNT = 44
 140};
 141
 142
 143struct target_ucontext {
 144    target_ulong tuc_flags;
 145    target_ulong tuc_link;    /* ucontext_t __user * */
 146    struct target_sigaltstack tuc_stack;
 147#if !defined(TARGET_PPC64)
 148    int32_t tuc_pad[7];
 149    target_ulong tuc_regs;    /* struct mcontext __user *
 150                                points to uc_mcontext field */
 151#endif
 152    target_sigset_t tuc_sigmask;
 153#if defined(TARGET_PPC64)
 154    target_sigset_t unused[15]; /* Allow for uc_sigmask growth */
 155    struct target_sigcontext tuc_sigcontext;
 156#else
 157    int32_t tuc_maskext[30];
 158    int32_t tuc_pad2[3];
 159    struct target_mcontext tuc_mcontext;
 160#endif
 161};
 162
 163/* See arch/powerpc/kernel/signal_32.c.  */
 164struct target_sigframe {
 165    struct target_sigcontext sctx;
 166    struct target_mcontext mctx;
 167    int32_t abigap[56];
 168};
 169
 170#if defined(TARGET_PPC64)
 171
 172#define TARGET_TRAMP_SIZE 6
 173
 174struct target_rt_sigframe {
 175    /* sys_rt_sigreturn requires the ucontext be the first field */
 176    struct target_ucontext uc;
 177    target_ulong  _unused[2];
 178    uint32_t trampoline[TARGET_TRAMP_SIZE];
 179    target_ulong pinfo; /* struct siginfo __user * */
 180    target_ulong puc; /* void __user * */
 181    struct target_siginfo info;
 182    /* 64 bit ABI allows for 288 bytes below sp before decrementing it. */
 183    char abigap[288];
 184} __attribute__((aligned(16)));
 185
 186#else
 187
 188struct target_rt_sigframe {
 189    struct target_siginfo info;
 190    struct target_ucontext uc;
 191    int32_t abigap[56];
 192};
 193
 194#endif
 195
 196#if defined(TARGET_PPC64)
 197
 198struct target_func_ptr {
 199    target_ulong entry;
 200    target_ulong toc;
 201};
 202
 203#endif
 204
 205/* We use the mc_pad field for the signal return trampoline.  */
 206#define tramp mc_pad
 207
 208/* See arch/powerpc/kernel/signal.c.  */
 209static target_ulong get_sigframe(struct target_sigaction *ka,
 210                                 CPUPPCState *env,
 211                                 int frame_size)
 212{
 213    target_ulong oldsp;
 214
 215    oldsp = target_sigsp(get_sp_from_cpustate(env), ka);
 216
 217    return (oldsp - frame_size) & ~0xFUL;
 218}
 219
 220#if ((defined(TARGET_WORDS_BIGENDIAN) && defined(HOST_WORDS_BIGENDIAN)) || \
 221     (!defined(HOST_WORDS_BIGENDIAN) && !defined(TARGET_WORDS_BIGENDIAN)))
 222#define PPC_VEC_HI      0
 223#define PPC_VEC_LO      1
 224#else
 225#define PPC_VEC_HI      1
 226#define PPC_VEC_LO      0
 227#endif
 228
 229
 230static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame)
 231{
 232    target_ulong msr = env->msr;
 233    int i;
 234    target_ulong ccr = 0;
 235
 236    /* In general, the kernel attempts to be intelligent about what it
 237       needs to save for Altivec/FP/SPE registers.  We don't care that
 238       much, so we just go ahead and save everything.  */
 239
 240    /* Save general registers.  */
 241    for (i = 0; i < ARRAY_SIZE(env->gpr); i++) {
 242        __put_user(env->gpr[i], &frame->mc_gregs[i]);
 243    }
 244    __put_user(env->nip, &frame->mc_gregs[TARGET_PT_NIP]);
 245    __put_user(env->ctr, &frame->mc_gregs[TARGET_PT_CTR]);
 246    __put_user(env->lr, &frame->mc_gregs[TARGET_PT_LNK]);
 247    __put_user(env->xer, &frame->mc_gregs[TARGET_PT_XER]);
 248
 249    for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
 250        ccr |= env->crf[i] << (32 - ((i + 1) * 4));
 251    }
 252    __put_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]);
 253
 254    /* Save Altivec registers if necessary.  */
 255    if (env->insns_flags & PPC_ALTIVEC) {
 256        uint32_t *vrsave;
 257        for (i = 0; i < 32; i++) {
 258            ppc_avr_t *avr = cpu_avr_ptr(env, i);
 259            ppc_avr_t *vreg = (ppc_avr_t *)&frame->mc_vregs.altivec[i];
 260
 261            __put_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]);
 262            __put_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]);
 263        }
 264        /* Set MSR_VR in the saved MSR value to indicate that
 265           frame->mc_vregs contains valid data.  */
 266        msr |= MSR_VR;
 267#if defined(TARGET_PPC64)
 268        vrsave = (uint32_t *)&frame->mc_vregs.altivec[33];
 269        /* 64-bit needs to put a pointer to the vectors in the frame */
 270        __put_user(h2g(frame->mc_vregs.altivec), &frame->v_regs);
 271#else
 272        vrsave = (uint32_t *)&frame->mc_vregs.altivec[32];
 273#endif
 274        __put_user((uint32_t)env->spr[SPR_VRSAVE], vrsave);
 275    }
 276
 277#if defined(TARGET_PPC64)
 278    /* Save VSX second halves */
 279    if (env->insns_flags2 & PPC2_VSX) {
 280        uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34];
 281        for (i = 0; i < 32; i++) {
 282            uint64_t *vsrl = cpu_vsrl_ptr(env, i);
 283            __put_user(*vsrl, &vsregs[i]);
 284        }
 285    }
 286#endif
 287
 288    /* Save floating point registers.  */
 289    if (env->insns_flags & PPC_FLOAT) {
 290        for (i = 0; i < 32; i++) {
 291            uint64_t *fpr = cpu_fpr_ptr(env, i);
 292            __put_user(*fpr, &frame->mc_fregs[i]);
 293        }
 294        __put_user((uint64_t) env->fpscr, &frame->mc_fregs[32]);
 295    }
 296
 297#if !defined(TARGET_PPC64)
 298    /* Save SPE registers.  The kernel only saves the high half.  */
 299    if (env->insns_flags & PPC_SPE) {
 300        for (i = 0; i < ARRAY_SIZE(env->gprh); i++) {
 301            __put_user(env->gprh[i], &frame->mc_vregs.spe[i]);
 302        }
 303        /* Set MSR_SPE in the saved MSR value to indicate that
 304           frame->mc_vregs contains valid data.  */
 305        msr |= MSR_SPE;
 306        __put_user(env->spe_fscr, &frame->mc_vregs.spe[32]);
 307    }
 308#endif
 309
 310    /* Store MSR.  */
 311    __put_user(msr, &frame->mc_gregs[TARGET_PT_MSR]);
 312}
 313
 314static void encode_trampoline(int sigret, uint32_t *tramp)
 315{
 316    /* Set up the sigreturn trampoline: li r0,sigret; sc.  */
 317    if (sigret) {
 318        __put_user(0x38000000 | sigret, &tramp[0]);
 319        __put_user(0x44000002, &tramp[1]);
 320    }
 321}
 322
 323static void restore_user_regs(CPUPPCState *env,
 324                              struct target_mcontext *frame, int sig)
 325{
 326    target_ulong save_r2 = 0;
 327    target_ulong msr;
 328    target_ulong ccr;
 329
 330    int i;
 331
 332    if (!sig) {
 333        save_r2 = env->gpr[2];
 334    }
 335
 336    /* Restore general registers.  */
 337    for (i = 0; i < ARRAY_SIZE(env->gpr); i++) {
 338        __get_user(env->gpr[i], &frame->mc_gregs[i]);
 339    }
 340    __get_user(env->nip, &frame->mc_gregs[TARGET_PT_NIP]);
 341    __get_user(env->ctr, &frame->mc_gregs[TARGET_PT_CTR]);
 342    __get_user(env->lr, &frame->mc_gregs[TARGET_PT_LNK]);
 343    __get_user(env->xer, &frame->mc_gregs[TARGET_PT_XER]);
 344    __get_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]);
 345
 346    for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
 347        env->crf[i] = (ccr >> (32 - ((i + 1) * 4))) & 0xf;
 348    }
 349
 350    if (!sig) {
 351        env->gpr[2] = save_r2;
 352    }
 353    /* Restore MSR.  */
 354    __get_user(msr, &frame->mc_gregs[TARGET_PT_MSR]);
 355
 356    /* If doing signal return, restore the previous little-endian mode.  */
 357    if (sig)
 358        env->msr = (env->msr & ~(1ull << MSR_LE)) | (msr & (1ull << MSR_LE));
 359
 360    /* Restore Altivec registers if necessary.  */
 361    if (env->insns_flags & PPC_ALTIVEC) {
 362        ppc_avr_t *v_regs;
 363        uint32_t *vrsave;
 364#if defined(TARGET_PPC64)
 365        uint64_t v_addr;
 366        /* 64-bit needs to recover the pointer to the vectors from the frame */
 367        __get_user(v_addr, &frame->v_regs);
 368        v_regs = g2h(v_addr);
 369#else
 370        v_regs = (ppc_avr_t *)frame->mc_vregs.altivec;
 371#endif
 372        for (i = 0; i < 32; i++) {
 373            ppc_avr_t *avr = cpu_avr_ptr(env, i);
 374            ppc_avr_t *vreg = &v_regs[i];
 375
 376            __get_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]);
 377            __get_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]);
 378        }
 379        /* Set MSR_VEC in the saved MSR value to indicate that
 380           frame->mc_vregs contains valid data.  */
 381#if defined(TARGET_PPC64)
 382        vrsave = (uint32_t *)&v_regs[33];
 383#else
 384        vrsave = (uint32_t *)&v_regs[32];
 385#endif
 386        __get_user(env->spr[SPR_VRSAVE], vrsave);
 387    }
 388
 389#if defined(TARGET_PPC64)
 390    /* Restore VSX second halves */
 391    if (env->insns_flags2 & PPC2_VSX) {
 392        uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34];
 393        for (i = 0; i < 32; i++) {
 394            uint64_t *vsrl = cpu_vsrl_ptr(env, i);
 395            __get_user(*vsrl, &vsregs[i]);
 396        }
 397    }
 398#endif
 399
 400    /* Restore floating point registers.  */
 401    if (env->insns_flags & PPC_FLOAT) {
 402        uint64_t fpscr;
 403        for (i = 0; i < 32; i++) {
 404            uint64_t *fpr = cpu_fpr_ptr(env, i);
 405            __get_user(*fpr, &frame->mc_fregs[i]);
 406        }
 407        __get_user(fpscr, &frame->mc_fregs[32]);
 408        env->fpscr = (uint32_t) fpscr;
 409    }
 410
 411#if !defined(TARGET_PPC64)
 412    /* Save SPE registers.  The kernel only saves the high half.  */
 413    if (env->insns_flags & PPC_SPE) {
 414        for (i = 0; i < ARRAY_SIZE(env->gprh); i++) {
 415            __get_user(env->gprh[i], &frame->mc_vregs.spe[i]);
 416        }
 417        __get_user(env->spe_fscr, &frame->mc_vregs.spe[32]);
 418    }
 419#endif
 420}
 421
 422#if !defined(TARGET_PPC64)
 423void setup_frame(int sig, struct target_sigaction *ka,
 424                 target_sigset_t *set, CPUPPCState *env)
 425{
 426    struct target_sigframe *frame;
 427    struct target_sigcontext *sc;
 428    target_ulong frame_addr, newsp;
 429    int err = 0;
 430
 431    frame_addr = get_sigframe(ka, env, sizeof(*frame));
 432    trace_user_setup_frame(env, frame_addr);
 433    if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 1))
 434        goto sigsegv;
 435    sc = &frame->sctx;
 436
 437    __put_user(ka->_sa_handler, &sc->handler);
 438    __put_user(set->sig[0], &sc->oldmask);
 439    __put_user(set->sig[1], &sc->_unused[3]);
 440    __put_user(h2g(&frame->mctx), &sc->regs);
 441    __put_user(sig, &sc->signal);
 442
 443    /* Save user regs.  */
 444    save_user_regs(env, &frame->mctx);
 445
 446    /* Construct the trampoline code on the stack. */
 447    encode_trampoline(TARGET_NR_sigreturn, (uint32_t *)&frame->mctx.tramp);
 448
 449    /* The kernel checks for the presence of a VDSO here.  We don't
 450       emulate a vdso, so use a sigreturn system call.  */
 451    env->lr = (target_ulong) h2g(frame->mctx.tramp);
 452
 453    /* Turn off all fp exceptions.  */
 454    env->fpscr = 0;
 455
 456    /* Create a stack frame for the caller of the handler.  */
 457    newsp = frame_addr - SIGNAL_FRAMESIZE;
 458    err |= put_user(env->gpr[1], newsp, target_ulong);
 459
 460    if (err)
 461        goto sigsegv;
 462
 463    /* Set up registers for signal handler.  */
 464    env->gpr[1] = newsp;
 465    env->gpr[3] = sig;
 466    env->gpr[4] = frame_addr + offsetof(struct target_sigframe, sctx);
 467
 468    env->nip = (target_ulong) ka->_sa_handler;
 469
 470    /* Signal handlers are entered in big-endian mode.  */
 471    env->msr &= ~(1ull << MSR_LE);
 472
 473    unlock_user_struct(frame, frame_addr, 1);
 474    return;
 475
 476sigsegv:
 477    unlock_user_struct(frame, frame_addr, 1);
 478    force_sigsegv(sig);
 479}
 480#endif /* !defined(TARGET_PPC64) */
 481
 482void setup_rt_frame(int sig, struct target_sigaction *ka,
 483                    target_siginfo_t *info,
 484                    target_sigset_t *set, CPUPPCState *env)
 485{
 486    struct target_rt_sigframe *rt_sf;
 487    uint32_t *trampptr = 0;
 488    struct target_mcontext *mctx = 0;
 489    target_ulong rt_sf_addr, newsp = 0;
 490    int i, err = 0;
 491#if defined(TARGET_PPC64)
 492    struct target_sigcontext *sc = 0;
 493#if !defined(TARGET_ABI32)
 494    struct image_info *image = ((TaskState *)thread_cpu->opaque)->info;
 495#endif
 496#endif
 497
 498    rt_sf_addr = get_sigframe(ka, env, sizeof(*rt_sf));
 499    if (!lock_user_struct(VERIFY_WRITE, rt_sf, rt_sf_addr, 1))
 500        goto sigsegv;
 501
 502    tswap_siginfo(&rt_sf->info, info);
 503
 504    __put_user(0, &rt_sf->uc.tuc_flags);
 505    __put_user(0, &rt_sf->uc.tuc_link);
 506    target_save_altstack(&rt_sf->uc.tuc_stack, env);
 507#if !defined(TARGET_PPC64)
 508    __put_user(h2g (&rt_sf->uc.tuc_mcontext),
 509               &rt_sf->uc.tuc_regs);
 510#endif
 511    for(i = 0; i < TARGET_NSIG_WORDS; i++) {
 512        __put_user(set->sig[i], &rt_sf->uc.tuc_sigmask.sig[i]);
 513    }
 514
 515#if defined(TARGET_PPC64)
 516    mctx = &rt_sf->uc.tuc_sigcontext.mcontext;
 517    trampptr = &rt_sf->trampoline[0];
 518
 519    sc = &rt_sf->uc.tuc_sigcontext;
 520    __put_user(h2g(mctx), &sc->regs);
 521    __put_user(sig, &sc->signal);
 522#else
 523    mctx = &rt_sf->uc.tuc_mcontext;
 524    trampptr = (uint32_t *)&rt_sf->uc.tuc_mcontext.tramp;
 525#endif
 526
 527    save_user_regs(env, mctx);
 528    encode_trampoline(TARGET_NR_rt_sigreturn, trampptr);
 529
 530    /* The kernel checks for the presence of a VDSO here.  We don't
 531       emulate a vdso, so use a sigreturn system call.  */
 532    env->lr = (target_ulong) h2g(trampptr);
 533
 534    /* Turn off all fp exceptions.  */
 535    env->fpscr = 0;
 536
 537    /* Create a stack frame for the caller of the handler.  */
 538    newsp = rt_sf_addr - (SIGNAL_FRAMESIZE + 16);
 539    err |= put_user(env->gpr[1], newsp, target_ulong);
 540
 541    if (err)
 542        goto sigsegv;
 543
 544    /* Set up registers for signal handler.  */
 545    env->gpr[1] = newsp;
 546    env->gpr[3] = (target_ulong) sig;
 547    env->gpr[4] = (target_ulong) h2g(&rt_sf->info);
 548    env->gpr[5] = (target_ulong) h2g(&rt_sf->uc);
 549    env->gpr[6] = (target_ulong) h2g(rt_sf);
 550
 551#if defined(TARGET_PPC64) && !defined(TARGET_ABI32)
 552    if (get_ppc64_abi(image) < 2) {
 553        /* ELFv1 PPC64 function pointers are pointers to OPD entries. */
 554        struct target_func_ptr *handler =
 555            (struct target_func_ptr *)g2h(ka->_sa_handler);
 556        env->nip = tswapl(handler->entry);
 557        env->gpr[2] = tswapl(handler->toc);
 558    } else {
 559        /* ELFv2 PPC64 function pointers are entry points. R12 must also be set. */
 560        env->gpr[12] = env->nip = ka->_sa_handler;
 561    }
 562#else
 563    env->nip = (target_ulong) ka->_sa_handler;
 564#endif
 565
 566    /* Signal handlers are entered in big-endian mode.  */
 567    env->msr &= ~(1ull << MSR_LE);
 568
 569    unlock_user_struct(rt_sf, rt_sf_addr, 1);
 570    return;
 571
 572sigsegv:
 573    unlock_user_struct(rt_sf, rt_sf_addr, 1);
 574    force_sigsegv(sig);
 575
 576}
 577
 578#if !defined(TARGET_PPC64) || defined(TARGET_ABI32)
 579long do_sigreturn(CPUPPCState *env)
 580{
 581    struct target_sigcontext *sc = NULL;
 582    struct target_mcontext *sr = NULL;
 583    target_ulong sr_addr = 0, sc_addr;
 584    sigset_t blocked;
 585    target_sigset_t set;
 586
 587    sc_addr = env->gpr[1] + SIGNAL_FRAMESIZE;
 588    if (!lock_user_struct(VERIFY_READ, sc, sc_addr, 1))
 589        goto sigsegv;
 590
 591#if defined(TARGET_PPC64)
 592    set.sig[0] = sc->oldmask + ((uint64_t)(sc->_unused[3]) << 32);
 593#else
 594    __get_user(set.sig[0], &sc->oldmask);
 595    __get_user(set.sig[1], &sc->_unused[3]);
 596#endif
 597    target_to_host_sigset_internal(&blocked, &set);
 598    set_sigmask(&blocked);
 599
 600    __get_user(sr_addr, &sc->regs);
 601    if (!lock_user_struct(VERIFY_READ, sr, sr_addr, 1))
 602        goto sigsegv;
 603    restore_user_regs(env, sr, 1);
 604
 605    unlock_user_struct(sr, sr_addr, 1);
 606    unlock_user_struct(sc, sc_addr, 1);
 607    return -TARGET_QEMU_ESIGRETURN;
 608
 609sigsegv:
 610    unlock_user_struct(sr, sr_addr, 1);
 611    unlock_user_struct(sc, sc_addr, 1);
 612    force_sig(TARGET_SIGSEGV);
 613    return -TARGET_QEMU_ESIGRETURN;
 614}
 615#endif /* !defined(TARGET_PPC64) */
 616
 617/* See arch/powerpc/kernel/signal_32.c.  */
 618static int do_setcontext(struct target_ucontext *ucp, CPUPPCState *env, int sig)
 619{
 620    struct target_mcontext *mcp;
 621    target_ulong mcp_addr;
 622    sigset_t blocked;
 623    target_sigset_t set;
 624
 625    if (copy_from_user(&set, h2g(ucp) + offsetof(struct target_ucontext, tuc_sigmask),
 626                       sizeof (set)))
 627        return 1;
 628
 629#if defined(TARGET_PPC64)
 630    mcp_addr = h2g(ucp) +
 631        offsetof(struct target_ucontext, tuc_sigcontext.mcontext);
 632#else
 633    __get_user(mcp_addr, &ucp->tuc_regs);
 634#endif
 635
 636    if (!lock_user_struct(VERIFY_READ, mcp, mcp_addr, 1))
 637        return 1;
 638
 639    target_to_host_sigset_internal(&blocked, &set);
 640    set_sigmask(&blocked);
 641    restore_user_regs(env, mcp, sig);
 642
 643    unlock_user_struct(mcp, mcp_addr, 1);
 644    return 0;
 645}
 646
 647long do_rt_sigreturn(CPUPPCState *env)
 648{
 649    struct target_rt_sigframe *rt_sf = NULL;
 650    target_ulong rt_sf_addr;
 651
 652    rt_sf_addr = env->gpr[1] + SIGNAL_FRAMESIZE + 16;
 653    if (!lock_user_struct(VERIFY_READ, rt_sf, rt_sf_addr, 1))
 654        goto sigsegv;
 655
 656    if (do_setcontext(&rt_sf->uc, env, 1))
 657        goto sigsegv;
 658
 659    do_sigaltstack(rt_sf_addr
 660                   + offsetof(struct target_rt_sigframe, uc.tuc_stack),
 661                   0, env->gpr[1]);
 662
 663    unlock_user_struct(rt_sf, rt_sf_addr, 1);
 664    return -TARGET_QEMU_ESIGRETURN;
 665
 666sigsegv:
 667    unlock_user_struct(rt_sf, rt_sf_addr, 1);
 668    force_sig(TARGET_SIGSEGV);
 669    return -TARGET_QEMU_ESIGRETURN;
 670}
 671
 672/* This syscall implements {get,set,swap}context for userland.  */
 673abi_long do_swapcontext(CPUArchState *env, abi_ulong uold_ctx,
 674                        abi_ulong unew_ctx, abi_long ctx_size)
 675{
 676    struct target_ucontext *uctx;
 677    struct target_mcontext *mctx;
 678
 679    /* For ppc32, ctx_size is "reserved for future use".
 680     * For ppc64, we do not yet support the VSX extension.
 681     */
 682    if (ctx_size < sizeof(struct target_ucontext)) {
 683        return -TARGET_EINVAL;
 684    }
 685
 686    if (uold_ctx) {
 687        TaskState *ts = (TaskState *)thread_cpu->opaque;
 688
 689        if (!lock_user_struct(VERIFY_WRITE, uctx, uold_ctx, 1)) {
 690            return -TARGET_EFAULT;
 691        }
 692
 693#ifdef TARGET_PPC64
 694        mctx = &uctx->tuc_sigcontext.mcontext;
 695#else
 696        /* ??? The kernel aligns the pointer down here into padding, but
 697         * in setup_rt_frame we don't.  Be self-compatible for now.
 698         */
 699        mctx = &uctx->tuc_mcontext;
 700        __put_user(h2g(mctx), &uctx->tuc_regs);
 701#endif
 702
 703        save_user_regs(env, mctx);
 704        host_to_target_sigset(&uctx->tuc_sigmask, &ts->signal_mask);
 705
 706        unlock_user_struct(uctx, uold_ctx, 1);
 707    }
 708
 709    if (unew_ctx) {
 710        int err;
 711
 712        if (!lock_user_struct(VERIFY_READ, uctx, unew_ctx, 1)) {
 713            return -TARGET_EFAULT;
 714        }
 715        err = do_setcontext(uctx, env, 0);
 716        unlock_user_struct(uctx, unew_ctx, 1);
 717
 718        if (err) {
 719            /* We cannot return to a partially updated context.  */
 720            force_sig(TARGET_SIGSEGV);
 721        }
 722        return -TARGET_QEMU_ESIGRETURN;
 723    }
 724
 725    return 0;
 726}
 727