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20#ifndef TARGET_MICROBLAZE_MMU_H
21#define TARGET_MICROBLAZE_MMU_H
22
23#define MMU_R_PID 0
24#define MMU_R_ZPR 1
25#define MMU_R_TLBX 2
26#define MMU_R_TLBLO 3
27#define MMU_R_TLBHI 4
28#define MMU_R_TLBSX 5
29
30#define RAM_DATA 1
31#define RAM_TAG 0
32
33
34#define TLB_EPN_MASK MAKE_64BIT_MASK(10, 64 - 10)
35#define TLB_PAGESZ_MASK 0x00000380
36#define TLB_PAGESZ(x) (((x) & 0x7) << 7)
37#define PAGESZ_1K 0
38#define PAGESZ_4K 1
39#define PAGESZ_16K 2
40#define PAGESZ_64K 3
41#define PAGESZ_256K 4
42#define PAGESZ_1M 5
43#define PAGESZ_4M 6
44#define PAGESZ_16M 7
45#define TLB_VALID 0x00000040
46
47
48#define TLB_RPN_MASK MAKE_64BIT_MASK(10, 64 - 10)
49#define TLB_PERM_MASK 0x00000300
50#define TLB_EX 0x00000200
51#define TLB_WR 0x00000100
52#define TLB_ZSEL_MASK 0x000000F0
53#define TLB_ZSEL(x) (((x) & 0xF) << 4)
54#define TLB_ATTR_MASK 0x0000000F
55#define TLB_W 0x00000008
56#define TLB_I 0x00000004
57#define TLB_M 0x00000002
58#define TLB_G 0x00000001
59
60
61#define R_TBLX_MISS_SHIFT 31
62#define R_TBLX_MISS_MASK (1U << R_TBLX_MISS_SHIFT)
63
64#define TLB_ENTRIES 64
65
66struct microblaze_mmu
67{
68
69 uint64_t rams[2][TLB_ENTRIES];
70
71 uint8_t tids[TLB_ENTRIES];
72
73 uint32_t regs[3];
74
75 int c_mmu;
76 int c_mmu_tlb_access;
77 int c_mmu_zones;
78 uint64_t c_addr_mask;
79};
80
81struct microblaze_mmu_lookup
82{
83 uint32_t paddr;
84 uint32_t vaddr;
85 unsigned int size;
86 unsigned int idx;
87 int prot;
88 enum {
89 ERR_PROT, ERR_MISS, ERR_HIT
90 } err;
91};
92
93unsigned int mmu_translate(struct microblaze_mmu *mmu,
94 struct microblaze_mmu_lookup *lu,
95 target_ulong vaddr, int rw, int mmu_idx);
96uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
97void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
98void mmu_init(struct microblaze_mmu *mmu);
99
100#endif
101