LXR qemu/target/ppc/translate

   1/*
   2 *  PowerPC CPU initialization for qemu.
   3 *
   4 *  Copyright (c) 2003-2007 Jocelyn Mayer
   5 *  Copyright 2011 Freescale Semiconductor, Inc.
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "disas/dis-asm.h"
  22#include "exec/gdbstub.h"
  23#include "kvm_ppc.h"
  24#include "sysemu/arch_init.h"
  25#include "sysemu/cpus.h"
  26#include "sysemu/hw_accel.h"
  27#include "sysemu/tcg.h"
  28#include "cpu-models.h"
  29#include "mmu-hash32.h"
  30#include "mmu-hash64.h"
  31#include "qemu/error-report.h"
  32#include "qemu/module.h"
  33#include "qemu/qemu-print.h"
  34#include "qapi/error.h"
  35#include "qapi/qmp/qnull.h"
  36#include "qapi/visitor.h"
  37#include "hw/qdev-properties.h"
  38#include "hw/ppc/ppc.h"
  39#include "mmu-book3s-v3.h"
  40#include "sysemu/qtest.h"
  41#include "qemu/cutils.h"
  42#include "disas/capstone.h"
  43#include "fpu/softfloat.h"
  44#include "qapi/qapi-commands-machine-target.h"
  45
  46/* #define PPC_DUMP_CPU */
  47/* #define PPC_DEBUG_SPR */
  48/* #define PPC_DUMP_SPR_ACCESSES */
  49/* #define USE_APPLE_GDB */
  50
  51/*
  52 * Generic callbacks:
  53 * do nothing but store/retrieve spr value
  54 */
  55static void spr_load_dump_spr(int sprn)
  56{
  57#ifdef PPC_DUMP_SPR_ACCESSES
  58    TCGv_i32 t0 = tcg_const_i32(sprn);
  59    gen_helper_load_dump_spr(cpu_env, t0);
  60    tcg_temp_free_i32(t0);
  61#endif
  62}
  63
  64static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
  65{
  66    gen_load_spr(cpu_gpr[gprn], sprn);
  67    spr_load_dump_spr(sprn);
  68}
  69
  70static void spr_store_dump_spr(int sprn)
  71{
  72#ifdef PPC_DUMP_SPR_ACCESSES
  73    TCGv_i32 t0 = tcg_const_i32(sprn);
  74    gen_helper_store_dump_spr(cpu_env, t0);
  75    tcg_temp_free_i32(t0);
  76#endif
  77}
  78
  79static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
  80{
  81    gen_store_spr(sprn, cpu_gpr[gprn]);
  82    spr_store_dump_spr(sprn);
  83}
  84
  85#if !defined(CONFIG_USER_ONLY)
  86static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
  87{
  88#ifdef TARGET_PPC64
  89    TCGv t0 = tcg_temp_new();
  90    tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
  91    gen_store_spr(sprn, t0);
  92    tcg_temp_free(t0);
  93    spr_store_dump_spr(sprn);
  94#else
  95    spr_write_generic(ctx, sprn, gprn);
  96#endif
  97}
  98
  99static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
 100{
 101    TCGv t0 = tcg_temp_new();
 102    TCGv t1 = tcg_temp_new();
 103    gen_load_spr(t0, sprn);
 104    tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
 105    tcg_gen_and_tl(t0, t0, t1);
 106    gen_store_spr(sprn, t0);
 107    tcg_temp_free(t0);
 108    tcg_temp_free(t1);
 109}
 110
 111static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
 112{
 113}
 114
 115#endif
 116
 117/* SPR common to all PowerPC */
 118/* XER */
 119static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
 120{
 121    gen_read_xer(ctx, cpu_gpr[gprn]);
 122}
 123
 124static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
 125{
 126    gen_write_xer(cpu_gpr[gprn]);
 127}
 128
 129/* LR */
 130static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
 131{
 132    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
 133}
 134
 135static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
 136{
 137    tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
 138}
 139
 140/* CFAR */
 141#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
 142static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
 143{
 144    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
 145}
 146
 147static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
 148{
 149    tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
 150}
 151#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
 152
 153/* CTR */
 154static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
 155{
 156    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
 157}
 158
 159static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
 160{
 161    tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
 162}
 163
 164/* User read access to SPR */
 165/* USPRx */
 166/* UMMCRx */
 167/* UPMCx */
 168/* USIA */
 169/* UDECR */
 170static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
 171{
 172    gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
 173}
 174
 175#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
 176static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
 177{
 178    gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
 179}
 180#endif
 181
 182/* SPR common to all non-embedded PowerPC */
 183/* DECR */
 184#if !defined(CONFIG_USER_ONLY)
 185static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
 186{
 187    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 188        gen_io_start();
 189    }
 190    gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
 191    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 192        gen_stop_exception(ctx);
 193    }
 194}
 195
 196static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
 197{
 198    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 199        gen_io_start();
 200    }
 201    gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
 202    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 203        gen_stop_exception(ctx);
 204    }
 205}
 206#endif
 207
 208/* SPR common to all non-embedded PowerPC, except 601 */
 209/* Time base */
 210static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
 211{
 212    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 213        gen_io_start();
 214    }
 215    gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
 216    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 217        gen_io_end();
 218        gen_stop_exception(ctx);
 219    }
 220}
 221
 222static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
 223{
 224    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 225        gen_io_start();
 226    }
 227    gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
 228    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 229        gen_io_end();
 230        gen_stop_exception(ctx);
 231    }
 232}
 233
 234ATTRIBUTE_UNUSED
 235static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
 236{
 237    gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
 238}
 239
 240ATTRIBUTE_UNUSED
 241static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
 242{
 243    gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
 244}
 245
 246#if !defined(CONFIG_USER_ONLY)
 247static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
 248{
 249    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 250        gen_io_start();
 251    }
 252    gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
 253    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 254        gen_io_end();
 255        gen_stop_exception(ctx);
 256    }
 257}
 258
 259static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
 260{
 261    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 262        gen_io_start();
 263    }
 264    gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
 265    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 266        gen_io_end();
 267        gen_stop_exception(ctx);
 268    }
 269}
 270
 271ATTRIBUTE_UNUSED
 272static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
 273{
 274    gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
 275}
 276
 277ATTRIBUTE_UNUSED
 278static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
 279{
 280    gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
 281}
 282
 283#if defined(TARGET_PPC64)
 284ATTRIBUTE_UNUSED
 285static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
 286{
 287    gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
 288}
 289
 290static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
 291{
 292    gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
 293}
 294
 295/* HDECR */
 296static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
 297{
 298    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 299        gen_io_start();
 300    }
 301    gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
 302    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 303        gen_io_end();
 304        gen_stop_exception(ctx);
 305    }
 306}
 307
 308static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
 309{
 310    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 311        gen_io_start();
 312    }
 313    gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
 314    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
 315        gen_io_end();
 316        gen_stop_exception(ctx);
 317    }
 318}
 319
 320static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
 321{
 322    gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
 323}
 324
 325static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
 326{
 327    gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
 328}
 329
 330static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
 331{
 332    gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
 333}
 334
 335#endif
 336#endif
 337
 338#if !defined(CONFIG_USER_ONLY)
 339/* IBAT0U...IBAT0U */
 340/* IBAT0L...IBAT7L */
 341static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
 342{
 343    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 344                  offsetof(CPUPPCState,
 345                           IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 346}
 347
 348static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
 349{
 350    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 351                  offsetof(CPUPPCState,
 352                           IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
 353}
 354
 355static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
 356{
 357    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 358    gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
 359    tcg_temp_free_i32(t0);
 360}
 361
 362static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
 363{
 364    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
 365    gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
 366    tcg_temp_free_i32(t0);
 367}
 368
 369static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
 370{
 371    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
 372    gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
 373    tcg_temp_free_i32(t0);
 374}
 375
 376static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
 377{
 378    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
 379    gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
 380    tcg_temp_free_i32(t0);
 381}
 382
 383/* DBAT0U...DBAT7U */
 384/* DBAT0L...DBAT7L */
 385static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
 386{
 387    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 388                  offsetof(CPUPPCState,
 389                           DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
 390}
 391
 392static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
 393{
 394    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 395                  offsetof(CPUPPCState,
 396                           DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
 397}
 398
 399static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
 400{
 401    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
 402    gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
 403    tcg_temp_free_i32(t0);
 404}
 405
 406static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
 407{
 408    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
 409    gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
 410    tcg_temp_free_i32(t0);
 411}
 412
 413static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
 414{
 415    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
 416    gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
 417    tcg_temp_free_i32(t0);
 418}
 419
 420static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
 421{
 422    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
 423    gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
 424    tcg_temp_free_i32(t0);
 425}
 426
 427/* SDR1 */
 428static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
 429{
 430    gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
 431}
 432
 433#if defined(TARGET_PPC64)
 434/* 64 bits PowerPC specific SPRs */
 435/* PIDR */
 436static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
 437{
 438    gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
 439}
 440
 441static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
 442{
 443    gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
 444}
 445
 446static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
 447{
 448    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
 449}
 450
 451static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
 452{
 453    TCGv t0 = tcg_temp_new();
 454    tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
 455    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
 456    tcg_temp_free(t0);
 457}
 458static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
 459{
 460    gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
 461}
 462
 463static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
 464{
 465    gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
 466}
 467
 468/* DPDES */
 469static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
 470{
 471    gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
 472}
 473
 474static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
 475{
 476    gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
 477}
 478#endif
 479#endif
 480
 481/* PowerPC 601 specific registers */
 482/* RTC */
 483static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
 484{
 485    gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
 486}
 487
 488static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
 489{
 490    gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
 491}
 492
 493#if !defined(CONFIG_USER_ONLY)
 494static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
 495{
 496    gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
 497}
 498
 499static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
 500{
 501    gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
 502}
 503
 504static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
 505{
 506    gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
 507    /* Must stop the translation as endianness may have changed */
 508    gen_stop_exception(ctx);
 509}
 510#endif
 511
 512/* Unified bats */
 513#if !defined(CONFIG_USER_ONLY)
 514static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
 515{
 516    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 517                  offsetof(CPUPPCState,
 518                           IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 519}
 520
 521static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
 522{
 523    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 524    gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
 525    tcg_temp_free_i32(t0);
 526}
 527
 528static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
 529{
 530    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 531    gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
 532    tcg_temp_free_i32(t0);
 533}
 534#endif
 535
 536/* PowerPC 40x specific registers */
 537#if !defined(CONFIG_USER_ONLY)
 538static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
 539{
 540    gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
 541}
 542
 543static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
 544{
 545    gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
 546}
 547
 548static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
 549{
 550    gen_store_spr(sprn, cpu_gpr[gprn]);
 551    gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
 552    /* We must stop translation as we may have rebooted */
 553    gen_stop_exception(ctx);
 554}
 555
 556static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
 557{
 558    gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
 559}
 560
 561static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
 562{
 563    gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
 564}
 565
 566static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
 567{
 568    gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
 569}
 570#endif
 571
 572/* PowerPC 403 specific registers */
 573/* PBL1 / PBU1 / PBL2 / PBU2 */
 574#if !defined(CONFIG_USER_ONLY)
 575static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
 576{
 577    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
 578                  offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
 579}
 580
 581static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
 582{
 583    TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
 584    gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
 585    tcg_temp_free_i32(t0);
 586}
 587
 588static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
 589{
 590    TCGv t0 = tcg_temp_new();
 591    tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
 592    gen_store_spr(SPR_PIR, t0);
 593    tcg_temp_free(t0);
 594}
 595#endif
 596
 597/* SPE specific registers */
 598static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
 599{
 600    TCGv_i32 t0 = tcg_temp_new_i32();
 601    tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
 602    tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
 603    tcg_temp_free_i32(t0);
 604}
 605
 606static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
 607{
 608    TCGv_i32 t0 = tcg_temp_new_i32();
 609    tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
 610    tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
 611    tcg_temp_free_i32(t0);
 612}
 613
 614#if !defined(CONFIG_USER_ONLY)
 615/* Callback used to write the exception vector base */
 616static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
 617{
 618    TCGv t0 = tcg_temp_new();
 619    tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
 620    tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 621    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
 622    gen_store_spr(sprn, t0);
 623    tcg_temp_free(t0);
 624}
 625
 626static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
 627{
 628    int sprn_offs;
 629
 630    if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
 631        sprn_offs = sprn - SPR_BOOKE_IVOR0;
 632    } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
 633        sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
 634    } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
 635        sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
 636    } else {
 637        printf("Trying to write an unknown exception vector %d %03x\n",
 638               sprn, sprn);
 639        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
 640        return;
 641    }
 642
 643    TCGv t0 = tcg_temp_new();
 644    tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
 645    tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 646    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
 647    gen_store_spr(sprn, t0);
 648    tcg_temp_free(t0);
 649}
 650#endif
 651
 652static inline void vscr_init(CPUPPCState *env, uint32_t val)
 653{
 654    /* Altivec always uses round-to-nearest */
 655    set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
 656    helper_mtvscr(env, val);
 657}
 658
 659#ifdef CONFIG_USER_ONLY
 660#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
 661                         oea_read, oea_write, one_reg_id, initial_value)       \
 662    _spr_register(env, num, name, uea_read, uea_write, initial_value)
 663#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
 664                            oea_read, oea_write, hea_read, hea_write,          \
 665                            one_reg_id, initial_value)                         \
 666    _spr_register(env, num, name, uea_read, uea_write, initial_value)
 667#else
 668#if !defined(CONFIG_KVM)
 669#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
 670                         oea_read, oea_write, one_reg_id, initial_value)       \
 671    _spr_register(env, num, name, uea_read, uea_write,                         \
 672                  oea_read, oea_write, oea_read, oea_write, initial_value)
 673#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
 674                            oea_read, oea_write, hea_read, hea_write,          \
 675                            one_reg_id, initial_value)                         \
 676    _spr_register(env, num, name, uea_read, uea_write,                         \
 677                  oea_read, oea_write, hea_read, hea_write, initial_value)
 678#else
 679#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
 680                         oea_read, oea_write, one_reg_id, initial_value)       \
 681    _spr_register(env, num, name, uea_read, uea_write,                         \
 682                  oea_read, oea_write, oea_read, oea_write,                    \
 683                  one_reg_id, initial_value)
 684#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
 685                            oea_read, oea_write, hea_read, hea_write,          \
 686                            one_reg_id, initial_value)                         \
 687    _spr_register(env, num, name, uea_read, uea_write,                         \
 688                  oea_read, oea_write, hea_read, hea_write,                    \
 689                  one_reg_id, initial_value)
 690#endif
 691#endif
 692
 693#define spr_register(env, num, name, uea_read, uea_write,                      \
 694                     oea_read, oea_write, initial_value)                       \
 695    spr_register_kvm(env, num, name, uea_read, uea_write,                      \
 696                     oea_read, oea_write, 0, initial_value)
 697
 698#define spr_register_hv(env, num, name, uea_read, uea_write,                   \
 699                        oea_read, oea_write, hea_read, hea_write,              \
 700                        initial_value)                                         \
 701    spr_register_kvm_hv(env, num, name, uea_read, uea_write,                   \
 702                        oea_read, oea_write, hea_read, hea_write,              \
 703                        0, initial_value)
 704
 705static inline void _spr_register(CPUPPCState *env, int num,
 706                                 const char *name,
 707                                 void (*uea_read)(DisasContext *ctx,
 708                                                  int gprn, int sprn),
 709                                 void (*uea_write)(DisasContext *ctx,
 710                                                   int sprn, int gprn),
 711#if !defined(CONFIG_USER_ONLY)
 712
 713                                 void (*oea_read)(DisasContext *ctx,
 714                                                  int gprn, int sprn),
 715                                 void (*oea_write)(DisasContext *ctx,
 716                                                   int sprn, int gprn),
 717                                 void (*hea_read)(DisasContext *opaque,
 718                                                  int gprn, int sprn),
 719                                 void (*hea_write)(DisasContext *opaque,
 720                                                   int sprn, int gprn),
 721#endif
 722#if defined(CONFIG_KVM)
 723                                 uint64_t one_reg_id,
 724#endif
 725                                 target_ulong initial_value)
 726{
 727    ppc_spr_t *spr;
 728
 729    spr = &env->spr_cb[num];
 730    if (spr->name != NULL || env->spr[num] != 0x00000000 ||
 731#if !defined(CONFIG_USER_ONLY)
 732        spr->oea_read != NULL || spr->oea_write != NULL ||
 733#endif
 734        spr->uea_read != NULL || spr->uea_write != NULL) {
 735        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
 736        exit(1);
 737    }
 738#if defined(PPC_DEBUG_SPR)
 739    printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
 740           name, initial_value);
 741#endif
 742    spr->name = name;
 743    spr->uea_read = uea_read;
 744    spr->uea_write = uea_write;
 745#if !defined(CONFIG_USER_ONLY)
 746    spr->oea_read = oea_read;
 747    spr->oea_write = oea_write;
 748    spr->hea_read = hea_read;
 749    spr->hea_write = hea_write;
 750#endif
 751#if defined(CONFIG_KVM)
 752    spr->one_reg_id = one_reg_id,
 753#endif
 754    env->spr[num] = spr->default_value = initial_value;
 755}
 756
 757/* Generic PowerPC SPRs */
 758static void gen_spr_generic(CPUPPCState *env)
 759{
 760    /* Integer processing */
 761    spr_register(env, SPR_XER, "XER",
 762                 &spr_read_xer, &spr_write_xer,
 763                 &spr_read_xer, &spr_write_xer,
 764                 0x00000000);
 765    /* Branch contol */
 766    spr_register(env, SPR_LR, "LR",
 767                 &spr_read_lr, &spr_write_lr,
 768                 &spr_read_lr, &spr_write_lr,
 769                 0x00000000);
 770    spr_register(env, SPR_CTR, "CTR",
 771                 &spr_read_ctr, &spr_write_ctr,
 772                 &spr_read_ctr, &spr_write_ctr,
 773                 0x00000000);
 774    /* Interrupt processing */
 775    spr_register(env, SPR_SRR0, "SRR0",
 776                 SPR_NOACCESS, SPR_NOACCESS,
 777                 &spr_read_generic, &spr_write_generic,
 778                 0x00000000);
 779    spr_register(env, SPR_SRR1, "SRR1",
 780                 SPR_NOACCESS, SPR_NOACCESS,
 781                 &spr_read_generic, &spr_write_generic,
 782                 0x00000000);
 783    /* Processor control */
 784    spr_register(env, SPR_SPRG0, "SPRG0",
 785                 SPR_NOACCESS, SPR_NOACCESS,
 786                 &spr_read_generic, &spr_write_generic,
 787                 0x00000000);
 788    spr_register(env, SPR_SPRG1, "SPRG1",
 789                 SPR_NOACCESS, SPR_NOACCESS,
 790                 &spr_read_generic, &spr_write_generic,
 791                 0x00000000);
 792    spr_register(env, SPR_SPRG2, "SPRG2",
 793                 SPR_NOACCESS, SPR_NOACCESS,
 794                 &spr_read_generic, &spr_write_generic,
 795                 0x00000000);
 796    spr_register(env, SPR_SPRG3, "SPRG3",
 797                 SPR_NOACCESS, SPR_NOACCESS,
 798                 &spr_read_generic, &spr_write_generic,
 799                 0x00000000);
 800}
 801
 802/* SPR common to all non-embedded PowerPC, including 601 */
 803static void gen_spr_ne_601(CPUPPCState *env)
 804{
 805    /* Exception processing */
 806    spr_register_kvm(env, SPR_DSISR, "DSISR",
 807                     SPR_NOACCESS, SPR_NOACCESS,
 808                     &spr_read_generic, &spr_write_generic,
 809                     KVM_REG_PPC_DSISR, 0x00000000);
 810    spr_register_kvm(env, SPR_DAR, "DAR",
 811                     SPR_NOACCESS, SPR_NOACCESS,
 812                     &spr_read_generic, &spr_write_generic,
 813                     KVM_REG_PPC_DAR, 0x00000000);
 814    /* Timer */
 815    spr_register(env, SPR_DECR, "DECR",
 816                 SPR_NOACCESS, SPR_NOACCESS,
 817                 &spr_read_decr, &spr_write_decr,
 818                 0x00000000);
 819}
 820
 821/* Storage Description Register 1 */
 822static void gen_spr_sdr1(CPUPPCState *env)
 823{
 824#ifndef CONFIG_USER_ONLY
 825    if (env->has_hv_mode) {
 826        /*
 827         * SDR1 is a hypervisor resource on CPUs which have a
 828         * hypervisor mode
 829         */
 830        spr_register_hv(env, SPR_SDR1, "SDR1",
 831                        SPR_NOACCESS, SPR_NOACCESS,
 832                        SPR_NOACCESS, SPR_NOACCESS,
 833                        &spr_read_generic, &spr_write_sdr1,
 834                        0x00000000);
 835    } else {
 836        spr_register(env, SPR_SDR1, "SDR1",
 837                     SPR_NOACCESS, SPR_NOACCESS,
 838                     &spr_read_generic, &spr_write_sdr1,
 839                     0x00000000);
 840    }
 841#endif
 842}
 843
 844/* BATs 0-3 */
 845static void gen_low_BATs(CPUPPCState *env)
 846{
 847#if !defined(CONFIG_USER_ONLY)
 848    spr_register(env, SPR_IBAT0U, "IBAT0U",
 849                 SPR_NOACCESS, SPR_NOACCESS,
 850                 &spr_read_ibat, &spr_write_ibatu,
 851                 0x00000000);
 852    spr_register(env, SPR_IBAT0L, "IBAT0L",
 853                 SPR_NOACCESS, SPR_NOACCESS,
 854                 &spr_read_ibat, &spr_write_ibatl,
 855                 0x00000000);
 856    spr_register(env, SPR_IBAT1U, "IBAT1U",
 857                 SPR_NOACCESS, SPR_NOACCESS,
 858                 &spr_read_ibat, &spr_write_ibatu,
 859                 0x00000000);
 860    spr_register(env, SPR_IBAT1L, "IBAT1L",
 861                 SPR_NOACCESS, SPR_NOACCESS,
 862                 &spr_read_ibat, &spr_write_ibatl,
 863                 0x00000000);
 864    spr_register(env, SPR_IBAT2U, "IBAT2U",
 865                 SPR_NOACCESS, SPR_NOACCESS,
 866                 &spr_read_ibat, &spr_write_ibatu,
 867                 0x00000000);
 868    spr_register(env, SPR_IBAT2L, "IBAT2L",
 869                 SPR_NOACCESS, SPR_NOACCESS,
 870                 &spr_read_ibat, &spr_write_ibatl,
 871                 0x00000000);
 872    spr_register(env, SPR_IBAT3U, "IBAT3U",
 873                 SPR_NOACCESS, SPR_NOACCESS,
 874                 &spr_read_ibat, &spr_write_ibatu,
 875                 0x00000000);
 876    spr_register(env, SPR_IBAT3L, "IBAT3L",
 877                 SPR_NOACCESS, SPR_NOACCESS,
 878                 &spr_read_ibat, &spr_write_ibatl,
 879                 0x00000000);
 880    spr_register(env, SPR_DBAT0U, "DBAT0U",
 881                 SPR_NOACCESS, SPR_NOACCESS,
 882                 &spr_read_dbat, &spr_write_dbatu,
 883                 0x00000000);
 884    spr_register(env, SPR_DBAT0L, "DBAT0L",
 885                 SPR_NOACCESS, SPR_NOACCESS,
 886                 &spr_read_dbat, &spr_write_dbatl,
 887                 0x00000000);
 888    spr_register(env, SPR_DBAT1U, "DBAT1U",
 889                 SPR_NOACCESS, SPR_NOACCESS,
 890                 &spr_read_dbat, &spr_write_dbatu,
 891                 0x00000000);
 892    spr_register(env, SPR_DBAT1L, "DBAT1L",
 893                 SPR_NOACCESS, SPR_NOACCESS,
 894                 &spr_read_dbat, &spr_write_dbatl,
 895                 0x00000000);
 896    spr_register(env, SPR_DBAT2U, "DBAT2U",
 897                 SPR_NOACCESS, SPR_NOACCESS,
 898                 &spr_read_dbat, &spr_write_dbatu,
 899                 0x00000000);
 900    spr_register(env, SPR_DBAT2L, "DBAT2L",
 901                 SPR_NOACCESS, SPR_NOACCESS,
 902                 &spr_read_dbat, &spr_write_dbatl,
 903                 0x00000000);
 904    spr_register(env, SPR_DBAT3U, "DBAT3U",
 905                 SPR_NOACCESS, SPR_NOACCESS,
 906                 &spr_read_dbat, &spr_write_dbatu,
 907                 0x00000000);
 908    spr_register(env, SPR_DBAT3L, "DBAT3L",
 909                 SPR_NOACCESS, SPR_NOACCESS,
 910                 &spr_read_dbat, &spr_write_dbatl,
 911                 0x00000000);
 912    env->nb_BATs += 4;
 913#endif
 914}
 915
 916/* BATs 4-7 */
 917static void gen_high_BATs(CPUPPCState *env)
 918{
 919#if !defined(CONFIG_USER_ONLY)
 920    spr_register(env, SPR_IBAT4U, "IBAT4U",
 921                 SPR_NOACCESS, SPR_NOACCESS,
 922                 &spr_read_ibat_h, &spr_write_ibatu_h,
 923                 0x00000000);
 924    spr_register(env, SPR_IBAT4L, "IBAT4L",
 925                 SPR_NOACCESS, SPR_NOACCESS,
 926                 &spr_read_ibat_h, &spr_write_ibatl_h,
 927                 0x00000000);
 928    spr_register(env, SPR_IBAT5U, "IBAT5U",
 929                 SPR_NOACCESS, SPR_NOACCESS,
 930                 &spr_read_ibat_h, &spr_write_ibatu_h,
 931                 0x00000000);
 932    spr_register(env, SPR_IBAT5L, "IBAT5L",
 933                 SPR_NOACCESS, SPR_NOACCESS,
 934                 &spr_read_ibat_h, &spr_write_ibatl_h,
 935                 0x00000000);
 936    spr_register(env, SPR_IBAT6U, "IBAT6U",
 937                 SPR_NOACCESS, SPR_NOACCESS,
 938                 &spr_read_ibat_h, &spr_write_ibatu_h,
 939                 0x00000000);
 940    spr_register(env, SPR_IBAT6L, "IBAT6L",
 941                 SPR_NOACCESS, SPR_NOACCESS,
 942                 &spr_read_ibat_h, &spr_write_ibatl_h,
 943                 0x00000000);
 944    spr_register(env, SPR_IBAT7U, "IBAT7U",
 945                 SPR_NOACCESS, SPR_NOACCESS,
 946                 &spr_read_ibat_h, &spr_write_ibatu_h,
 947                 0x00000000);
 948    spr_register(env, SPR_IBAT7L, "IBAT7L",
 949                 SPR_NOACCESS, SPR_NOACCESS,
 950                 &spr_read_ibat_h, &spr_write_ibatl_h,
 951                 0x00000000);
 952    spr_register(env, SPR_DBAT4U, "DBAT4U",
 953                 SPR_NOACCESS, SPR_NOACCESS,
 954                 &spr_read_dbat_h, &spr_write_dbatu_h,
 955                 0x00000000);
 956    spr_register(env, SPR_DBAT4L, "DBAT4L",
 957                 SPR_NOACCESS, SPR_NOACCESS,
 958                 &spr_read_dbat_h, &spr_write_dbatl_h,
 959                 0x00000000);
 960    spr_register(env, SPR_DBAT5U, "DBAT5U",
 961                 SPR_NOACCESS, SPR_NOACCESS,
 962                 &spr_read_dbat_h, &spr_write_dbatu_h,
 963                 0x00000000);
 964    spr_register(env, SPR_DBAT5L, "DBAT5L",
 965                 SPR_NOACCESS, SPR_NOACCESS,
 966                 &spr_read_dbat_h, &spr_write_dbatl_h,
 967                 0x00000000);
 968    spr_register(env, SPR_DBAT6U, "DBAT6U",
 969                 SPR_NOACCESS, SPR_NOACCESS,
 970                 &spr_read_dbat_h, &spr_write_dbatu_h,
 971                 0x00000000);
 972    spr_register(env, SPR_DBAT6L, "DBAT6L",
 973                 SPR_NOACCESS, SPR_NOACCESS,
 974                 &spr_read_dbat_h, &spr_write_dbatl_h,
 975                 0x00000000);
 976    spr_register(env, SPR_DBAT7U, "DBAT7U",
 977                 SPR_NOACCESS, SPR_NOACCESS,
 978                 &spr_read_dbat_h, &spr_write_dbatu_h,
 979                 0x00000000);
 980    spr_register(env, SPR_DBAT7L, "DBAT7L",
 981                 SPR_NOACCESS, SPR_NOACCESS,
 982                 &spr_read_dbat_h, &spr_write_dbatl_h,
 983                 0x00000000);
 984    env->nb_BATs += 4;
 985#endif
 986}
 987
 988/* Generic PowerPC time base */
 989static void gen_tbl(CPUPPCState *env)
 990{
 991    spr_register(env, SPR_VTBL,  "TBL",
 992                 &spr_read_tbl, SPR_NOACCESS,
 993                 &spr_read_tbl, SPR_NOACCESS,
 994                 0x00000000);
 995    spr_register(env, SPR_TBL,   "TBL",
 996                 &spr_read_tbl, SPR_NOACCESS,
 997                 &spr_read_tbl, &spr_write_tbl,
 998                 0x00000000);
 999    spr_register(env, SPR_VTBU,  "TBU",
1000                 &spr_read_tbu, SPR_NOACCESS,

1001                 &spr_read_tbu, SPR_NOACCESS,
1002                 0x00000000);
1003    spr_register(env, SPR_TBU,   "TBU",
1004                 &spr_read_tbu, SPR_NOACCESS,
1005                 &spr_read_tbu, &spr_write_tbu,
1006                 0x00000000);
1007}
1008
1009/* Softare table search registers */
1010static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
1011{
1012#if !defined(CONFIG_USER_ONLY)
1013    env->nb_tlb = nb_tlbs;
1014    env->nb_ways = nb_ways;
1015    env->id_tlbs = 1;
1016    env->tlb_type = TLB_6XX;
1017    spr_register(env, SPR_DMISS, "DMISS",
1018                 SPR_NOACCESS, SPR_NOACCESS,
1019                 &spr_read_generic, SPR_NOACCESS,
1020                 0x00000000);
1021    spr_register(env, SPR_DCMP, "DCMP",
1022                 SPR_NOACCESS, SPR_NOACCESS,
1023                 &spr_read_generic, SPR_NOACCESS,
1024                 0x00000000);
1025    spr_register(env, SPR_HASH1, "HASH1",
1026                 SPR_NOACCESS, SPR_NOACCESS,
1027                 &spr_read_generic, SPR_NOACCESS,
1028                 0x00000000);
1029    spr_register(env, SPR_HASH2, "HASH2",
1030                 SPR_NOACCESS, SPR_NOACCESS,
1031                 &spr_read_generic, SPR_NOACCESS,
1032                 0x00000000);
1033    spr_register(env, SPR_IMISS, "IMISS",
1034                 SPR_NOACCESS, SPR_NOACCESS,
1035                 &spr_read_generic, SPR_NOACCESS,
1036                 0x00000000);
1037    spr_register(env, SPR_ICMP, "ICMP",
1038                 SPR_NOACCESS, SPR_NOACCESS,
1039                 &spr_read_generic, SPR_NOACCESS,
1040                 0x00000000);
1041    spr_register(env, SPR_RPA, "RPA",
1042                 SPR_NOACCESS, SPR_NOACCESS,
1043                 &spr_read_generic, &spr_write_generic,
1044                 0x00000000);
1045#endif
1046}
1047
1048/* SPR common to MPC755 and G2 */
1049static void gen_spr_G2_755(CPUPPCState *env)
1050{
1051    /* SGPRs */
1052    spr_register(env, SPR_SPRG4, "SPRG4",
1053                 SPR_NOACCESS, SPR_NOACCESS,
1054                 &spr_read_generic, &spr_write_generic,
1055                 0x00000000);
1056    spr_register(env, SPR_SPRG5, "SPRG5",
1057                 SPR_NOACCESS, SPR_NOACCESS,
1058                 &spr_read_generic, &spr_write_generic,
1059                 0x00000000);
1060    spr_register(env, SPR_SPRG6, "SPRG6",
1061                 SPR_NOACCESS, SPR_NOACCESS,
1062                 &spr_read_generic, &spr_write_generic,
1063                 0x00000000);
1064    spr_register(env, SPR_SPRG7, "SPRG7",
1065                 SPR_NOACCESS, SPR_NOACCESS,
1066                 &spr_read_generic, &spr_write_generic,
1067                 0x00000000);
1068}
1069
1070/* SPR common to all 7xx PowerPC implementations */
1071static void gen_spr_7xx(CPUPPCState *env)
1072{
1073    /* Breakpoints */
1074    /* XXX : not implemented */
1075    spr_register_kvm(env, SPR_DABR, "DABR",
1076                     SPR_NOACCESS, SPR_NOACCESS,
1077                     &spr_read_generic, &spr_write_generic,
1078                     KVM_REG_PPC_DABR, 0x00000000);
1079    /* XXX : not implemented */
1080    spr_register(env, SPR_IABR, "IABR",
1081                 SPR_NOACCESS, SPR_NOACCESS,
1082                 &spr_read_generic, &spr_write_generic,
1083                 0x00000000);
1084    /* Cache management */
1085    /* XXX : not implemented */
1086    spr_register(env, SPR_ICTC, "ICTC",
1087                 SPR_NOACCESS, SPR_NOACCESS,
1088                 &spr_read_generic, &spr_write_generic,
1089                 0x00000000);
1090    /* Performance monitors */
1091    /* XXX : not implemented */
1092    spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1093                 SPR_NOACCESS, SPR_NOACCESS,
1094                 &spr_read_generic, &spr_write_generic,
1095                 0x00000000);
1096    /* XXX : not implemented */
1097    spr_register(env, SPR_7XX_MMCR1, "MMCR1",
1098                 SPR_NOACCESS, SPR_NOACCESS,
1099                 &spr_read_generic, &spr_write_generic,
1100                 0x00000000);
1101    /* XXX : not implemented */
1102    spr_register(env, SPR_7XX_PMC1, "PMC1",
1103                 SPR_NOACCESS, SPR_NOACCESS,
1104                 &spr_read_generic, &spr_write_generic,
1105                 0x00000000);
1106    /* XXX : not implemented */
1107    spr_register(env, SPR_7XX_PMC2, "PMC2",
1108                 SPR_NOACCESS, SPR_NOACCESS,
1109                 &spr_read_generic, &spr_write_generic,
1110                 0x00000000);
1111    /* XXX : not implemented */
1112    spr_register(env, SPR_7XX_PMC3, "PMC3",
1113                 SPR_NOACCESS, SPR_NOACCESS,
1114                 &spr_read_generic, &spr_write_generic,
1115                 0x00000000);
1116    /* XXX : not implemented */
1117    spr_register(env, SPR_7XX_PMC4, "PMC4",
1118                 SPR_NOACCESS, SPR_NOACCESS,
1119                 &spr_read_generic, &spr_write_generic,
1120                 0x00000000);
1121    /* XXX : not implemented */
1122    spr_register(env, SPR_7XX_SIAR, "SIAR",
1123                 SPR_NOACCESS, SPR_NOACCESS,
1124                 &spr_read_generic, SPR_NOACCESS,
1125                 0x00000000);
1126    /* XXX : not implemented */
1127    spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1128                 &spr_read_ureg, SPR_NOACCESS,
1129                 &spr_read_ureg, SPR_NOACCESS,
1130                 0x00000000);
1131    /* XXX : not implemented */
1132    spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1133                 &spr_read_ureg, SPR_NOACCESS,
1134                 &spr_read_ureg, SPR_NOACCESS,
1135                 0x00000000);
1136    /* XXX : not implemented */
1137    spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1138                 &spr_read_ureg, SPR_NOACCESS,
1139                 &spr_read_ureg, SPR_NOACCESS,
1140                 0x00000000);
1141    /* XXX : not implemented */
1142    spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1143                 &spr_read_ureg, SPR_NOACCESS,
1144                 &spr_read_ureg, SPR_NOACCESS,
1145                 0x00000000);
1146    /* XXX : not implemented */
1147    spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1148                 &spr_read_ureg, SPR_NOACCESS,
1149                 &spr_read_ureg, SPR_NOACCESS,
1150                 0x00000000);
1151    /* XXX : not implemented */
1152    spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1153                 &spr_read_ureg, SPR_NOACCESS,
1154                 &spr_read_ureg, SPR_NOACCESS,
1155                 0x00000000);
1156    /* XXX : not implemented */
1157    spr_register(env, SPR_7XX_USIAR, "USIAR",
1158                 &spr_read_ureg, SPR_NOACCESS,
1159                 &spr_read_ureg, SPR_NOACCESS,
1160                 0x00000000);
1161    /* External access control */
1162    /* XXX : not implemented */
1163    spr_register(env, SPR_EAR, "EAR",
1164                 SPR_NOACCESS, SPR_NOACCESS,
1165                 &spr_read_generic, &spr_write_generic,
1166                 0x00000000);
1167}
1168
1169#ifdef TARGET_PPC64
1170#ifndef CONFIG_USER_ONLY
1171static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1172{
1173    TCGv t0 = tcg_temp_new();
1174    TCGv t1 = tcg_temp_new();
1175    TCGv t2 = tcg_temp_new();
1176
1177    /*
1178     * Note, the HV=1 PR=0 case is handled earlier by simply using
1179     * spr_write_generic for HV mode in the SPR table
1180     */
1181
1182    /* Build insertion mask into t1 based on context */
1183    if (ctx->pr) {
1184        gen_load_spr(t1, SPR_UAMOR);
1185    } else {
1186        gen_load_spr(t1, SPR_AMOR);
1187    }
1188
1189    /* Mask new bits into t2 */
1190    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1191
1192    /* Load AMR and clear new bits in t0 */
1193    gen_load_spr(t0, SPR_AMR);
1194    tcg_gen_andc_tl(t0, t0, t1);
1195
1196    /* Or'in new bits and write it out */
1197    tcg_gen_or_tl(t0, t0, t2);
1198    gen_store_spr(SPR_AMR, t0);
1199    spr_store_dump_spr(SPR_AMR);
1200
1201    tcg_temp_free(t0);
1202    tcg_temp_free(t1);
1203    tcg_temp_free(t2);
1204}
1205
1206static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1207{
1208    TCGv t0 = tcg_temp_new();
1209    TCGv t1 = tcg_temp_new();
1210    TCGv t2 = tcg_temp_new();
1211
1212    /*
1213     * Note, the HV=1 case is handled earlier by simply using
1214     * spr_write_generic for HV mode in the SPR table
1215     */
1216
1217    /* Build insertion mask into t1 based on context */
1218    gen_load_spr(t1, SPR_AMOR);
1219
1220    /* Mask new bits into t2 */
1221    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1222
1223    /* Load AMR and clear new bits in t0 */
1224    gen_load_spr(t0, SPR_UAMOR);
1225    tcg_gen_andc_tl(t0, t0, t1);
1226
1227    /* Or'in new bits and write it out */
1228    tcg_gen_or_tl(t0, t0, t2);
1229    gen_store_spr(SPR_UAMOR, t0);
1230    spr_store_dump_spr(SPR_UAMOR);
1231
1232    tcg_temp_free(t0);
1233    tcg_temp_free(t1);
1234    tcg_temp_free(t2);
1235}
1236
1237static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1238{
1239    TCGv t0 = tcg_temp_new();
1240    TCGv t1 = tcg_temp_new();
1241    TCGv t2 = tcg_temp_new();
1242
1243    /*
1244     * Note, the HV=1 case is handled earlier by simply using
1245     * spr_write_generic for HV mode in the SPR table
1246     */
1247
1248    /* Build insertion mask into t1 based on context */
1249    gen_load_spr(t1, SPR_AMOR);
1250
1251    /* Mask new bits into t2 */
1252    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1253
1254    /* Load AMR and clear new bits in t0 */
1255    gen_load_spr(t0, SPR_IAMR);
1256    tcg_gen_andc_tl(t0, t0, t1);
1257
1258    /* Or'in new bits and write it out */
1259    tcg_gen_or_tl(t0, t0, t2);
1260    gen_store_spr(SPR_IAMR, t0);
1261    spr_store_dump_spr(SPR_IAMR);
1262
1263    tcg_temp_free(t0);
1264    tcg_temp_free(t1);
1265    tcg_temp_free(t2);
1266}
1267#endif /* CONFIG_USER_ONLY */
1268
1269static void gen_spr_amr(CPUPPCState *env)
1270{
1271#ifndef CONFIG_USER_ONLY
1272    /*
1273     * Virtual Page Class Key protection
1274     *
1275     * The AMR is accessible either via SPR 13 or SPR 29.  13 is
1276     * userspace accessible, 29 is privileged.  So we only need to set
1277     * the kvm ONE_REG id on one of them, we use 29
1278     */
1279    spr_register(env, SPR_UAMR, "UAMR",
1280                 &spr_read_generic, &spr_write_amr,
1281                 &spr_read_generic, &spr_write_amr,
1282                 0);
1283    spr_register_kvm_hv(env, SPR_AMR, "AMR",
1284                     SPR_NOACCESS, SPR_NOACCESS,
1285                     &spr_read_generic, &spr_write_amr,
1286                     &spr_read_generic, &spr_write_generic,
1287                     KVM_REG_PPC_AMR, 0);
1288    spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1289                     SPR_NOACCESS, SPR_NOACCESS,
1290                     &spr_read_generic, &spr_write_uamor,
1291                     &spr_read_generic, &spr_write_generic,
1292                     KVM_REG_PPC_UAMOR, 0);
1293    spr_register_hv(env, SPR_AMOR, "AMOR",
1294                    SPR_NOACCESS, SPR_NOACCESS,
1295                    SPR_NOACCESS, SPR_NOACCESS,
1296                    &spr_read_generic, &spr_write_generic,
1297                    0);
1298#endif /* !CONFIG_USER_ONLY */
1299}
1300
1301static void gen_spr_iamr(CPUPPCState *env)
1302{
1303#ifndef CONFIG_USER_ONLY
1304    spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1305                        SPR_NOACCESS, SPR_NOACCESS,
1306                        &spr_read_generic, &spr_write_iamr,
1307                        &spr_read_generic, &spr_write_generic,
1308                        KVM_REG_PPC_IAMR, 0);
1309#endif /* !CONFIG_USER_ONLY */
1310}
1311#endif /* TARGET_PPC64 */
1312
1313#ifndef CONFIG_USER_ONLY
1314static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1315{
1316    gen_helper_fixup_thrm(cpu_env);
1317    gen_load_spr(cpu_gpr[gprn], sprn);
1318    spr_load_dump_spr(sprn);
1319}
1320#endif /* !CONFIG_USER_ONLY */
1321
1322static void gen_spr_thrm(CPUPPCState *env)
1323{
1324    /* Thermal management */
1325    /* XXX : not implemented */
1326    spr_register(env, SPR_THRM1, "THRM1",
1327                 SPR_NOACCESS, SPR_NOACCESS,
1328                 &spr_read_thrm, &spr_write_generic,
1329                 0x00000000);
1330    /* XXX : not implemented */
1331    spr_register(env, SPR_THRM2, "THRM2",
1332                 SPR_NOACCESS, SPR_NOACCESS,
1333                 &spr_read_thrm, &spr_write_generic,
1334                 0x00000000);
1335    /* XXX : not implemented */
1336    spr_register(env, SPR_THRM3, "THRM3",
1337                 SPR_NOACCESS, SPR_NOACCESS,
1338                 &spr_read_thrm, &spr_write_generic,
1339                 0x00000000);
1340}
1341
1342/* SPR specific to PowerPC 604 implementation */
1343static void gen_spr_604(CPUPPCState *env)
1344{
1345    /* Processor identification */
1346    spr_register(env, SPR_PIR, "PIR",
1347                 SPR_NOACCESS, SPR_NOACCESS,
1348                 &spr_read_generic, &spr_write_pir,
1349                 0x00000000);
1350    /* Breakpoints */
1351    /* XXX : not implemented */
1352    spr_register(env, SPR_IABR, "IABR",
1353                 SPR_NOACCESS, SPR_NOACCESS,
1354                 &spr_read_generic, &spr_write_generic,
1355                 0x00000000);
1356    /* XXX : not implemented */
1357    spr_register_kvm(env, SPR_DABR, "DABR",
1358                     SPR_NOACCESS, SPR_NOACCESS,
1359                     &spr_read_generic, &spr_write_generic,
1360                     KVM_REG_PPC_DABR, 0x00000000);
1361    /* Performance counters */
1362    /* XXX : not implemented */
1363    spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1364                 SPR_NOACCESS, SPR_NOACCESS,
1365                 &spr_read_generic, &spr_write_generic,
1366                 0x00000000);
1367    /* XXX : not implemented */
1368    spr_register(env, SPR_7XX_PMC1, "PMC1",
1369                 SPR_NOACCESS, SPR_NOACCESS,
1370                 &spr_read_generic, &spr_write_generic,
1371                 0x00000000);
1372    /* XXX : not implemented */
1373    spr_register(env, SPR_7XX_PMC2, "PMC2",
1374                 SPR_NOACCESS, SPR_NOACCESS,
1375                 &spr_read_generic, &spr_write_generic,
1376                 0x00000000);
1377    /* XXX : not implemented */
1378    spr_register(env, SPR_7XX_SIAR, "SIAR",
1379                 SPR_NOACCESS, SPR_NOACCESS,
1380                 &spr_read_generic, SPR_NOACCESS,
1381                 0x00000000);
1382    /* XXX : not implemented */
1383    spr_register(env, SPR_SDA, "SDA",
1384                 SPR_NOACCESS, SPR_NOACCESS,
1385                 &spr_read_generic, SPR_NOACCESS,
1386                 0x00000000);
1387    /* External access control */
1388    /* XXX : not implemented */
1389    spr_register(env, SPR_EAR, "EAR",
1390                 SPR_NOACCESS, SPR_NOACCESS,
1391                 &spr_read_generic, &spr_write_generic,
1392                 0x00000000);
1393}
1394
1395/* SPR specific to PowerPC 603 implementation */
1396static void gen_spr_603(CPUPPCState *env)
1397{
1398    /* External access control */
1399    /* XXX : not implemented */
1400    spr_register(env, SPR_EAR, "EAR",
1401                 SPR_NOACCESS, SPR_NOACCESS,
1402                 &spr_read_generic, &spr_write_generic,
1403                 0x00000000);
1404    /* Breakpoints */
1405    /* XXX : not implemented */
1406    spr_register(env, SPR_IABR, "IABR",
1407                 SPR_NOACCESS, SPR_NOACCESS,
1408                 &spr_read_generic, &spr_write_generic,
1409                 0x00000000);
1410
1411}
1412
1413/* SPR specific to PowerPC G2 implementation */
1414static void gen_spr_G2(CPUPPCState *env)
1415{
1416    /* Memory base address */
1417    /* MBAR */
1418    /* XXX : not implemented */
1419    spr_register(env, SPR_MBAR, "MBAR",
1420                 SPR_NOACCESS, SPR_NOACCESS,
1421                 &spr_read_generic, &spr_write_generic,
1422                 0x00000000);
1423    /* Exception processing */
1424    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1425                 SPR_NOACCESS, SPR_NOACCESS,
1426                 &spr_read_generic, &spr_write_generic,
1427                 0x00000000);
1428    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1429                 SPR_NOACCESS, SPR_NOACCESS,
1430                 &spr_read_generic, &spr_write_generic,
1431                 0x00000000);
1432    /* Breakpoints */
1433    /* XXX : not implemented */
1434    spr_register(env, SPR_DABR, "DABR",
1435                 SPR_NOACCESS, SPR_NOACCESS,
1436                 &spr_read_generic, &spr_write_generic,
1437                 0x00000000);
1438    /* XXX : not implemented */
1439    spr_register(env, SPR_DABR2, "DABR2",
1440                 SPR_NOACCESS, SPR_NOACCESS,
1441                 &spr_read_generic, &spr_write_generic,
1442                 0x00000000);
1443    /* XXX : not implemented */
1444    spr_register(env, SPR_IABR, "IABR",
1445                 SPR_NOACCESS, SPR_NOACCESS,
1446                 &spr_read_generic, &spr_write_generic,
1447                 0x00000000);
1448    /* XXX : not implemented */
1449    spr_register(env, SPR_IABR2, "IABR2",
1450                 SPR_NOACCESS, SPR_NOACCESS,
1451                 &spr_read_generic, &spr_write_generic,
1452                 0x00000000);
1453    /* XXX : not implemented */
1454    spr_register(env, SPR_IBCR, "IBCR",
1455                 SPR_NOACCESS, SPR_NOACCESS,
1456                 &spr_read_generic, &spr_write_generic,
1457                 0x00000000);
1458    /* XXX : not implemented */
1459    spr_register(env, SPR_DBCR, "DBCR",
1460                 SPR_NOACCESS, SPR_NOACCESS,
1461                 &spr_read_generic, &spr_write_generic,
1462                 0x00000000);
1463}
1464
1465/* SPR specific to PowerPC 602 implementation */
1466static void gen_spr_602(CPUPPCState *env)
1467{
1468    /* ESA registers */
1469    /* XXX : not implemented */
1470    spr_register(env, SPR_SER, "SER",
1471                 SPR_NOACCESS, SPR_NOACCESS,
1472                 &spr_read_generic, &spr_write_generic,
1473                 0x00000000);
1474    /* XXX : not implemented */
1475    spr_register(env, SPR_SEBR, "SEBR",
1476                 SPR_NOACCESS, SPR_NOACCESS,
1477                 &spr_read_generic, &spr_write_generic,
1478                 0x00000000);
1479    /* XXX : not implemented */
1480    spr_register(env, SPR_ESASRR, "ESASRR",
1481                 SPR_NOACCESS, SPR_NOACCESS,
1482                 &spr_read_generic, &spr_write_generic,
1483                 0x00000000);
1484    /* Floating point status */
1485    /* XXX : not implemented */
1486    spr_register(env, SPR_SP, "SP",
1487                 SPR_NOACCESS, SPR_NOACCESS,
1488                 &spr_read_generic, &spr_write_generic,
1489                 0x00000000);
1490    /* XXX : not implemented */
1491    spr_register(env, SPR_LT, "LT",
1492                 SPR_NOACCESS, SPR_NOACCESS,
1493                 &spr_read_generic, &spr_write_generic,
1494                 0x00000000);
1495    /* Watchdog timer */
1496    /* XXX : not implemented */
1497    spr_register(env, SPR_TCR, "TCR",
1498                 SPR_NOACCESS, SPR_NOACCESS,
1499                 &spr_read_generic, &spr_write_generic,
1500                 0x00000000);
1501    /* Interrupt base */
1502    spr_register(env, SPR_IBR, "IBR",
1503                 SPR_NOACCESS, SPR_NOACCESS,
1504                 &spr_read_generic, &spr_write_generic,
1505                 0x00000000);
1506    /* XXX : not implemented */
1507    spr_register(env, SPR_IABR, "IABR",
1508                 SPR_NOACCESS, SPR_NOACCESS,
1509                 &spr_read_generic, &spr_write_generic,
1510                 0x00000000);
1511}
1512
1513/* SPR specific to PowerPC 601 implementation */
1514static void gen_spr_601(CPUPPCState *env)
1515{
1516    /* Multiplication/division register */
1517    /* MQ */
1518    spr_register(env, SPR_MQ, "MQ",
1519                 &spr_read_generic, &spr_write_generic,
1520                 &spr_read_generic, &spr_write_generic,
1521                 0x00000000);
1522    /* RTC registers */
1523    spr_register(env, SPR_601_RTCU, "RTCU",
1524                 SPR_NOACCESS, SPR_NOACCESS,
1525                 SPR_NOACCESS, &spr_write_601_rtcu,
1526                 0x00000000);
1527    spr_register(env, SPR_601_VRTCU, "RTCU",
1528                 &spr_read_601_rtcu, SPR_NOACCESS,
1529                 &spr_read_601_rtcu, SPR_NOACCESS,
1530                 0x00000000);
1531    spr_register(env, SPR_601_RTCL, "RTCL",
1532                 SPR_NOACCESS, SPR_NOACCESS,
1533                 SPR_NOACCESS, &spr_write_601_rtcl,
1534                 0x00000000);
1535    spr_register(env, SPR_601_VRTCL, "RTCL",
1536                 &spr_read_601_rtcl, SPR_NOACCESS,
1537                 &spr_read_601_rtcl, SPR_NOACCESS,
1538                 0x00000000);
1539    /* Timer */
1540#if 0 /* ? */
1541    spr_register(env, SPR_601_UDECR, "UDECR",
1542                 &spr_read_decr, SPR_NOACCESS,
1543                 &spr_read_decr, SPR_NOACCESS,
1544                 0x00000000);
1545#endif
1546    /* External access control */
1547    /* XXX : not implemented */
1548    spr_register(env, SPR_EAR, "EAR",
1549                 SPR_NOACCESS, SPR_NOACCESS,
1550                 &spr_read_generic, &spr_write_generic,
1551                 0x00000000);
1552    /* Memory management */
1553#if !defined(CONFIG_USER_ONLY)
1554    spr_register(env, SPR_IBAT0U, "IBAT0U",
1555                 SPR_NOACCESS, SPR_NOACCESS,
1556                 &spr_read_601_ubat, &spr_write_601_ubatu,
1557                 0x00000000);
1558    spr_register(env, SPR_IBAT0L, "IBAT0L",
1559                 SPR_NOACCESS, SPR_NOACCESS,
1560                 &spr_read_601_ubat, &spr_write_601_ubatl,
1561                 0x00000000);
1562    spr_register(env, SPR_IBAT1U, "IBAT1U",
1563                 SPR_NOACCESS, SPR_NOACCESS,
1564                 &spr_read_601_ubat, &spr_write_601_ubatu,
1565                 0x00000000);
1566    spr_register(env, SPR_IBAT1L, "IBAT1L",
1567                 SPR_NOACCESS, SPR_NOACCESS,
1568                 &spr_read_601_ubat, &spr_write_601_ubatl,
1569                 0x00000000);
1570    spr_register(env, SPR_IBAT2U, "IBAT2U",
1571                 SPR_NOACCESS, SPR_NOACCESS,
1572                 &spr_read_601_ubat, &spr_write_601_ubatu,
1573                 0x00000000);
1574    spr_register(env, SPR_IBAT2L, "IBAT2L",
1575                 SPR_NOACCESS, SPR_NOACCESS,
1576                 &spr_read_601_ubat, &spr_write_601_ubatl,
1577                 0x00000000);
1578    spr_register(env, SPR_IBAT3U, "IBAT3U",
1579                 SPR_NOACCESS, SPR_NOACCESS,
1580                 &spr_read_601_ubat, &spr_write_601_ubatu,
1581                 0x00000000);
1582    spr_register(env, SPR_IBAT3L, "IBAT3L",
1583                 SPR_NOACCESS, SPR_NOACCESS,
1584                 &spr_read_601_ubat, &spr_write_601_ubatl,
1585                 0x00000000);
1586    env->nb_BATs = 4;
1587#endif
1588}
1589
1590static void gen_spr_74xx(CPUPPCState *env)
1591{
1592    /* Processor identification */
1593    spr_register(env, SPR_PIR, "PIR",
1594                 SPR_NOACCESS, SPR_NOACCESS,
1595                 &spr_read_generic, &spr_write_pir,
1596                 0x00000000);
1597    /* XXX : not implemented */
1598    spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1599                 SPR_NOACCESS, SPR_NOACCESS,
1600                 &spr_read_generic, &spr_write_generic,
1601                 0x00000000);
1602    /* XXX : not implemented */
1603    spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1604                 &spr_read_ureg, SPR_NOACCESS,
1605                 &spr_read_ureg, SPR_NOACCESS,
1606                 0x00000000);
1607    /* XXX: not implemented */
1608    spr_register(env, SPR_BAMR, "BAMR",
1609                 SPR_NOACCESS, SPR_NOACCESS,
1610                 &spr_read_generic, &spr_write_generic,
1611                 0x00000000);
1612    /* XXX : not implemented */
1613    spr_register(env, SPR_MSSCR0, "MSSCR0",
1614                 SPR_NOACCESS, SPR_NOACCESS,
1615                 &spr_read_generic, &spr_write_generic,
1616                 0x00000000);
1617    /* Hardware implementation registers */
1618    /* XXX : not implemented */
1619    spr_register(env, SPR_HID0, "HID0",
1620                 SPR_NOACCESS, SPR_NOACCESS,
1621                 &spr_read_generic, &spr_write_generic,
1622                 0x00000000);
1623    /* XXX : not implemented */
1624    spr_register(env, SPR_HID1, "HID1",
1625                 SPR_NOACCESS, SPR_NOACCESS,
1626                 &spr_read_generic, &spr_write_generic,
1627                 0x00000000);
1628    /* Altivec */
1629    spr_register(env, SPR_VRSAVE, "VRSAVE",
1630                 &spr_read_generic, &spr_write_generic,
1631                 &spr_read_generic, &spr_write_generic,
1632                 0x00000000);
1633    /* XXX : not implemented */
1634    spr_register(env, SPR_L2CR, "L2CR",
1635                 SPR_NOACCESS, SPR_NOACCESS,
1636                 &spr_read_generic, spr_access_nop,
1637                 0x00000000);
1638    /* Not strictly an SPR */
1639    vscr_init(env, 0x00010000);
1640}
1641
1642static void gen_l3_ctrl(CPUPPCState *env)
1643{
1644    /* L3CR */
1645    /* XXX : not implemented */
1646    spr_register(env, SPR_L3CR, "L3CR",
1647                 SPR_NOACCESS, SPR_NOACCESS,
1648                 &spr_read_generic, &spr_write_generic,
1649                 0x00000000);
1650    /* L3ITCR0 */
1651    /* XXX : not implemented */
1652    spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1653                 SPR_NOACCESS, SPR_NOACCESS,
1654                 &spr_read_generic, &spr_write_generic,
1655                 0x00000000);
1656    /* L3PM */
1657    /* XXX : not implemented */
1658    spr_register(env, SPR_L3PM, "L3PM",
1659                 SPR_NOACCESS, SPR_NOACCESS,
1660                 &spr_read_generic, &spr_write_generic,
1661                 0x00000000);
1662}
1663
1664static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
1665{
1666#if !defined(CONFIG_USER_ONLY)
1667    env->nb_tlb = nb_tlbs;
1668    env->nb_ways = nb_ways;
1669    env->id_tlbs = 1;
1670    env->tlb_type = TLB_6XX;
1671    /* XXX : not implemented */
1672    spr_register(env, SPR_PTEHI, "PTEHI",
1673                 SPR_NOACCESS, SPR_NOACCESS,
1674                 &spr_read_generic, &spr_write_generic,
1675                 0x00000000);
1676    /* XXX : not implemented */
1677    spr_register(env, SPR_PTELO, "PTELO",
1678                 SPR_NOACCESS, SPR_NOACCESS,
1679                 &spr_read_generic, &spr_write_generic,
1680                 0x00000000);
1681    /* XXX : not implemented */
1682    spr_register(env, SPR_TLBMISS, "TLBMISS",
1683                 SPR_NOACCESS, SPR_NOACCESS,
1684                 &spr_read_generic, &spr_write_generic,
1685                 0x00000000);
1686#endif
1687}
1688
1689#if !defined(CONFIG_USER_ONLY)
1690static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1691{
1692    TCGv t0 = tcg_temp_new();
1693
1694    tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1695    gen_store_spr(sprn, t0);
1696    tcg_temp_free(t0);
1697}
1698
1699static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1700{
1701    TCGv t0 = tcg_temp_new();
1702
1703    tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1704    gen_store_spr(sprn, t0);
1705    tcg_temp_free(t0);
1706}
1707
1708static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1709{
1710    gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1711}
1712
1713static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1714{
1715    TCGv_i32 t0 = tcg_const_i32(sprn);
1716    gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1717    tcg_temp_free_i32(t0);
1718}
1719static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
1720{
1721    gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
1722}
1723static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
1724{
1725    gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
1726}
1727
1728#endif
1729
1730static void gen_spr_usprg3(CPUPPCState *env)
1731{
1732    spr_register(env, SPR_USPRG3, "USPRG3",
1733                 &spr_read_ureg, SPR_NOACCESS,
1734                 &spr_read_ureg, SPR_NOACCESS,
1735                 0x00000000);
1736}
1737
1738static void gen_spr_usprgh(CPUPPCState *env)
1739{
1740    spr_register(env, SPR_USPRG4, "USPRG4",
1741                 &spr_read_ureg, SPR_NOACCESS,
1742                 &spr_read_ureg, SPR_NOACCESS,
1743                 0x00000000);
1744    spr_register(env, SPR_USPRG5, "USPRG5",
1745                 &spr_read_ureg, SPR_NOACCESS,
1746                 &spr_read_ureg, SPR_NOACCESS,
1747                 0x00000000);
1748    spr_register(env, SPR_USPRG6, "USPRG6",
1749                 &spr_read_ureg, SPR_NOACCESS,
1750                 &spr_read_ureg, SPR_NOACCESS,
1751                 0x00000000);
1752    spr_register(env, SPR_USPRG7, "USPRG7",
1753                 &spr_read_ureg, SPR_NOACCESS,
1754                 &spr_read_ureg, SPR_NOACCESS,
1755                 0x00000000);
1756}
1757
1758/* PowerPC BookE SPR */
1759static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
1760{
1761    const char *ivor_names[64] = {
1762        "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
1763        "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
1764        "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
1765        "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1766        "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1767        "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1768        "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1769        "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1770        "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1771        "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1772        "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1773        "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1774        "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1775        "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1776        "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1777        "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1778    };
1779#define SPR_BOOKE_IVORxx (-1)
1780    int ivor_sprn[64] = {
1781        SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
1782        SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
1783        SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1784        SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1785        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1786        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1787        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1788        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1789        SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1790        SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1791        SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1792        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1793        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1794        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1795        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1796        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1797    };
1798    int i;
1799
1800    /* Interrupt processing */
1801    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1802                 SPR_NOACCESS, SPR_NOACCESS,
1803                 &spr_read_generic, &spr_write_generic,
1804                 0x00000000);
1805    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1806                 SPR_NOACCESS, SPR_NOACCESS,
1807                 &spr_read_generic, &spr_write_generic,
1808                 0x00000000);
1809    /* Debug */
1810    /* XXX : not implemented */
1811    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1812                 SPR_NOACCESS, SPR_NOACCESS,
1813                 &spr_read_generic, &spr_write_generic,
1814                 0x00000000);
1815    /* XXX : not implemented */
1816    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1817                 SPR_NOACCESS, SPR_NOACCESS,
1818                 &spr_read_generic, &spr_write_generic,
1819                 0x00000000);
1820    /* XXX : not implemented */
1821    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1822                 SPR_NOACCESS, SPR_NOACCESS,
1823                 &spr_read_generic, &spr_write_generic,
1824                 0x00000000);
1825    /* XXX : not implemented */
1826    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1827                 SPR_NOACCESS, SPR_NOACCESS,
1828                 &spr_read_generic, &spr_write_generic,
1829                 0x00000000);
1830    /* XXX : not implemented */
1831    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1832                 SPR_NOACCESS, SPR_NOACCESS,
1833                 &spr_read_generic, &spr_write_40x_dbcr0,
1834                 0x00000000);
1835    /* XXX : not implemented */
1836    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1837                 SPR_NOACCESS, SPR_NOACCESS,
1838                 &spr_read_generic, &spr_write_generic,
1839                 0x00000000);
1840    /* XXX : not implemented */
1841    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1842                 SPR_NOACCESS, SPR_NOACCESS,
1843                 &spr_read_generic, &spr_write_generic,
1844                 0x00000000);
1845    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1846                 SPR_NOACCESS, SPR_NOACCESS,
1847                 &spr_read_generic, &spr_write_generic,
1848                 0x00000000);
1849    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1850                 SPR_NOACCESS, SPR_NOACCESS,
1851                 &spr_read_generic, &spr_write_generic,
1852                 0x00000000);
1853    /* XXX : not implemented */
1854    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1855                 SPR_NOACCESS, SPR_NOACCESS,
1856                 &spr_read_generic, &spr_write_clear,
1857                 0x00000000);
1858    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1859                 SPR_NOACCESS, SPR_NOACCESS,
1860                 &spr_read_generic, &spr_write_generic,
1861                 0x00000000);
1862    spr_register(env, SPR_BOOKE_ESR, "ESR",
1863                 SPR_NOACCESS, SPR_NOACCESS,
1864                 &spr_read_generic, &spr_write_generic,
1865                 0x00000000);
1866    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1867                 SPR_NOACCESS, SPR_NOACCESS,
1868                 &spr_read_generic, &spr_write_excp_prefix,
1869                 0x00000000);
1870    /* Exception vectors */
1871    for (i = 0; i < 64; i++) {
1872        if (ivor_mask & (1ULL << i)) {
1873            if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1874                fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1875                exit(1);
1876            }
1877            spr_register(env, ivor_sprn[i], ivor_names[i],
1878                         SPR_NOACCESS, SPR_NOACCESS,
1879                         &spr_read_generic, &spr_write_excp_vector,
1880                         0x00000000);
1881        }
1882    }
1883    spr_register(env, SPR_BOOKE_PID, "PID",
1884                 SPR_NOACCESS, SPR_NOACCESS,
1885                 &spr_read_generic, &spr_write_booke_pid,
1886                 0x00000000);
1887    spr_register(env, SPR_BOOKE_TCR, "TCR",
1888                 SPR_NOACCESS, SPR_NOACCESS,
1889                 &spr_read_generic, &spr_write_booke_tcr,
1890                 0x00000000);
1891    spr_register(env, SPR_BOOKE_TSR, "TSR",
1892                 SPR_NOACCESS, SPR_NOACCESS,
1893                 &spr_read_generic, &spr_write_booke_tsr,
1894                 0x00000000);
1895    /* Timer */
1896    spr_register(env, SPR_DECR, "DECR",
1897                 SPR_NOACCESS, SPR_NOACCESS,
1898                 &spr_read_decr, &spr_write_decr,
1899                 0x00000000);
1900    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1901                 SPR_NOACCESS, SPR_NOACCESS,
1902                 SPR_NOACCESS, &spr_write_generic,
1903                 0x00000000);
1904    /* SPRGs */
1905    spr_register(env, SPR_USPRG0, "USPRG0",
1906                 &spr_read_generic, &spr_write_generic,
1907                 &spr_read_generic, &spr_write_generic,
1908                 0x00000000);
1909    spr_register(env, SPR_SPRG4, "SPRG4",
1910                 SPR_NOACCESS, SPR_NOACCESS,
1911                 &spr_read_generic, &spr_write_generic,
1912                 0x00000000);
1913    spr_register(env, SPR_SPRG5, "SPRG5",
1914                 SPR_NOACCESS, SPR_NOACCESS,
1915                 &spr_read_generic, &spr_write_generic,
1916                 0x00000000);
1917    spr_register(env, SPR_SPRG6, "SPRG6",
1918                 SPR_NOACCESS, SPR_NOACCESS,
1919                 &spr_read_generic, &spr_write_generic,
1920                 0x00000000);
1921    spr_register(env, SPR_SPRG7, "SPRG7",
1922                 SPR_NOACCESS, SPR_NOACCESS,
1923                 &spr_read_generic, &spr_write_generic,
1924                 0x00000000);
1925    spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
1926                 SPR_NOACCESS, SPR_NOACCESS,
1927                 &spr_read_generic, &spr_write_generic,
1928                 0x00000000);
1929    spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
1930                 SPR_NOACCESS, SPR_NOACCESS,
1931                 &spr_read_generic, &spr_write_generic,
1932                 0x00000000);
1933}
1934
1935static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1936                                   uint32_t maxsize, uint32_t flags,
1937                                   uint32_t nentries)
1938{
1939    return (assoc << TLBnCFG_ASSOC_SHIFT) |
1940           (minsize << TLBnCFG_MINSIZE_SHIFT) |
1941           (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1942           flags | nentries;
1943}
1944
1945/* BookE 2.06 storage control registers */
1946static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1947                             uint32_t *tlbncfg, uint32_t mmucfg)
1948{
1949#if !defined(CONFIG_USER_ONLY)
1950    const char *mas_names[8] = {
1951        "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1952    };
1953    int mas_sprn[8] = {
1954        SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1955        SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1956    };
1957    int i;
1958
1959    /* TLB assist registers */
1960    /* XXX : not implemented */
1961    for (i = 0; i < 8; i++) {
1962        void (*uea_write)(DisasContext *ctx, int sprn, int gprn) =
1963            &spr_write_generic32;
1964        if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1965            uea_write = &spr_write_generic;
1966        }
1967        if (mas_mask & (1 << i)) {
1968            spr_register(env, mas_sprn[i], mas_names[i],
1969                         SPR_NOACCESS, SPR_NOACCESS,
1970                         &spr_read_generic, uea_write,
1971                         0x00000000);
1972        }
1973    }
1974    if (env->nb_pids > 1) {
1975        /* XXX : not implemented */
1976        spr_register(env, SPR_BOOKE_PID1, "PID1",
1977                     SPR_NOACCESS, SPR_NOACCESS,
1978                     &spr_read_generic, &spr_write_booke_pid,
1979                     0x00000000);
1980    }
1981    if (env->nb_pids > 2) {
1982        /* XXX : not implemented */
1983        spr_register(env, SPR_BOOKE_PID2, "PID2",
1984                     SPR_NOACCESS, SPR_NOACCESS,
1985                     &spr_read_generic, &spr_write_booke_pid,
1986                     0x00000000);
1987    }
1988
1989    spr_register(env, SPR_BOOKE_EPLC, "EPLC",
1990                 SPR_NOACCESS, SPR_NOACCESS,
1991                 &spr_read_generic, &spr_write_eplc,
1992                 0x00000000);
1993    spr_register(env, SPR_BOOKE_EPSC, "EPSC",
1994                 SPR_NOACCESS, SPR_NOACCESS,
1995                 &spr_read_generic, &spr_write_epsc,
1996                 0x00000000);
1997
1998    /* XXX : not implemented */
1999    spr_register(env, SPR_MMUCFG, "MMUCFG",
2000                 SPR_NOACCESS, SPR_NOACCESS,

2001                 &spr_read_generic, SPR_NOACCESS,
2002                 mmucfg);
2003    switch (env->nb_ways) {
2004    case 4:
2005        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
2006                     SPR_NOACCESS, SPR_NOACCESS,
2007                     &spr_read_generic, SPR_NOACCESS,
2008                     tlbncfg[3]);
2009        /* Fallthru */
2010    case 3:
2011        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
2012                     SPR_NOACCESS, SPR_NOACCESS,
2013                     &spr_read_generic, SPR_NOACCESS,
2014                     tlbncfg[2]);
2015        /* Fallthru */
2016    case 2:
2017        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
2018                     SPR_NOACCESS, SPR_NOACCESS,
2019                     &spr_read_generic, SPR_NOACCESS,
2020                     tlbncfg[1]);
2021        /* Fallthru */
2022    case 1:
2023        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
2024                     SPR_NOACCESS, SPR_NOACCESS,
2025                     &spr_read_generic, SPR_NOACCESS,
2026                     tlbncfg[0]);
2027        /* Fallthru */
2028    case 0:
2029    default:
2030        break;
2031    }
2032#endif
2033
2034    gen_spr_usprgh(env);
2035}
2036
2037/* SPR specific to PowerPC 440 implementation */
2038static void gen_spr_440(CPUPPCState *env)
2039{
2040    /* Cache control */
2041    /* XXX : not implemented */
2042    spr_register(env, SPR_440_DNV0, "DNV0",
2043                 SPR_NOACCESS, SPR_NOACCESS,
2044                 &spr_read_generic, &spr_write_generic,
2045                 0x00000000);
2046    /* XXX : not implemented */
2047    spr_register(env, SPR_440_DNV1, "DNV1",
2048                 SPR_NOACCESS, SPR_NOACCESS,
2049                 &spr_read_generic, &spr_write_generic,
2050                 0x00000000);
2051    /* XXX : not implemented */
2052    spr_register(env, SPR_440_DNV2, "DNV2",
2053                 SPR_NOACCESS, SPR_NOACCESS,
2054                 &spr_read_generic, &spr_write_generic,
2055                 0x00000000);
2056    /* XXX : not implemented */
2057    spr_register(env, SPR_440_DNV3, "DNV3",
2058                 SPR_NOACCESS, SPR_NOACCESS,
2059                 &spr_read_generic, &spr_write_generic,
2060                 0x00000000);
2061    /* XXX : not implemented */
2062    spr_register(env, SPR_440_DTV0, "DTV0",
2063                 SPR_NOACCESS, SPR_NOACCESS,
2064                 &spr_read_generic, &spr_write_generic,
2065                 0x00000000);
2066    /* XXX : not implemented */
2067    spr_register(env, SPR_440_DTV1, "DTV1",
2068                 SPR_NOACCESS, SPR_NOACCESS,
2069                 &spr_read_generic, &spr_write_generic,
2070                 0x00000000);
2071    /* XXX : not implemented */
2072    spr_register(env, SPR_440_DTV2, "DTV2",
2073                 SPR_NOACCESS, SPR_NOACCESS,
2074                 &spr_read_generic, &spr_write_generic,
2075                 0x00000000);
2076    /* XXX : not implemented */
2077    spr_register(env, SPR_440_DTV3, "DTV3",
2078                 SPR_NOACCESS, SPR_NOACCESS,
2079                 &spr_read_generic, &spr_write_generic,
2080                 0x00000000);
2081    /* XXX : not implemented */
2082    spr_register(env, SPR_440_DVLIM, "DVLIM",
2083                 SPR_NOACCESS, SPR_NOACCESS,
2084                 &spr_read_generic, &spr_write_generic,
2085                 0x00000000);
2086    /* XXX : not implemented */
2087    spr_register(env, SPR_440_INV0, "INV0",
2088                 SPR_NOACCESS, SPR_NOACCESS,
2089                 &spr_read_generic, &spr_write_generic,
2090                 0x00000000);
2091    /* XXX : not implemented */
2092    spr_register(env, SPR_440_INV1, "INV1",
2093                 SPR_NOACCESS, SPR_NOACCESS,
2094                 &spr_read_generic, &spr_write_generic,
2095                 0x00000000);
2096    /* XXX : not implemented */
2097    spr_register(env, SPR_440_INV2, "INV2",
2098                 SPR_NOACCESS, SPR_NOACCESS,
2099                 &spr_read_generic, &spr_write_generic,
2100                 0x00000000);
2101    /* XXX : not implemented */
2102    spr_register(env, SPR_440_INV3, "INV3",
2103                 SPR_NOACCESS, SPR_NOACCESS,
2104                 &spr_read_generic, &spr_write_generic,
2105                 0x00000000);
2106    /* XXX : not implemented */
2107    spr_register(env, SPR_440_ITV0, "ITV0",
2108                 SPR_NOACCESS, SPR_NOACCESS,
2109                 &spr_read_generic, &spr_write_generic,
2110                 0x00000000);
2111    /* XXX : not implemented */
2112    spr_register(env, SPR_440_ITV1, "ITV1",
2113                 SPR_NOACCESS, SPR_NOACCESS,
2114                 &spr_read_generic, &spr_write_generic,
2115                 0x00000000);
2116    /* XXX : not implemented */
2117    spr_register(env, SPR_440_ITV2, "ITV2",
2118                 SPR_NOACCESS, SPR_NOACCESS,
2119                 &spr_read_generic, &spr_write_generic,
2120                 0x00000000);
2121    /* XXX : not implemented */
2122    spr_register(env, SPR_440_ITV3, "ITV3",
2123                 SPR_NOACCESS, SPR_NOACCESS,
2124                 &spr_read_generic, &spr_write_generic,
2125                 0x00000000);
2126    /* XXX : not implemented */
2127    spr_register(env, SPR_440_IVLIM, "IVLIM",
2128                 SPR_NOACCESS, SPR_NOACCESS,
2129                 &spr_read_generic, &spr_write_generic,
2130                 0x00000000);
2131    /* Cache debug */
2132    /* XXX : not implemented */
2133    spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
2134                 SPR_NOACCESS, SPR_NOACCESS,
2135                 &spr_read_generic, SPR_NOACCESS,
2136                 0x00000000);
2137    /* XXX : not implemented */
2138    spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
2139                 SPR_NOACCESS, SPR_NOACCESS,
2140                 &spr_read_generic, SPR_NOACCESS,
2141                 0x00000000);
2142    /* XXX : not implemented */
2143    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2144                 SPR_NOACCESS, SPR_NOACCESS,
2145                 &spr_read_generic, SPR_NOACCESS,
2146                 0x00000000);
2147    /* XXX : not implemented */
2148    spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
2149                 SPR_NOACCESS, SPR_NOACCESS,
2150                 &spr_read_generic, SPR_NOACCESS,
2151                 0x00000000);
2152    /* XXX : not implemented */
2153    spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
2154                 SPR_NOACCESS, SPR_NOACCESS,
2155                 &spr_read_generic, SPR_NOACCESS,
2156                 0x00000000);
2157    /* XXX : not implemented */
2158    spr_register(env, SPR_440_DBDR, "DBDR",
2159                 SPR_NOACCESS, SPR_NOACCESS,
2160                 &spr_read_generic, &spr_write_generic,
2161                 0x00000000);
2162    /* Processor control */
2163    spr_register(env, SPR_4xx_CCR0, "CCR0",
2164                 SPR_NOACCESS, SPR_NOACCESS,
2165                 &spr_read_generic, &spr_write_generic,
2166                 0x00000000);
2167    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
2168                 SPR_NOACCESS, SPR_NOACCESS,
2169                 &spr_read_generic, SPR_NOACCESS,
2170                 0x00000000);
2171    /* Storage control */
2172    spr_register(env, SPR_440_MMUCR, "MMUCR",
2173                 SPR_NOACCESS, SPR_NOACCESS,
2174                 &spr_read_generic, &spr_write_generic,
2175                 0x00000000);
2176}
2177
2178/* SPR shared between PowerPC 40x implementations */
2179static void gen_spr_40x(CPUPPCState *env)
2180{
2181    /* Cache */
2182    /* not emulated, as QEMU do not emulate caches */
2183    spr_register(env, SPR_40x_DCCR, "DCCR",
2184                 SPR_NOACCESS, SPR_NOACCESS,
2185                 &spr_read_generic, &spr_write_generic,
2186                 0x00000000);
2187    /* not emulated, as QEMU do not emulate caches */
2188    spr_register(env, SPR_40x_ICCR, "ICCR",
2189                 SPR_NOACCESS, SPR_NOACCESS,
2190                 &spr_read_generic, &spr_write_generic,
2191                 0x00000000);
2192    /* not emulated, as QEMU do not emulate caches */
2193    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2194                 SPR_NOACCESS, SPR_NOACCESS,
2195                 &spr_read_generic, SPR_NOACCESS,
2196                 0x00000000);
2197    /* Exception */
2198    spr_register(env, SPR_40x_DEAR, "DEAR",
2199                 SPR_NOACCESS, SPR_NOACCESS,
2200                 &spr_read_generic, &spr_write_generic,
2201                 0x00000000);
2202    spr_register(env, SPR_40x_ESR, "ESR",
2203                 SPR_NOACCESS, SPR_NOACCESS,
2204                 &spr_read_generic, &spr_write_generic,
2205                 0x00000000);
2206    spr_register(env, SPR_40x_EVPR, "EVPR",
2207                 SPR_NOACCESS, SPR_NOACCESS,
2208                 &spr_read_generic, &spr_write_excp_prefix,
2209                 0x00000000);
2210    spr_register(env, SPR_40x_SRR2, "SRR2",
2211                 &spr_read_generic, &spr_write_generic,
2212                 &spr_read_generic, &spr_write_generic,
2213                 0x00000000);
2214    spr_register(env, SPR_40x_SRR3, "SRR3",
2215                 &spr_read_generic, &spr_write_generic,
2216                 &spr_read_generic, &spr_write_generic,
2217                 0x00000000);
2218    /* Timers */
2219    spr_register(env, SPR_40x_PIT, "PIT",
2220                 SPR_NOACCESS, SPR_NOACCESS,
2221                 &spr_read_40x_pit, &spr_write_40x_pit,
2222                 0x00000000);
2223    spr_register(env, SPR_40x_TCR, "TCR",
2224                 SPR_NOACCESS, SPR_NOACCESS,
2225                 &spr_read_generic, &spr_write_booke_tcr,
2226                 0x00000000);
2227    spr_register(env, SPR_40x_TSR, "TSR",
2228                 SPR_NOACCESS, SPR_NOACCESS,
2229                 &spr_read_generic, &spr_write_booke_tsr,
2230                 0x00000000);
2231}
2232
2233/* SPR specific to PowerPC 405 implementation */
2234static void gen_spr_405(CPUPPCState *env)
2235{
2236    /* MMU */
2237    spr_register(env, SPR_40x_PID, "PID",
2238                 SPR_NOACCESS, SPR_NOACCESS,
2239                 &spr_read_generic, &spr_write_generic,
2240                 0x00000000);
2241    spr_register(env, SPR_4xx_CCR0, "CCR0",
2242                 SPR_NOACCESS, SPR_NOACCESS,
2243                 &spr_read_generic, &spr_write_generic,
2244                 0x00700000);
2245    /* Debug interface */
2246    /* XXX : not implemented */
2247    spr_register(env, SPR_40x_DBCR0, "DBCR0",
2248                 SPR_NOACCESS, SPR_NOACCESS,
2249                 &spr_read_generic, &spr_write_40x_dbcr0,
2250                 0x00000000);
2251    /* XXX : not implemented */
2252    spr_register(env, SPR_405_DBCR1, "DBCR1",
2253                 SPR_NOACCESS, SPR_NOACCESS,
2254                 &spr_read_generic, &spr_write_generic,
2255                 0x00000000);
2256    /* XXX : not implemented */
2257    spr_register(env, SPR_40x_DBSR, "DBSR",
2258                 SPR_NOACCESS, SPR_NOACCESS,
2259                 &spr_read_generic, &spr_write_clear,
2260                 /* Last reset was system reset */
2261                 0x00000300);
2262    /* XXX : not implemented */
2263    spr_register(env, SPR_40x_DAC1, "DAC1",
2264                 SPR_NOACCESS, SPR_NOACCESS,
2265                 &spr_read_generic, &spr_write_generic,
2266                 0x00000000);
2267    spr_register(env, SPR_40x_DAC2, "DAC2",
2268                 SPR_NOACCESS, SPR_NOACCESS,
2269                 &spr_read_generic, &spr_write_generic,
2270                 0x00000000);
2271    /* XXX : not implemented */
2272    spr_register(env, SPR_405_DVC1, "DVC1",
2273                 SPR_NOACCESS, SPR_NOACCESS,
2274                 &spr_read_generic, &spr_write_generic,
2275                 0x00000000);
2276    /* XXX : not implemented */
2277    spr_register(env, SPR_405_DVC2, "DVC2",
2278                 SPR_NOACCESS, SPR_NOACCESS,
2279                 &spr_read_generic, &spr_write_generic,
2280                 0x00000000);
2281    /* XXX : not implemented */
2282    spr_register(env, SPR_40x_IAC1, "IAC1",
2283                 SPR_NOACCESS, SPR_NOACCESS,
2284                 &spr_read_generic, &spr_write_generic,
2285                 0x00000000);
2286    spr_register(env, SPR_40x_IAC2, "IAC2",
2287                 SPR_NOACCESS, SPR_NOACCESS,
2288                 &spr_read_generic, &spr_write_generic,
2289                 0x00000000);
2290    /* XXX : not implemented */
2291    spr_register(env, SPR_405_IAC3, "IAC3",
2292                 SPR_NOACCESS, SPR_NOACCESS,
2293                 &spr_read_generic, &spr_write_generic,
2294                 0x00000000);
2295    /* XXX : not implemented */
2296    spr_register(env, SPR_405_IAC4, "IAC4",
2297                 SPR_NOACCESS, SPR_NOACCESS,
2298                 &spr_read_generic, &spr_write_generic,
2299                 0x00000000);
2300    /* Storage control */
2301    /* XXX: TODO: not implemented */
2302    spr_register(env, SPR_405_SLER, "SLER",
2303                 SPR_NOACCESS, SPR_NOACCESS,
2304                 &spr_read_generic, &spr_write_40x_sler,
2305                 0x00000000);
2306    spr_register(env, SPR_40x_ZPR, "ZPR",
2307                 SPR_NOACCESS, SPR_NOACCESS,
2308                 &spr_read_generic, &spr_write_generic,
2309                 0x00000000);
2310    /* XXX : not implemented */
2311    spr_register(env, SPR_405_SU0R, "SU0R",
2312                 SPR_NOACCESS, SPR_NOACCESS,
2313                 &spr_read_generic, &spr_write_generic,
2314                 0x00000000);
2315    /* SPRG */
2316    spr_register(env, SPR_USPRG0, "USPRG0",
2317                 &spr_read_ureg, SPR_NOACCESS,
2318                 &spr_read_ureg, SPR_NOACCESS,
2319                 0x00000000);
2320    spr_register(env, SPR_SPRG4, "SPRG4",
2321                 SPR_NOACCESS, SPR_NOACCESS,
2322                 &spr_read_generic, &spr_write_generic,
2323                 0x00000000);
2324    spr_register(env, SPR_SPRG5, "SPRG5",
2325                 SPR_NOACCESS, SPR_NOACCESS,
2326                 spr_read_generic, &spr_write_generic,
2327                 0x00000000);
2328    spr_register(env, SPR_SPRG6, "SPRG6",
2329                 SPR_NOACCESS, SPR_NOACCESS,
2330                 spr_read_generic, &spr_write_generic,
2331                 0x00000000);
2332    spr_register(env, SPR_SPRG7, "SPRG7",
2333                 SPR_NOACCESS, SPR_NOACCESS,
2334                 spr_read_generic, &spr_write_generic,
2335                 0x00000000);
2336    gen_spr_usprgh(env);
2337}
2338
2339/* SPR shared between PowerPC 401 & 403 implementations */
2340static void gen_spr_401_403(CPUPPCState *env)
2341{
2342    /* Time base */
2343    spr_register(env, SPR_403_VTBL,  "TBL",
2344                 &spr_read_tbl, SPR_NOACCESS,
2345                 &spr_read_tbl, SPR_NOACCESS,
2346                 0x00000000);
2347    spr_register(env, SPR_403_TBL,   "TBL",
2348                 SPR_NOACCESS, SPR_NOACCESS,
2349                 SPR_NOACCESS, &spr_write_tbl,
2350                 0x00000000);
2351    spr_register(env, SPR_403_VTBU,  "TBU",
2352                 &spr_read_tbu, SPR_NOACCESS,
2353                 &spr_read_tbu, SPR_NOACCESS,
2354                 0x00000000);
2355    spr_register(env, SPR_403_TBU,   "TBU",
2356                 SPR_NOACCESS, SPR_NOACCESS,
2357                 SPR_NOACCESS, &spr_write_tbu,
2358                 0x00000000);
2359    /* Debug */
2360    /* not emulated, as QEMU do not emulate caches */
2361    spr_register(env, SPR_403_CDBCR, "CDBCR",
2362                 SPR_NOACCESS, SPR_NOACCESS,
2363                 &spr_read_generic, &spr_write_generic,
2364                 0x00000000);
2365}
2366
2367/* SPR specific to PowerPC 401 implementation */
2368static void gen_spr_401(CPUPPCState *env)
2369{
2370    /* Debug interface */
2371    /* XXX : not implemented */
2372    spr_register(env, SPR_40x_DBCR0, "DBCR",
2373                 SPR_NOACCESS, SPR_NOACCESS,
2374                 &spr_read_generic, &spr_write_40x_dbcr0,
2375                 0x00000000);
2376    /* XXX : not implemented */
2377    spr_register(env, SPR_40x_DBSR, "DBSR",
2378                 SPR_NOACCESS, SPR_NOACCESS,
2379                 &spr_read_generic, &spr_write_clear,
2380                 /* Last reset was system reset */
2381                 0x00000300);
2382    /* XXX : not implemented */
2383    spr_register(env, SPR_40x_DAC1, "DAC",
2384                 SPR_NOACCESS, SPR_NOACCESS,
2385                 &spr_read_generic, &spr_write_generic,
2386                 0x00000000);
2387    /* XXX : not implemented */
2388    spr_register(env, SPR_40x_IAC1, "IAC",
2389                 SPR_NOACCESS, SPR_NOACCESS,
2390                 &spr_read_generic, &spr_write_generic,
2391                 0x00000000);
2392    /* Storage control */
2393    /* XXX: TODO: not implemented */
2394    spr_register(env, SPR_405_SLER, "SLER",
2395                 SPR_NOACCESS, SPR_NOACCESS,
2396                 &spr_read_generic, &spr_write_40x_sler,
2397                 0x00000000);
2398    /* not emulated, as QEMU never does speculative access */
2399    spr_register(env, SPR_40x_SGR, "SGR",
2400                 SPR_NOACCESS, SPR_NOACCESS,
2401                 &spr_read_generic, &spr_write_generic,
2402                 0xFFFFFFFF);
2403    /* not emulated, as QEMU do not emulate caches */
2404    spr_register(env, SPR_40x_DCWR, "DCWR",
2405                 SPR_NOACCESS, SPR_NOACCESS,
2406                 &spr_read_generic, &spr_write_generic,
2407                 0x00000000);
2408}
2409
2410static void gen_spr_401x2(CPUPPCState *env)
2411{
2412    gen_spr_401(env);
2413    spr_register(env, SPR_40x_PID, "PID",
2414                 SPR_NOACCESS, SPR_NOACCESS,
2415                 &spr_read_generic, &spr_write_generic,
2416                 0x00000000);
2417    spr_register(env, SPR_40x_ZPR, "ZPR",
2418                 SPR_NOACCESS, SPR_NOACCESS,
2419                 &spr_read_generic, &spr_write_generic,
2420                 0x00000000);
2421}
2422
2423/* SPR specific to PowerPC 403 implementation */
2424static void gen_spr_403(CPUPPCState *env)
2425{
2426    /* Debug interface */
2427    /* XXX : not implemented */
2428    spr_register(env, SPR_40x_DBCR0, "DBCR0",
2429                 SPR_NOACCESS, SPR_NOACCESS,
2430                 &spr_read_generic, &spr_write_40x_dbcr0,
2431                 0x00000000);
2432    /* XXX : not implemented */
2433    spr_register(env, SPR_40x_DBSR, "DBSR",
2434                 SPR_NOACCESS, SPR_NOACCESS,
2435                 &spr_read_generic, &spr_write_clear,
2436                 /* Last reset was system reset */
2437                 0x00000300);
2438    /* XXX : not implemented */
2439    spr_register(env, SPR_40x_DAC1, "DAC1",
2440                 SPR_NOACCESS, SPR_NOACCESS,
2441                 &spr_read_generic, &spr_write_generic,
2442                 0x00000000);
2443    /* XXX : not implemented */
2444    spr_register(env, SPR_40x_DAC2, "DAC2",
2445                 SPR_NOACCESS, SPR_NOACCESS,
2446                 &spr_read_generic, &spr_write_generic,
2447                 0x00000000);
2448    /* XXX : not implemented */
2449    spr_register(env, SPR_40x_IAC1, "IAC1",
2450                 SPR_NOACCESS, SPR_NOACCESS,
2451                 &spr_read_generic, &spr_write_generic,
2452                 0x00000000);
2453    /* XXX : not implemented */
2454    spr_register(env, SPR_40x_IAC2, "IAC2",
2455                 SPR_NOACCESS, SPR_NOACCESS,
2456                 &spr_read_generic, &spr_write_generic,
2457                 0x00000000);
2458}
2459
2460static void gen_spr_403_real(CPUPPCState *env)
2461{
2462    spr_register(env, SPR_403_PBL1,  "PBL1",
2463                 SPR_NOACCESS, SPR_NOACCESS,
2464                 &spr_read_403_pbr, &spr_write_403_pbr,
2465                 0x00000000);
2466    spr_register(env, SPR_403_PBU1,  "PBU1",
2467                 SPR_NOACCESS, SPR_NOACCESS,
2468                 &spr_read_403_pbr, &spr_write_403_pbr,
2469                 0x00000000);
2470    spr_register(env, SPR_403_PBL2,  "PBL2",
2471                 SPR_NOACCESS, SPR_NOACCESS,
2472                 &spr_read_403_pbr, &spr_write_403_pbr,
2473                 0x00000000);
2474    spr_register(env, SPR_403_PBU2,  "PBU2",
2475                 SPR_NOACCESS, SPR_NOACCESS,
2476                 &spr_read_403_pbr, &spr_write_403_pbr,
2477                 0x00000000);
2478}
2479
2480static void gen_spr_403_mmu(CPUPPCState *env)
2481{
2482    /* MMU */
2483    spr_register(env, SPR_40x_PID, "PID",
2484                 SPR_NOACCESS, SPR_NOACCESS,
2485                 &spr_read_generic, &spr_write_generic,
2486                 0x00000000);
2487    spr_register(env, SPR_40x_ZPR, "ZPR",
2488                 SPR_NOACCESS, SPR_NOACCESS,
2489                 &spr_read_generic, &spr_write_generic,
2490                 0x00000000);
2491}
2492
2493/* SPR specific to PowerPC compression coprocessor extension */
2494static void gen_spr_compress(CPUPPCState *env)
2495{
2496    /* XXX : not implemented */
2497    spr_register(env, SPR_401_SKR, "SKR",
2498                 SPR_NOACCESS, SPR_NOACCESS,
2499                 &spr_read_generic, &spr_write_generic,
2500                 0x00000000);
2501}
2502
2503static void gen_spr_5xx_8xx(CPUPPCState *env)
2504{
2505    /* Exception processing */
2506    spr_register_kvm(env, SPR_DSISR, "DSISR",
2507                     SPR_NOACCESS, SPR_NOACCESS,
2508                     &spr_read_generic, &spr_write_generic,
2509                     KVM_REG_PPC_DSISR, 0x00000000);
2510    spr_register_kvm(env, SPR_DAR, "DAR",
2511                     SPR_NOACCESS, SPR_NOACCESS,
2512                     &spr_read_generic, &spr_write_generic,
2513                     KVM_REG_PPC_DAR, 0x00000000);
2514    /* Timer */
2515    spr_register(env, SPR_DECR, "DECR",
2516                 SPR_NOACCESS, SPR_NOACCESS,
2517                 &spr_read_decr, &spr_write_decr,
2518                 0x00000000);
2519    /* XXX : not implemented */
2520    spr_register(env, SPR_MPC_EIE, "EIE",
2521                 SPR_NOACCESS, SPR_NOACCESS,
2522                 &spr_read_generic, &spr_write_generic,
2523                 0x00000000);
2524    /* XXX : not implemented */
2525    spr_register(env, SPR_MPC_EID, "EID",
2526                 SPR_NOACCESS, SPR_NOACCESS,
2527                 &spr_read_generic, &spr_write_generic,
2528                 0x00000000);
2529    /* XXX : not implemented */
2530    spr_register(env, SPR_MPC_NRI, "NRI",
2531                 SPR_NOACCESS, SPR_NOACCESS,
2532                 &spr_read_generic, &spr_write_generic,
2533                 0x00000000);
2534    /* XXX : not implemented */
2535    spr_register(env, SPR_MPC_CMPA, "CMPA",
2536                 SPR_NOACCESS, SPR_NOACCESS,
2537                 &spr_read_generic, &spr_write_generic,
2538                 0x00000000);
2539    /* XXX : not implemented */
2540    spr_register(env, SPR_MPC_CMPB, "CMPB",
2541                 SPR_NOACCESS, SPR_NOACCESS,
2542                 &spr_read_generic, &spr_write_generic,
2543                 0x00000000);
2544    /* XXX : not implemented */
2545    spr_register(env, SPR_MPC_CMPC, "CMPC",
2546                 SPR_NOACCESS, SPR_NOACCESS,
2547                 &spr_read_generic, &spr_write_generic,
2548                 0x00000000);
2549    /* XXX : not implemented */
2550    spr_register(env, SPR_MPC_CMPD, "CMPD",
2551                 SPR_NOACCESS, SPR_NOACCESS,
2552                 &spr_read_generic, &spr_write_generic,
2553                 0x00000000);
2554    /* XXX : not implemented */
2555    spr_register(env, SPR_MPC_ECR, "ECR",
2556                 SPR_NOACCESS, SPR_NOACCESS,
2557                 &spr_read_generic, &spr_write_generic,
2558                 0x00000000);
2559    /* XXX : not implemented */
2560    spr_register(env, SPR_MPC_DER, "DER",
2561                 SPR_NOACCESS, SPR_NOACCESS,
2562                 &spr_read_generic, &spr_write_generic,
2563                 0x00000000);
2564    /* XXX : not implemented */
2565    spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2566                 SPR_NOACCESS, SPR_NOACCESS,
2567                 &spr_read_generic, &spr_write_generic,
2568                 0x00000000);
2569    /* XXX : not implemented */
2570    spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2571                 SPR_NOACCESS, SPR_NOACCESS,
2572                 &spr_read_generic, &spr_write_generic,
2573                 0x00000000);
2574    /* XXX : not implemented */
2575    spr_register(env, SPR_MPC_CMPE, "CMPE",
2576                 SPR_NOACCESS, SPR_NOACCESS,
2577                 &spr_read_generic, &spr_write_generic,
2578                 0x00000000);
2579    /* XXX : not implemented */
2580    spr_register(env, SPR_MPC_CMPF, "CMPF",
2581                 SPR_NOACCESS, SPR_NOACCESS,
2582                 &spr_read_generic, &spr_write_generic,
2583                 0x00000000);
2584    /* XXX : not implemented */
2585    spr_register(env, SPR_MPC_CMPG, "CMPG",
2586                 SPR_NOACCESS, SPR_NOACCESS,
2587                 &spr_read_generic, &spr_write_generic,
2588                 0x00000000);
2589    /* XXX : not implemented */
2590    spr_register(env, SPR_MPC_CMPH, "CMPH",
2591                 SPR_NOACCESS, SPR_NOACCESS,
2592                 &spr_read_generic, &spr_write_generic,
2593                 0x00000000);
2594    /* XXX : not implemented */
2595    spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2596                 SPR_NOACCESS, SPR_NOACCESS,
2597                 &spr_read_generic, &spr_write_generic,
2598                 0x00000000);
2599    /* XXX : not implemented */
2600    spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2601                 SPR_NOACCESS, SPR_NOACCESS,
2602                 &spr_read_generic, &spr_write_generic,
2603                 0x00000000);
2604    /* XXX : not implemented */
2605    spr_register(env, SPR_MPC_BAR, "BAR",
2606                 SPR_NOACCESS, SPR_NOACCESS,
2607                 &spr_read_generic, &spr_write_generic,
2608                 0x00000000);
2609    /* XXX : not implemented */
2610    spr_register(env, SPR_MPC_DPDR, "DPDR",
2611                 SPR_NOACCESS, SPR_NOACCESS,
2612                 &spr_read_generic, &spr_write_generic,
2613                 0x00000000);
2614    /* XXX : not implemented */
2615    spr_register(env, SPR_MPC_IMMR, "IMMR",
2616                 SPR_NOACCESS, SPR_NOACCESS,
2617                 &spr_read_generic, &spr_write_generic,
2618                 0x00000000);
2619}
2620
2621static void gen_spr_5xx(CPUPPCState *env)
2622{
2623    /* XXX : not implemented */
2624    spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2625                 SPR_NOACCESS, SPR_NOACCESS,
2626                 &spr_read_generic, &spr_write_generic,
2627                 0x00000000);
2628    /* XXX : not implemented */
2629    spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2630                 SPR_NOACCESS, SPR_NOACCESS,
2631                 &spr_read_generic, &spr_write_generic,
2632                 0x00000000);
2633    /* XXX : not implemented */
2634    spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2635                 SPR_NOACCESS, SPR_NOACCESS,
2636                 &spr_read_generic, &spr_write_generic,
2637                 0x00000000);
2638    /* XXX : not implemented */
2639    spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2640                 SPR_NOACCESS, SPR_NOACCESS,
2641                 &spr_read_generic, &spr_write_generic,
2642                 0x00000000);
2643    /* XXX : not implemented */
2644    spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2645                 SPR_NOACCESS, SPR_NOACCESS,
2646                 &spr_read_generic, &spr_write_generic,
2647                 0x00000000);
2648    /* XXX : not implemented */
2649    spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2650                 SPR_NOACCESS, SPR_NOACCESS,
2651                 &spr_read_generic, &spr_write_generic,
2652                 0x00000000);
2653    /* XXX : not implemented */
2654    spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2655                 SPR_NOACCESS, SPR_NOACCESS,
2656                 &spr_read_generic, &spr_write_generic,
2657                 0x00000000);
2658    /* XXX : not implemented */
2659    spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2660                 SPR_NOACCESS, SPR_NOACCESS,
2661                 &spr_read_generic, &spr_write_generic,
2662                 0x00000000);
2663    /* XXX : not implemented */
2664    spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2665                 SPR_NOACCESS, SPR_NOACCESS,
2666                 &spr_read_generic, &spr_write_generic,
2667                 0x00000000);
2668    /* XXX : not implemented */
2669    spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2670                 SPR_NOACCESS, SPR_NOACCESS,
2671                 &spr_read_generic, &spr_write_generic,
2672                 0x00000000);
2673    /* XXX : not implemented */
2674    spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2675                 SPR_NOACCESS, SPR_NOACCESS,
2676                 &spr_read_generic, &spr_write_generic,
2677                 0x00000000);
2678    /* XXX : not implemented */
2679    spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2680                 SPR_NOACCESS, SPR_NOACCESS,
2681                 &spr_read_generic, &spr_write_generic,
2682                 0x00000000);
2683    /* XXX : not implemented */
2684    spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2685                 SPR_NOACCESS, SPR_NOACCESS,
2686                 &spr_read_generic, &spr_write_generic,
2687                 0x00000000);
2688    /* XXX : not implemented */
2689    spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2690                 SPR_NOACCESS, SPR_NOACCESS,
2691                 &spr_read_generic, &spr_write_generic,
2692                 0x00000000);
2693    /* XXX : not implemented */
2694    spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2695                 SPR_NOACCESS, SPR_NOACCESS,
2696                 &spr_read_generic, &spr_write_generic,
2697                 0x00000000);
2698    /* XXX : not implemented */
2699    spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2700                 SPR_NOACCESS, SPR_NOACCESS,
2701                 &spr_read_generic, &spr_write_generic,
2702                 0x00000000);
2703    /* XXX : not implemented */
2704    spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2705                 SPR_NOACCESS, SPR_NOACCESS,
2706                 &spr_read_generic, &spr_write_generic,
2707                 0x00000000);
2708    /* XXX : not implemented */
2709    spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2710                 SPR_NOACCESS, SPR_NOACCESS,
2711                 &spr_read_generic, &spr_write_generic,
2712                 0x00000000);
2713    /* XXX : not implemented */
2714    spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2715                 SPR_NOACCESS, SPR_NOACCESS,
2716                 &spr_read_generic, &spr_write_generic,
2717                 0x00000000);
2718    /* XXX : not implemented */
2719    spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2720                 SPR_NOACCESS, SPR_NOACCESS,
2721                 &spr_read_generic, &spr_write_generic,
2722                 0x00000000);
2723    /* XXX : not implemented */
2724    spr_register(env, SPR_RCPU_FPECR, "FPECR",
2725                 SPR_NOACCESS, SPR_NOACCESS,
2726                 &spr_read_generic, &spr_write_generic,
2727                 0x00000000);
2728}
2729
2730static void gen_spr_8xx(CPUPPCState *env)
2731{
2732    /* XXX : not implemented */
2733    spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2734                 SPR_NOACCESS, SPR_NOACCESS,
2735                 &spr_read_generic, &spr_write_generic,
2736                 0x00000000);
2737    /* XXX : not implemented */
2738    spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2739                 SPR_NOACCESS, SPR_NOACCESS,
2740                 &spr_read_generic, &spr_write_generic,
2741                 0x00000000);
2742    /* XXX : not implemented */
2743    spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2744                 SPR_NOACCESS, SPR_NOACCESS,
2745                 &spr_read_generic, &spr_write_generic,
2746                 0x00000000);
2747    /* XXX : not implemented */
2748    spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2749                 SPR_NOACCESS, SPR_NOACCESS,
2750                 &spr_read_generic, &spr_write_generic,
2751                 0x00000000);
2752    /* XXX : not implemented */
2753    spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2754                 SPR_NOACCESS, SPR_NOACCESS,
2755                 &spr_read_generic, &spr_write_generic,
2756                 0x00000000);
2757    /* XXX : not implemented */
2758    spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2759                 SPR_NOACCESS, SPR_NOACCESS,
2760                 &spr_read_generic, &spr_write_generic,
2761                 0x00000000);
2762    /* XXX : not implemented */
2763    spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2764                 SPR_NOACCESS, SPR_NOACCESS,
2765                 &spr_read_generic, &spr_write_generic,
2766                 0x00000000);
2767    /* XXX : not implemented */
2768    spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2769                 SPR_NOACCESS, SPR_NOACCESS,
2770                 &spr_read_generic, &spr_write_generic,
2771                 0x00000000);
2772    /* XXX : not implemented */
2773    spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2774                 SPR_NOACCESS, SPR_NOACCESS,
2775                 &spr_read_generic, &spr_write_generic,
2776                 0x00000000);
2777    /* XXX : not implemented */
2778    spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2779                 SPR_NOACCESS, SPR_NOACCESS,
2780                 &spr_read_generic, &spr_write_generic,
2781                 0x00000000);
2782    /* XXX : not implemented */
2783    spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2784                 SPR_NOACCESS, SPR_NOACCESS,
2785                 &spr_read_generic, &spr_write_generic,
2786                 0x00000000);
2787    /* XXX : not implemented */
2788    spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2789                 SPR_NOACCESS, SPR_NOACCESS,
2790                 &spr_read_generic, &spr_write_generic,
2791                 0x00000000);
2792    /* XXX : not implemented */
2793    spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2794                 SPR_NOACCESS, SPR_NOACCESS,
2795                 &spr_read_generic, &spr_write_generic,
2796                 0x00000000);
2797    /* XXX : not implemented */
2798    spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2799                 SPR_NOACCESS, SPR_NOACCESS,
2800                 &spr_read_generic, &spr_write_generic,
2801                 0x00000000);
2802    /* XXX : not implemented */
2803    spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2804                 SPR_NOACCESS, SPR_NOACCESS,
2805                 &spr_read_generic, &spr_write_generic,
2806                 0x00000000);
2807    /* XXX : not implemented */
2808    spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2809                 SPR_NOACCESS, SPR_NOACCESS,
2810                 &spr_read_generic, &spr_write_generic,
2811                 0x00000000);
2812    /* XXX : not implemented */
2813    spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2814                 SPR_NOACCESS, SPR_NOACCESS,
2815                 &spr_read_generic, &spr_write_generic,
2816                 0x00000000);
2817    /* XXX : not implemented */
2818    spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2819                 SPR_NOACCESS, SPR_NOACCESS,
2820                 &spr_read_generic, &spr_write_generic,
2821                 0x00000000);
2822    /* XXX : not implemented */
2823    spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2824                 SPR_NOACCESS, SPR_NOACCESS,
2825                 &spr_read_generic, &spr_write_generic,
2826                 0x00000000);
2827    /* XXX : not implemented */
2828    spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2829                 SPR_NOACCESS, SPR_NOACCESS,
2830                 &spr_read_generic, &spr_write_generic,
2831                 0x00000000);
2832    /* XXX : not implemented */
2833    spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2834                 SPR_NOACCESS, SPR_NOACCESS,
2835                 &spr_read_generic, &spr_write_generic,
2836                 0x00000000);
2837    /* XXX : not implemented */
2838    spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2839                 SPR_NOACCESS, SPR_NOACCESS,
2840                 &spr_read_generic, &spr_write_generic,
2841                 0x00000000);
2842    /* XXX : not implemented */
2843    spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2844                 SPR_NOACCESS, SPR_NOACCESS,
2845                 &spr_read_generic, &spr_write_generic,
2846                 0x00000000);
2847    /* XXX : not implemented */
2848    spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2849                 SPR_NOACCESS, SPR_NOACCESS,
2850                 &spr_read_generic, &spr_write_generic,
2851                 0x00000000);
2852    /* XXX : not implemented */
2853    spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2854                 SPR_NOACCESS, SPR_NOACCESS,
2855                 &spr_read_generic, &spr_write_generic,
2856                 0x00000000);
2857}
2858
2859/*
2860 * AMR     => SPR 29 (Power 2.04)
2861 * CTRL    => SPR 136 (Power 2.04)
2862 * CTRL    => SPR 152 (Power 2.04)
2863 * SCOMC   => SPR 276 (64 bits ?)
2864 * SCOMD   => SPR 277 (64 bits ?)
2865 * TBU40   => SPR 286 (Power 2.04 hypv)
2866 * HSPRG0  => SPR 304 (Power 2.04 hypv)
2867 * HSPRG1  => SPR 305 (Power 2.04 hypv)
2868 * HDSISR  => SPR 306 (Power 2.04 hypv)
2869 * HDAR    => SPR 307 (Power 2.04 hypv)
2870 * PURR    => SPR 309 (Power 2.04 hypv)
2871 * HDEC    => SPR 310 (Power 2.04 hypv)
2872 * HIOR    => SPR 311 (hypv)
2873 * RMOR    => SPR 312 (970)
2874 * HRMOR   => SPR 313 (Power 2.04 hypv)
2875 * HSRR0   => SPR 314 (Power 2.04 hypv)
2876 * HSRR1   => SPR 315 (Power 2.04 hypv)
2877 * LPIDR   => SPR 317 (970)
2878 * EPR     => SPR 702 (Power 2.04 emb)
2879 * perf    => 768-783 (Power 2.04)
2880 * perf    => 784-799 (Power 2.04)
2881 * PPR     => SPR 896 (Power 2.04)
2882 * DABRX   => 1015    (Power 2.04 hypv)
2883 * FPECR   => SPR 1022 (?)
2884 * ... and more (thermal management, performance counters, ...)
2885 */
2886
2887/*****************************************************************************/
2888/* Exception vectors models                                                  */
2889static void init_excp_4xx_real(CPUPPCState *env)
2890{
2891#if !defined(CONFIG_USER_ONLY)
2892    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2893    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2894    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2895    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2896    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2897    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2898    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2899    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2900    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2901    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2902    env->ivor_mask = 0x0000FFF0UL;
2903    env->ivpr_mask = 0xFFFF0000UL;
2904    /* Hardware reset vector */
2905    env->hreset_vector = 0xFFFFFFFCUL;
2906#endif
2907}
2908
2909static void init_excp_4xx_softmmu(CPUPPCState *env)
2910{
2911#if !defined(CONFIG_USER_ONLY)
2912    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2913    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2914    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2915    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2916    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2917    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2918    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2919    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2920    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2921    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2922    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2923    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2924    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2925    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2926    env->ivor_mask = 0x0000FFF0UL;
2927    env->ivpr_mask = 0xFFFF0000UL;
2928    /* Hardware reset vector */
2929    env->hreset_vector = 0xFFFFFFFCUL;
2930#endif
2931}
2932
2933static void init_excp_MPC5xx(CPUPPCState *env)
2934{
2935#if !defined(CONFIG_USER_ONLY)
2936    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2937    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2938    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2939    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2940    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2941    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2942    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2943    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2944    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2945    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2946    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2947    env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2948    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2949    env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2950    env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2951    env->ivor_mask = 0x0000FFF0UL;
2952    env->ivpr_mask = 0xFFFF0000UL;
2953    /* Hardware reset vector */
2954    env->hreset_vector = 0x00000100UL;
2955#endif
2956}
2957
2958static void init_excp_MPC8xx(CPUPPCState *env)
2959{
2960#if !defined(CONFIG_USER_ONLY)
2961    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2962    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2963    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2964    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2965    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2966    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2967    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2968    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2969    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2970    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2971    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2972    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2973    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2974    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
2975    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
2976    env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
2977    env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
2978    env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2979    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2980    env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2981    env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2982    env->ivor_mask = 0x0000FFF0UL;
2983    env->ivpr_mask = 0xFFFF0000UL;
2984    /* Hardware reset vector */
2985    env->hreset_vector = 0x00000100UL;
2986#endif
2987}
2988
2989static void init_excp_G2(CPUPPCState *env)
2990{
2991#if !defined(CONFIG_USER_ONLY)
2992    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2993    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2994    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2995    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2996    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2997    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2998    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2999    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3000    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;

3001    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
3002    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3003    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3004    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3005    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3006    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3007    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3008    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3009    /* Hardware reset vector */
3010    env->hreset_vector = 0x00000100UL;
3011#endif
3012}
3013
3014static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
3015{
3016#if !defined(CONFIG_USER_ONLY)
3017    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
3018    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
3019    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
3020    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
3021    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
3022    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
3023    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
3024    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
3025    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
3026    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
3027    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
3028    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
3029    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
3030    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
3031    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
3032    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
3033    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
3034    env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
3035    env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
3036    env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
3037    env->ivor_mask = 0x0000FFF7UL;
3038    env->ivpr_mask = ivpr_mask;
3039    /* Hardware reset vector */
3040    env->hreset_vector = 0xFFFFFFFCUL;
3041#endif
3042}
3043
3044static void init_excp_BookE(CPUPPCState *env)
3045{
3046#if !defined(CONFIG_USER_ONLY)
3047    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
3048    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
3049    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
3050    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
3051    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
3052    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
3053    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
3054    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
3055    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
3056    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
3057    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
3058    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
3059    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
3060    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
3061    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
3062    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
3063    env->ivor_mask = 0x0000FFF0UL;
3064    env->ivpr_mask = 0xFFFF0000UL;
3065    /* Hardware reset vector */
3066    env->hreset_vector = 0xFFFFFFFCUL;
3067#endif
3068}
3069
3070static void init_excp_601(CPUPPCState *env)
3071{
3072#if !defined(CONFIG_USER_ONLY)
3073    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3074    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3075    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3076    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3077    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3078    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3079    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3080    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3081    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3082    env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
3083    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3084    env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
3085    /* Hardware reset vector */
3086    env->hreset_vector = 0x00000100UL;
3087#endif
3088}
3089
3090static void init_excp_602(CPUPPCState *env)
3091{
3092#if !defined(CONFIG_USER_ONLY)
3093    /* XXX: exception prefix has a special behavior on 602 */
3094    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3095    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3096    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3097    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3098    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3099    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3100    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3101    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3102    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3103    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3104    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3105    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3106    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3107    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3108    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3109    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3110    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
3111    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
3112    /* Hardware reset vector */
3113    env->hreset_vector = 0x00000100UL;
3114#endif
3115}
3116
3117static void init_excp_603(CPUPPCState *env)
3118{
3119#if !defined(CONFIG_USER_ONLY)
3120    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3121    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3122    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3123    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3124    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3125    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3126    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3127    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3128    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3129    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3130    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3131    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3132    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3133    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3134    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3135    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3136    /* Hardware reset vector */
3137    env->hreset_vector = 0x00000100UL;
3138#endif
3139}
3140
3141static void init_excp_604(CPUPPCState *env)
3142{
3143#if !defined(CONFIG_USER_ONLY)
3144    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3145    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3146    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3147    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3148    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3149    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3150    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3151    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3152    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3153    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3154    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3155    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3156    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3157    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3158    /* Hardware reset vector */
3159    env->hreset_vector = 0x00000100UL;
3160#endif
3161}
3162
3163static void init_excp_7x0(CPUPPCState *env)
3164{
3165#if !defined(CONFIG_USER_ONLY)
3166    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3167    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3168    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3169    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3170    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3171    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3172    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3173    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3174    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3175    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3176    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3177    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3178    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3179    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3180    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3181    /* Hardware reset vector */
3182    env->hreset_vector = 0x00000100UL;
3183#endif
3184}
3185
3186static void init_excp_750cl(CPUPPCState *env)
3187{
3188#if !defined(CONFIG_USER_ONLY)
3189    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3190    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3191    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3192    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3193    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3194    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3195    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3196    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3197    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3198    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3199    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3200    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3201    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3202    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3203    /* Hardware reset vector */
3204    env->hreset_vector = 0x00000100UL;
3205#endif
3206}
3207
3208static void init_excp_750cx(CPUPPCState *env)
3209{
3210#if !defined(CONFIG_USER_ONLY)
3211    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3212    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3213    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3214    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3215    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3216    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3217    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3218    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3219    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3220    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3221    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3222    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3223    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3224    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3225    /* Hardware reset vector */
3226    env->hreset_vector = 0x00000100UL;
3227#endif
3228}
3229
3230/* XXX: Check if this is correct */
3231static void init_excp_7x5(CPUPPCState *env)
3232{
3233#if !defined(CONFIG_USER_ONLY)
3234    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3235    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3236    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3237    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3238    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3239    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3240    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3241    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3242    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3243    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3244    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3245    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3246    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3247    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3248    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3249    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3250    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3251    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3252    /* Hardware reset vector */
3253    env->hreset_vector = 0x00000100UL;
3254#endif
3255}
3256
3257static void init_excp_7400(CPUPPCState *env)
3258{
3259#if !defined(CONFIG_USER_ONLY)
3260    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3261    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3262    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3263    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3264    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3265    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3266    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3267    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3268    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3269    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3270    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3271    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3272    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3273    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3274    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3275    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3276    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3277    /* Hardware reset vector */
3278    env->hreset_vector = 0x00000100UL;
3279#endif
3280}
3281
3282static void init_excp_7450(CPUPPCState *env)
3283{
3284#if !defined(CONFIG_USER_ONLY)
3285    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3286    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3287    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3288    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3289    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3290    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3291    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3292    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3293    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3294    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3295    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3296    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3297    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3298    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3299    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3300    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3301    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3302    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3303    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3304    /* Hardware reset vector */
3305    env->hreset_vector = 0x00000100UL;
3306#endif
3307}
3308
3309#if defined(TARGET_PPC64)
3310static void init_excp_970(CPUPPCState *env)
3311{
3312#if !defined(CONFIG_USER_ONLY)
3313    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3314    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3315    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3316    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3317    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3318    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3319    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3320    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3321    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3322    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3323    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3324    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3325    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3326    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3327    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3328    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3329    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3330    env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
3331    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
3332    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
3333    /* Hardware reset vector */
3334    env->hreset_vector = 0x0000000000000100ULL;
3335#endif
3336}
3337
3338static void init_excp_POWER7(CPUPPCState *env)
3339{
3340#if !defined(CONFIG_USER_ONLY)
3341    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3342    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3343    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3344    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3345    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3346    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3347    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3348    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3349    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3350    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3351    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3352    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3353    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3354    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3355    env->excp_vectors[POWERPC_EXCP_HDSI]     = 0x00000E00;
3356    env->excp_vectors[POWERPC_EXCP_HISI]     = 0x00000E20;
3357    env->excp_vectors[POWERPC_EXCP_HV_EMU]   = 0x00000E40;
3358    env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
3359    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3360    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3361    env->excp_vectors[POWERPC_EXCP_VSXU]     = 0x00000F40;
3362    /* Hardware reset vector */
3363    env->hreset_vector = 0x0000000000000100ULL;
3364#endif
3365}
3366
3367static void init_excp_POWER8(CPUPPCState *env)
3368{
3369    init_excp_POWER7(env);
3370
3371#if !defined(CONFIG_USER_ONLY)
3372    env->excp_vectors[POWERPC_EXCP_SDOOR]    = 0x00000A00;
3373    env->excp_vectors[POWERPC_EXCP_FU]       = 0x00000F60;
3374    env->excp_vectors[POWERPC_EXCP_HV_FU]    = 0x00000F80;
3375    env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
3376#endif
3377}
3378
3379static void init_excp_POWER9(CPUPPCState *env)
3380{
3381    init_excp_POWER8(env);
3382
3383#if !defined(CONFIG_USER_ONLY)
3384    env->excp_vectors[POWERPC_EXCP_HVIRT]    = 0x00000EA0;
3385#endif
3386}
3387
3388static void init_excp_POWER10(CPUPPCState *env)
3389{
3390    init_excp_POWER9(env);
3391}
3392
3393#endif
3394
3395/*****************************************************************************/
3396/* Power management enable checks                                            */
3397static int check_pow_none(CPUPPCState *env)
3398{
3399    return 0;
3400}
3401
3402static int check_pow_nocheck(CPUPPCState *env)
3403{
3404    return 1;
3405}
3406
3407static int check_pow_hid0(CPUPPCState *env)
3408{
3409    if (env->spr[SPR_HID0] & 0x00E00000) {
3410        return 1;
3411    }
3412
3413    return 0;
3414}
3415
3416static int check_pow_hid0_74xx(CPUPPCState *env)
3417{
3418    if (env->spr[SPR_HID0] & 0x00600000) {
3419        return 1;
3420    }
3421
3422    return 0;
3423}
3424
3425static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
3426{
3427    return true;
3428}
3429
3430#ifdef TARGET_PPC64
3431static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
3432{
3433    return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
3434}
3435#endif
3436
3437/*****************************************************************************/
3438/* PowerPC implementations definitions                                       */
3439
3440#define POWERPC_FAMILY(_name)                                               \
3441    static void                                                             \
3442    glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3443                                                                            \
3444    static const TypeInfo                                                   \
3445    glue(glue(ppc_, _name), _cpu_family_type_info) = {                      \
3446        .name = stringify(_name) "-family-" TYPE_POWERPC_CPU,               \
3447        .parent = TYPE_POWERPC_CPU,                                         \
3448        .abstract = true,                                                   \
3449        .class_init = glue(glue(ppc_, _name), _cpu_family_class_init),      \
3450    };                                                                      \
3451                                                                            \
3452    static void glue(glue(ppc_, _name), _cpu_family_register_types)(void)   \
3453    {                                                                       \
3454        type_register_static(                                               \
3455            &glue(glue(ppc_, _name), _cpu_family_type_info));               \
3456    }                                                                       \
3457                                                                            \
3458    type_init(glue(glue(ppc_, _name), _cpu_family_register_types))          \
3459                                                                            \
3460    static void glue(glue(ppc_, _name), _cpu_family_class_init)
3461
3462static void init_proc_401(CPUPPCState *env)
3463{
3464    gen_spr_40x(env);
3465    gen_spr_401_403(env);
3466    gen_spr_401(env);
3467    init_excp_4xx_real(env);
3468    env->dcache_line_size = 32;
3469    env->icache_line_size = 32;
3470    /* Allocate hardware IRQ controller */
3471    ppc40x_irq_init(env_archcpu(env));
3472
3473    SET_FIT_PERIOD(12, 16, 20, 24);
3474    SET_WDT_PERIOD(16, 20, 24, 28);
3475}
3476
3477POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3478{
3479    DeviceClass *dc = DEVICE_CLASS(oc);
3480    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3481
3482    dc->desc = "PowerPC 401";
3483    pcc->init_proc = init_proc_401;
3484    pcc->check_pow = check_pow_nocheck;
3485    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3486                       PPC_WRTEE | PPC_DCR |
3487                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3488                       PPC_CACHE_DCBZ |
3489                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3490                       PPC_4xx_COMMON | PPC_40x_EXCP;
3491    pcc->msr_mask = (1ull << MSR_KEY) |
3492                    (1ull << MSR_POW) |
3493                    (1ull << MSR_CE) |
3494                    (1ull << MSR_ILE) |
3495                    (1ull << MSR_EE) |
3496                    (1ull << MSR_PR) |
3497                    (1ull << MSR_ME) |
3498                    (1ull << MSR_DE) |
3499                    (1ull << MSR_LE);
3500    pcc->mmu_model = POWERPC_MMU_REAL;
3501    pcc->excp_model = POWERPC_EXCP_40x;
3502    pcc->bus_model = PPC_FLAGS_INPUT_401;
3503    pcc->bfd_mach = bfd_mach_ppc_403;
3504    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3505                 POWERPC_FLAG_BUS_CLK;
3506}
3507
3508static void init_proc_401x2(CPUPPCState *env)
3509{
3510    gen_spr_40x(env);
3511    gen_spr_401_403(env);
3512    gen_spr_401x2(env);
3513    gen_spr_compress(env);
3514    /* Memory management */
3515#if !defined(CONFIG_USER_ONLY)
3516    env->nb_tlb = 64;
3517    env->nb_ways = 1;
3518    env->id_tlbs = 0;
3519    env->tlb_type = TLB_EMB;
3520#endif
3521    init_excp_4xx_softmmu(env);
3522    env->dcache_line_size = 32;
3523    env->icache_line_size = 32;
3524    /* Allocate hardware IRQ controller */
3525    ppc40x_irq_init(env_archcpu(env));
3526
3527    SET_FIT_PERIOD(12, 16, 20, 24);
3528    SET_WDT_PERIOD(16, 20, 24, 28);
3529}
3530
3531POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3532{
3533    DeviceClass *dc = DEVICE_CLASS(oc);
3534    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3535
3536    dc->desc = "PowerPC 401x2";
3537    pcc->init_proc = init_proc_401x2;
3538    pcc->check_pow = check_pow_nocheck;
3539    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3540                       PPC_DCR | PPC_WRTEE |
3541                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3542                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3543                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3544                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3545                       PPC_4xx_COMMON | PPC_40x_EXCP;
3546    pcc->msr_mask = (1ull << 20) |
3547                    (1ull << MSR_KEY) |
3548                    (1ull << MSR_POW) |
3549                    (1ull << MSR_CE) |
3550                    (1ull << MSR_ILE) |
3551                    (1ull << MSR_EE) |
3552                    (1ull << MSR_PR) |
3553                    (1ull << MSR_ME) |
3554                    (1ull << MSR_DE) |
3555                    (1ull << MSR_IR) |
3556                    (1ull << MSR_DR) |
3557                    (1ull << MSR_LE);
3558    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3559    pcc->excp_model = POWERPC_EXCP_40x;
3560    pcc->bus_model = PPC_FLAGS_INPUT_401;
3561    pcc->bfd_mach = bfd_mach_ppc_403;
3562    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3563                 POWERPC_FLAG_BUS_CLK;
3564}
3565
3566static void init_proc_401x3(CPUPPCState *env)
3567{
3568    gen_spr_40x(env);
3569    gen_spr_401_403(env);
3570    gen_spr_401(env);
3571    gen_spr_401x2(env);
3572    gen_spr_compress(env);
3573    init_excp_4xx_softmmu(env);
3574    env->dcache_line_size = 32;
3575    env->icache_line_size = 32;
3576    /* Allocate hardware IRQ controller */
3577    ppc40x_irq_init(env_archcpu(env));
3578
3579    SET_FIT_PERIOD(12, 16, 20, 24);
3580    SET_WDT_PERIOD(16, 20, 24, 28);
3581}
3582
3583POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3584{
3585    DeviceClass *dc = DEVICE_CLASS(oc);
3586    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3587
3588    dc->desc = "PowerPC 401x3";
3589    pcc->init_proc = init_proc_401x3;
3590    pcc->check_pow = check_pow_nocheck;
3591    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3592                       PPC_DCR | PPC_WRTEE |
3593                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3594                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3595                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3596                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3597                       PPC_4xx_COMMON | PPC_40x_EXCP;
3598    pcc->msr_mask = (1ull << 20) |
3599                    (1ull << MSR_KEY) |
3600                    (1ull << MSR_POW) |
3601                    (1ull << MSR_CE) |
3602                    (1ull << MSR_ILE) |
3603                    (1ull << MSR_EE) |
3604                    (1ull << MSR_PR) |
3605                    (1ull << MSR_ME) |
3606                    (1ull << MSR_DWE) |
3607                    (1ull << MSR_DE) |
3608                    (1ull << MSR_IR) |
3609                    (1ull << MSR_DR) |
3610                    (1ull << MSR_LE);
3611    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3612    pcc->excp_model = POWERPC_EXCP_40x;
3613    pcc->bus_model = PPC_FLAGS_INPUT_401;
3614    pcc->bfd_mach = bfd_mach_ppc_403;
3615    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3616                 POWERPC_FLAG_BUS_CLK;
3617}
3618
3619static void init_proc_IOP480(CPUPPCState *env)
3620{
3621    gen_spr_40x(env);
3622    gen_spr_401_403(env);
3623    gen_spr_401x2(env);
3624    gen_spr_compress(env);
3625    /* Memory management */
3626#if !defined(CONFIG_USER_ONLY)
3627    env->nb_tlb = 64;
3628    env->nb_ways = 1;
3629    env->id_tlbs = 0;
3630    env->tlb_type = TLB_EMB;
3631#endif
3632    init_excp_4xx_softmmu(env);
3633    env->dcache_line_size = 32;
3634    env->icache_line_size = 32;
3635    /* Allocate hardware IRQ controller */
3636    ppc40x_irq_init(env_archcpu(env));
3637
3638    SET_FIT_PERIOD(8, 12, 16, 20);
3639    SET_WDT_PERIOD(16, 20, 24, 28);
3640}
3641
3642POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3643{
3644    DeviceClass *dc = DEVICE_CLASS(oc);
3645    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3646
3647    dc->desc = "IOP480";
3648    pcc->init_proc = init_proc_IOP480;
3649    pcc->check_pow = check_pow_nocheck;
3650    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3651                       PPC_DCR | PPC_WRTEE |
3652                       PPC_CACHE | PPC_CACHE_ICBI |  PPC_40x_ICBT |
3653                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3654                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3655                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3656                       PPC_4xx_COMMON | PPC_40x_EXCP;
3657    pcc->msr_mask = (1ull << 20) |
3658                    (1ull << MSR_KEY) |
3659                    (1ull << MSR_POW) |
3660                    (1ull << MSR_CE) |
3661                    (1ull << MSR_ILE) |
3662                    (1ull << MSR_EE) |
3663                    (1ull << MSR_PR) |
3664                    (1ull << MSR_ME) |
3665                    (1ull << MSR_DE) |
3666                    (1ull << MSR_IR) |
3667                    (1ull << MSR_DR) |
3668                    (1ull << MSR_LE);
3669    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3670    pcc->excp_model = POWERPC_EXCP_40x;
3671    pcc->bus_model = PPC_FLAGS_INPUT_401;
3672    pcc->bfd_mach = bfd_mach_ppc_403;
3673    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3674                 POWERPC_FLAG_BUS_CLK;
3675}
3676
3677static void init_proc_403(CPUPPCState *env)
3678{
3679    gen_spr_40x(env);
3680    gen_spr_401_403(env);
3681    gen_spr_403(env);
3682    gen_spr_403_real(env);
3683    init_excp_4xx_real(env);
3684    env->dcache_line_size = 32;
3685    env->icache_line_size = 32;
3686    /* Allocate hardware IRQ controller */
3687    ppc40x_irq_init(env_archcpu(env));
3688
3689    SET_FIT_PERIOD(8, 12, 16, 20);
3690    SET_WDT_PERIOD(16, 20, 24, 28);
3691}
3692
3693POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3694{
3695    DeviceClass *dc = DEVICE_CLASS(oc);
3696    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3697
3698    dc->desc = "PowerPC 403";
3699    pcc->init_proc = init_proc_403;
3700    pcc->check_pow = check_pow_nocheck;
3701    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3702                       PPC_DCR | PPC_WRTEE |
3703                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3704                       PPC_CACHE_DCBZ |
3705                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3706                       PPC_4xx_COMMON | PPC_40x_EXCP;
3707    pcc->msr_mask = (1ull << MSR_POW) |
3708                    (1ull << MSR_CE) |
3709                    (1ull << MSR_ILE) |
3710                    (1ull << MSR_EE) |
3711                    (1ull << MSR_PR) |
3712                    (1ull << MSR_ME) |
3713                    (1ull << MSR_PE) |
3714                    (1ull << MSR_PX) |
3715                    (1ull << MSR_LE);
3716    pcc->mmu_model = POWERPC_MMU_REAL;
3717    pcc->excp_model = POWERPC_EXCP_40x;
3718    pcc->bus_model = PPC_FLAGS_INPUT_401;
3719    pcc->bfd_mach = bfd_mach_ppc_403;
3720    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3721                 POWERPC_FLAG_BUS_CLK;
3722}
3723
3724static void init_proc_403GCX(CPUPPCState *env)
3725{
3726    gen_spr_40x(env);
3727    gen_spr_401_403(env);
3728    gen_spr_403(env);
3729    gen_spr_403_real(env);
3730    gen_spr_403_mmu(env);
3731    /* Bus access control */
3732    /* not emulated, as QEMU never does speculative access */
3733    spr_register(env, SPR_40x_SGR, "SGR",
3734                 SPR_NOACCESS, SPR_NOACCESS,
3735                 &spr_read_generic, &spr_write_generic,
3736                 0xFFFFFFFF);
3737    /* not emulated, as QEMU do not emulate caches */
3738    spr_register(env, SPR_40x_DCWR, "DCWR",
3739                 SPR_NOACCESS, SPR_NOACCESS,
3740                 &spr_read_generic, &spr_write_generic,
3741                 0x00000000);
3742    /* Memory management */
3743#if !defined(CONFIG_USER_ONLY)
3744    env->nb_tlb = 64;
3745    env->nb_ways = 1;
3746    env->id_tlbs = 0;
3747    env->tlb_type = TLB_EMB;
3748#endif
3749    init_excp_4xx_softmmu(env);
3750    env->dcache_line_size = 32;
3751    env->icache_line_size = 32;
3752    /* Allocate hardware IRQ controller */
3753    ppc40x_irq_init(env_archcpu(env));
3754
3755    SET_FIT_PERIOD(8, 12, 16, 20);
3756    SET_WDT_PERIOD(16, 20, 24, 28);
3757}
3758
3759POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3760{
3761    DeviceClass *dc = DEVICE_CLASS(oc);
3762    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3763
3764    dc->desc = "PowerPC 403 GCX";
3765    pcc->init_proc = init_proc_403GCX;
3766    pcc->check_pow = check_pow_nocheck;
3767    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3768                       PPC_DCR | PPC_WRTEE |
3769                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3770                       PPC_CACHE_DCBZ |
3771                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3772                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3773                       PPC_4xx_COMMON | PPC_40x_EXCP;
3774    pcc->msr_mask = (1ull << MSR_POW) |
3775                    (1ull << MSR_CE) |
3776                    (1ull << MSR_ILE) |
3777                    (1ull << MSR_EE) |
3778                    (1ull << MSR_PR) |
3779                    (1ull << MSR_ME) |
3780                    (1ull << MSR_PE) |
3781                    (1ull << MSR_PX) |
3782                    (1ull << MSR_LE);
3783    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3784    pcc->excp_model = POWERPC_EXCP_40x;
3785    pcc->bus_model = PPC_FLAGS_INPUT_401;
3786    pcc->bfd_mach = bfd_mach_ppc_403;
3787    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3788                 POWERPC_FLAG_BUS_CLK;
3789}
3790
3791static void init_proc_405(CPUPPCState *env)
3792{
3793    /* Time base */
3794    gen_tbl(env);
3795    gen_spr_40x(env);
3796    gen_spr_405(env);
3797    /* Bus access control */
3798    /* not emulated, as QEMU never does speculative access */
3799    spr_register(env, SPR_40x_SGR, "SGR",
3800                 SPR_NOACCESS, SPR_NOACCESS,
3801                 &spr_read_generic, &spr_write_generic,
3802                 0xFFFFFFFF);
3803    /* not emulated, as QEMU do not emulate caches */
3804    spr_register(env, SPR_40x_DCWR, "DCWR",
3805                 SPR_NOACCESS, SPR_NOACCESS,
3806                 &spr_read_generic, &spr_write_generic,
3807                 0x00000000);
3808    /* Memory management */
3809#if !defined(CONFIG_USER_ONLY)
3810    env->nb_tlb = 64;
3811    env->nb_ways = 1;
3812    env->id_tlbs = 0;
3813    env->tlb_type = TLB_EMB;
3814#endif
3815    init_excp_4xx_softmmu(env);
3816    env->dcache_line_size = 32;
3817    env->icache_line_size = 32;
3818    /* Allocate hardware IRQ controller */
3819    ppc40x_irq_init(env_archcpu(env));
3820
3821    SET_FIT_PERIOD(8, 12, 16, 20);
3822    SET_WDT_PERIOD(16, 20, 24, 28);
3823}
3824
3825POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3826{
3827    DeviceClass *dc = DEVICE_CLASS(oc);
3828    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3829
3830    dc->desc = "PowerPC 405";
3831    pcc->init_proc = init_proc_405;
3832    pcc->check_pow = check_pow_nocheck;
3833    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3834                       PPC_DCR | PPC_WRTEE |
3835                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3836                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3837                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3838                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3839                       PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3840    pcc->msr_mask = (1ull << MSR_POW) |
3841                    (1ull << MSR_CE) |
3842                    (1ull << MSR_EE) |
3843                    (1ull << MSR_PR) |
3844                    (1ull << MSR_FP) |
3845                    (1ull << MSR_DWE) |
3846                    (1ull << MSR_DE) |
3847                    (1ull << MSR_IR) |
3848                    (1ull << MSR_DR);
3849    pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3850    pcc->excp_model = POWERPC_EXCP_40x;
3851    pcc->bus_model = PPC_FLAGS_INPUT_405;
3852    pcc->bfd_mach = bfd_mach_ppc_403;
3853    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3854                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3855}
3856
3857static void init_proc_440EP(CPUPPCState *env)
3858{
3859    /* Time base */
3860    gen_tbl(env);
3861    gen_spr_BookE(env, 0x000000000000FFFFULL);
3862    gen_spr_440(env);
3863    gen_spr_usprgh(env);
3864    /* Processor identification */
3865    spr_register(env, SPR_BOOKE_PIR, "PIR",
3866                 SPR_NOACCESS, SPR_NOACCESS,
3867                 &spr_read_generic, &spr_write_pir,
3868                 0x00000000);
3869    /* XXX : not implemented */
3870    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3871                 SPR_NOACCESS, SPR_NOACCESS,
3872                 &spr_read_generic, &spr_write_generic,
3873                 0x00000000);
3874    /* XXX : not implemented */
3875    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3876                 SPR_NOACCESS, SPR_NOACCESS,
3877                 &spr_read_generic, &spr_write_generic,
3878                 0x00000000);
3879    /* XXX : not implemented */
3880    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3881                 SPR_NOACCESS, SPR_NOACCESS,
3882                 &spr_read_generic, &spr_write_generic,
3883                 0x00000000);
3884    /* XXX : not implemented */
3885    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3886                 SPR_NOACCESS, SPR_NOACCESS,
3887                 &spr_read_generic, &spr_write_generic,
3888                 0x00000000);
3889    /* XXX : not implemented */
3890    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3891                 SPR_NOACCESS, SPR_NOACCESS,
3892                 &spr_read_generic, &spr_write_generic,
3893                 0x00000000);
3894    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3895                 SPR_NOACCESS, SPR_NOACCESS,
3896                 &spr_read_generic, &spr_write_generic,
3897                 0x00000000);
3898    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3899                 SPR_NOACCESS, SPR_NOACCESS,
3900                 &spr_read_generic, &spr_write_generic,
3901                 0x00000000);
3902    /* XXX : not implemented */
3903    spr_register(env, SPR_440_CCR1, "CCR1",
3904                 SPR_NOACCESS, SPR_NOACCESS,
3905                 &spr_read_generic, &spr_write_generic,
3906                 0x00000000);
3907    /* Memory management */
3908#if !defined(CONFIG_USER_ONLY)
3909    env->nb_tlb = 64;
3910    env->nb_ways = 1;
3911    env->id_tlbs = 0;
3912    env->tlb_type = TLB_EMB;
3913#endif
3914    init_excp_BookE(env);
3915    env->dcache_line_size = 32;
3916    env->icache_line_size = 32;
3917    ppc40x_irq_init(env_archcpu(env));
3918
3919    SET_FIT_PERIOD(12, 16, 20, 24);
3920    SET_WDT_PERIOD(20, 24, 28, 32);
3921}
3922
3923POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3924{
3925    DeviceClass *dc = DEVICE_CLASS(oc);
3926    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3927
3928    dc->desc = "PowerPC 440 EP";
3929    pcc->init_proc = init_proc_440EP;
3930    pcc->check_pow = check_pow_nocheck;
3931    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3932                       PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3933                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3934                       PPC_FLOAT_STFIWX |
3935                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3936                       PPC_CACHE | PPC_CACHE_ICBI |
3937                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3938                       PPC_MEM_TLBSYNC | PPC_MFTB |
3939                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3940                       PPC_440_SPEC;
3941    pcc->msr_mask = (1ull << MSR_POW) |
3942                    (1ull << MSR_CE) |
3943                    (1ull << MSR_EE) |
3944                    (1ull << MSR_PR) |
3945                    (1ull << MSR_FP) |
3946                    (1ull << MSR_ME) |
3947                    (1ull << MSR_FE0) |
3948                    (1ull << MSR_DWE) |
3949                    (1ull << MSR_DE) |
3950                    (1ull << MSR_FE1) |
3951                    (1ull << MSR_IR) |
3952                    (1ull << MSR_DR);
3953    pcc->mmu_model = POWERPC_MMU_BOOKE;
3954    pcc->excp_model = POWERPC_EXCP_BOOKE;
3955    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3956    pcc->bfd_mach = bfd_mach_ppc_403;
3957    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3958                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3959}
3960
3961POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
3962{
3963    DeviceClass *dc = DEVICE_CLASS(oc);
3964    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3965
3966    dc->desc = "PowerPC 460 EX";
3967    pcc->init_proc = init_proc_440EP;
3968    pcc->check_pow = check_pow_nocheck;
3969    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3970                       PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3971                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3972                       PPC_FLOAT_STFIWX |
3973                       PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
3974                       PPC_CACHE | PPC_CACHE_ICBI |
3975                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3976                       PPC_MEM_TLBSYNC | PPC_MFTB |
3977                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3978                       PPC_440_SPEC;
3979    pcc->msr_mask = (1ull << MSR_POW) |
3980                    (1ull << MSR_CE) |
3981                    (1ull << MSR_EE) |
3982                    (1ull << MSR_PR) |
3983                    (1ull << MSR_FP) |
3984                    (1ull << MSR_ME) |
3985                    (1ull << MSR_FE0) |
3986                    (1ull << MSR_DWE) |
3987                    (1ull << MSR_DE) |
3988                    (1ull << MSR_FE1) |
3989                    (1ull << MSR_IR) |
3990                    (1ull << MSR_DR);
3991    pcc->mmu_model = POWERPC_MMU_BOOKE;
3992    pcc->excp_model = POWERPC_EXCP_BOOKE;
3993    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3994    pcc->bfd_mach = bfd_mach_ppc_403;
3995    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3996                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3997}
3998
3999static void init_proc_440GP(CPUPPCState *env)
4000{

4001    /* Time base */
4002    gen_tbl(env);
4003    gen_spr_BookE(env, 0x000000000000FFFFULL);
4004    gen_spr_440(env);
4005    gen_spr_usprgh(env);
4006    /* Processor identification */
4007    spr_register(env, SPR_BOOKE_PIR, "PIR",
4008                 SPR_NOACCESS, SPR_NOACCESS,
4009                 &spr_read_generic, &spr_write_pir,
4010                 0x00000000);
4011    /* XXX : not implemented */
4012    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4013                 SPR_NOACCESS, SPR_NOACCESS,
4014                 &spr_read_generic, &spr_write_generic,
4015                 0x00000000);
4016    /* XXX : not implemented */
4017    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4018                 SPR_NOACCESS, SPR_NOACCESS,
4019                 &spr_read_generic, &spr_write_generic,
4020                 0x00000000);
4021    /* XXX : not implemented */
4022    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4023                 SPR_NOACCESS, SPR_NOACCESS,
4024                 &spr_read_generic, &spr_write_generic,
4025                 0x00000000);
4026    /* XXX : not implemented */
4027    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4028                 SPR_NOACCESS, SPR_NOACCESS,
4029                 &spr_read_generic, &spr_write_generic,
4030                 0x00000000);
4031    /* Memory management */
4032#if !defined(CONFIG_USER_ONLY)
4033    env->nb_tlb = 64;
4034    env->nb_ways = 1;
4035    env->id_tlbs = 0;
4036    env->tlb_type = TLB_EMB;
4037#endif
4038    init_excp_BookE(env);
4039    env->dcache_line_size = 32;
4040    env->icache_line_size = 32;
4041    /* XXX: TODO: allocate internal IRQ controller */
4042
4043    SET_FIT_PERIOD(12, 16, 20, 24);
4044    SET_WDT_PERIOD(20, 24, 28, 32);
4045}
4046
4047POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
4048{
4049    DeviceClass *dc = DEVICE_CLASS(oc);
4050    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4051
4052    dc->desc = "PowerPC 440 GP";
4053    pcc->init_proc = init_proc_440GP;
4054    pcc->check_pow = check_pow_nocheck;
4055    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4056                       PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
4057                       PPC_CACHE | PPC_CACHE_ICBI |
4058                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4059                       PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
4060                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4061                       PPC_440_SPEC;
4062    pcc->msr_mask = (1ull << MSR_POW) |
4063                    (1ull << MSR_CE) |
4064                    (1ull << MSR_EE) |
4065                    (1ull << MSR_PR) |
4066                    (1ull << MSR_FP) |
4067                    (1ull << MSR_ME) |
4068                    (1ull << MSR_FE0) |
4069                    (1ull << MSR_DWE) |
4070                    (1ull << MSR_DE) |
4071                    (1ull << MSR_FE1) |
4072                    (1ull << MSR_IR) |
4073                    (1ull << MSR_DR);
4074    pcc->mmu_model = POWERPC_MMU_BOOKE;
4075    pcc->excp_model = POWERPC_EXCP_BOOKE;
4076    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4077    pcc->bfd_mach = bfd_mach_ppc_403;
4078    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4079                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4080}
4081
4082static void init_proc_440x4(CPUPPCState *env)
4083{
4084    /* Time base */
4085    gen_tbl(env);
4086    gen_spr_BookE(env, 0x000000000000FFFFULL);
4087    gen_spr_440(env);
4088    gen_spr_usprgh(env);
4089    /* Processor identification */
4090    spr_register(env, SPR_BOOKE_PIR, "PIR",
4091                 SPR_NOACCESS, SPR_NOACCESS,
4092                 &spr_read_generic, &spr_write_pir,
4093                 0x00000000);
4094    /* XXX : not implemented */
4095    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4096                 SPR_NOACCESS, SPR_NOACCESS,
4097                 &spr_read_generic, &spr_write_generic,
4098                 0x00000000);
4099    /* XXX : not implemented */
4100    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4101                 SPR_NOACCESS, SPR_NOACCESS,
4102                 &spr_read_generic, &spr_write_generic,
4103                 0x00000000);
4104    /* XXX : not implemented */
4105    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4106                 SPR_NOACCESS, SPR_NOACCESS,
4107                 &spr_read_generic, &spr_write_generic,
4108                 0x00000000);
4109    /* XXX : not implemented */
4110    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4111                 SPR_NOACCESS, SPR_NOACCESS,
4112                 &spr_read_generic, &spr_write_generic,
4113                 0x00000000);
4114    /* Memory management */
4115#if !defined(CONFIG_USER_ONLY)
4116    env->nb_tlb = 64;
4117    env->nb_ways = 1;
4118    env->id_tlbs = 0;
4119    env->tlb_type = TLB_EMB;
4120#endif
4121    init_excp_BookE(env);
4122    env->dcache_line_size = 32;
4123    env->icache_line_size = 32;
4124    /* XXX: TODO: allocate internal IRQ controller */
4125
4126    SET_FIT_PERIOD(12, 16, 20, 24);
4127    SET_WDT_PERIOD(20, 24, 28, 32);
4128}
4129
4130POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
4131{
4132    DeviceClass *dc = DEVICE_CLASS(oc);
4133    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4134
4135    dc->desc = "PowerPC 440x4";
4136    pcc->init_proc = init_proc_440x4;
4137    pcc->check_pow = check_pow_nocheck;
4138    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4139                       PPC_DCR | PPC_WRTEE |
4140                       PPC_CACHE | PPC_CACHE_ICBI |
4141                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4142                       PPC_MEM_TLBSYNC | PPC_MFTB |
4143                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4144                       PPC_440_SPEC;
4145    pcc->msr_mask = (1ull << MSR_POW) |
4146                    (1ull << MSR_CE) |
4147                    (1ull << MSR_EE) |
4148                    (1ull << MSR_PR) |
4149                    (1ull << MSR_FP) |
4150                    (1ull << MSR_ME) |
4151                    (1ull << MSR_FE0) |
4152                    (1ull << MSR_DWE) |
4153                    (1ull << MSR_DE) |
4154                    (1ull << MSR_FE1) |
4155                    (1ull << MSR_IR) |
4156                    (1ull << MSR_DR);
4157    pcc->mmu_model = POWERPC_MMU_BOOKE;
4158    pcc->excp_model = POWERPC_EXCP_BOOKE;
4159    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4160    pcc->bfd_mach = bfd_mach_ppc_403;
4161    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4162                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4163}
4164
4165static void init_proc_440x5(CPUPPCState *env)
4166{
4167    /* Time base */
4168    gen_tbl(env);
4169    gen_spr_BookE(env, 0x000000000000FFFFULL);
4170    gen_spr_440(env);
4171    gen_spr_usprgh(env);
4172    /* Processor identification */
4173    spr_register(env, SPR_BOOKE_PIR, "PIR",
4174                 SPR_NOACCESS, SPR_NOACCESS,
4175                 &spr_read_generic, &spr_write_pir,
4176                 0x00000000);
4177    /* XXX : not implemented */
4178    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4179                 SPR_NOACCESS, SPR_NOACCESS,
4180                 &spr_read_generic, &spr_write_generic,
4181                 0x00000000);
4182    /* XXX : not implemented */
4183    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4184                 SPR_NOACCESS, SPR_NOACCESS,
4185                 &spr_read_generic, &spr_write_generic,
4186                 0x00000000);
4187    /* XXX : not implemented */
4188    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4189                 SPR_NOACCESS, SPR_NOACCESS,
4190                 &spr_read_generic, &spr_write_generic,
4191                 0x00000000);
4192    /* XXX : not implemented */
4193    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4194                 SPR_NOACCESS, SPR_NOACCESS,
4195                 &spr_read_generic, &spr_write_generic,
4196                 0x00000000);
4197    /* XXX : not implemented */
4198    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4199                 SPR_NOACCESS, SPR_NOACCESS,
4200                 &spr_read_generic, &spr_write_generic,
4201                 0x00000000);
4202    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4203                 SPR_NOACCESS, SPR_NOACCESS,
4204                 &spr_read_generic, &spr_write_generic,
4205                 0x00000000);
4206    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4207                 SPR_NOACCESS, SPR_NOACCESS,
4208                 &spr_read_generic, &spr_write_generic,
4209                 0x00000000);
4210    /* XXX : not implemented */
4211    spr_register(env, SPR_440_CCR1, "CCR1",
4212                 SPR_NOACCESS, SPR_NOACCESS,
4213                 &spr_read_generic, &spr_write_generic,
4214                 0x00000000);
4215    /* Memory management */
4216#if !defined(CONFIG_USER_ONLY)
4217    env->nb_tlb = 64;
4218    env->nb_ways = 1;
4219    env->id_tlbs = 0;
4220    env->tlb_type = TLB_EMB;
4221#endif
4222    init_excp_BookE(env);
4223    env->dcache_line_size = 32;
4224    env->icache_line_size = 32;
4225    ppc40x_irq_init(env_archcpu(env));
4226
4227    SET_FIT_PERIOD(12, 16, 20, 24);
4228    SET_WDT_PERIOD(20, 24, 28, 32);
4229}
4230
4231POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
4232{
4233    DeviceClass *dc = DEVICE_CLASS(oc);
4234    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4235
4236    dc->desc = "PowerPC 440x5";
4237    pcc->init_proc = init_proc_440x5;
4238    pcc->check_pow = check_pow_nocheck;
4239    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4240                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4241                       PPC_CACHE | PPC_CACHE_ICBI |
4242                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4243                       PPC_MEM_TLBSYNC | PPC_MFTB |
4244                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4245                       PPC_440_SPEC;
4246    pcc->msr_mask = (1ull << MSR_POW) |
4247                    (1ull << MSR_CE) |
4248                    (1ull << MSR_EE) |
4249                    (1ull << MSR_PR) |
4250                    (1ull << MSR_FP) |
4251                    (1ull << MSR_ME) |
4252                    (1ull << MSR_FE0) |
4253                    (1ull << MSR_DWE) |
4254                    (1ull << MSR_DE) |
4255                    (1ull << MSR_FE1) |
4256                    (1ull << MSR_IR) |
4257                    (1ull << MSR_DR);
4258    pcc->mmu_model = POWERPC_MMU_BOOKE;
4259    pcc->excp_model = POWERPC_EXCP_BOOKE;
4260    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4261    pcc->bfd_mach = bfd_mach_ppc_403;
4262    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4263                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4264}
4265
4266POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
4267{
4268    DeviceClass *dc = DEVICE_CLASS(oc);
4269    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4270
4271    dc->desc = "PowerPC 440x5 with double precision FPU";
4272    pcc->init_proc = init_proc_440x5;
4273    pcc->check_pow = check_pow_nocheck;
4274    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4275                       PPC_FLOAT | PPC_FLOAT_FSQRT |
4276                       PPC_FLOAT_STFIWX |
4277                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4278                       PPC_CACHE | PPC_CACHE_ICBI |
4279                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4280                       PPC_MEM_TLBSYNC | PPC_MFTB |
4281                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4282                       PPC_440_SPEC;
4283    pcc->insns_flags2 = PPC2_FP_CVT_S64;
4284    pcc->msr_mask = (1ull << MSR_POW) |
4285                    (1ull << MSR_CE) |
4286                    (1ull << MSR_EE) |
4287                    (1ull << MSR_PR) |
4288                    (1ull << MSR_FP) |
4289                    (1ull << MSR_ME) |
4290                    (1ull << MSR_FE0) |
4291                    (1ull << MSR_DWE) |
4292                    (1ull << MSR_DE) |
4293                    (1ull << MSR_FE1) |
4294                    (1ull << MSR_IR) |
4295                    (1ull << MSR_DR);
4296    pcc->mmu_model = POWERPC_MMU_BOOKE;
4297    pcc->excp_model = POWERPC_EXCP_BOOKE;
4298    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4299    pcc->bfd_mach = bfd_mach_ppc_403;
4300    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4301                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4302}
4303
4304static void init_proc_MPC5xx(CPUPPCState *env)
4305{
4306    /* Time base */
4307    gen_tbl(env);
4308    gen_spr_5xx_8xx(env);
4309    gen_spr_5xx(env);
4310    init_excp_MPC5xx(env);
4311    env->dcache_line_size = 32;
4312    env->icache_line_size = 32;
4313    /* XXX: TODO: allocate internal IRQ controller */
4314}
4315
4316POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4317{
4318    DeviceClass *dc = DEVICE_CLASS(oc);
4319    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4320
4321    dc->desc = "Freescale 5xx cores (aka RCPU)";
4322    pcc->init_proc = init_proc_MPC5xx;
4323    pcc->check_pow = check_pow_none;
4324    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4325                       PPC_MEM_EIEIO | PPC_MEM_SYNC |
4326                       PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4327                       PPC_MFTB;
4328    pcc->msr_mask = (1ull << MSR_ILE) |
4329                    (1ull << MSR_EE) |
4330                    (1ull << MSR_PR) |
4331                    (1ull << MSR_FP) |
4332                    (1ull << MSR_ME) |
4333                    (1ull << MSR_FE0) |
4334                    (1ull << MSR_SE) |
4335                    (1ull << MSR_DE) |
4336                    (1ull << MSR_FE1) |
4337                    (1ull << MSR_EP) |
4338                    (1ull << MSR_RI) |
4339                    (1ull << MSR_LE);
4340    pcc->mmu_model = POWERPC_MMU_REAL;
4341    pcc->excp_model = POWERPC_EXCP_603;
4342    pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4343    pcc->bfd_mach = bfd_mach_ppc_505;
4344    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4345                 POWERPC_FLAG_BUS_CLK;
4346}
4347
4348static void init_proc_MPC8xx(CPUPPCState *env)
4349{
4350    /* Time base */
4351    gen_tbl(env);
4352    gen_spr_5xx_8xx(env);
4353    gen_spr_8xx(env);
4354    init_excp_MPC8xx(env);
4355    env->dcache_line_size = 32;
4356    env->icache_line_size = 32;
4357    /* XXX: TODO: allocate internal IRQ controller */
4358}
4359
4360POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4361{
4362    DeviceClass *dc = DEVICE_CLASS(oc);
4363    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4364
4365    dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4366    pcc->init_proc = init_proc_MPC8xx;
4367    pcc->check_pow = check_pow_none;
4368    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING  |
4369                       PPC_MEM_EIEIO | PPC_MEM_SYNC |
4370                       PPC_CACHE_ICBI | PPC_MFTB;
4371    pcc->msr_mask = (1ull << MSR_ILE) |
4372                    (1ull << MSR_EE) |
4373                    (1ull << MSR_PR) |
4374                    (1ull << MSR_FP) |
4375                    (1ull << MSR_ME) |
4376                    (1ull << MSR_SE) |
4377                    (1ull << MSR_DE) |
4378                    (1ull << MSR_EP) |
4379                    (1ull << MSR_IR) |
4380                    (1ull << MSR_DR) |
4381                    (1ull << MSR_RI) |
4382                    (1ull << MSR_LE);
4383    pcc->mmu_model = POWERPC_MMU_MPC8xx;
4384    pcc->excp_model = POWERPC_EXCP_603;
4385    pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4386    pcc->bfd_mach = bfd_mach_ppc_860;
4387    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4388                 POWERPC_FLAG_BUS_CLK;
4389}
4390
4391/* Freescale 82xx cores (aka PowerQUICC-II)                                  */
4392
4393static void init_proc_G2(CPUPPCState *env)
4394{
4395    gen_spr_ne_601(env);
4396    gen_spr_sdr1(env);
4397    gen_spr_G2_755(env);
4398    gen_spr_G2(env);
4399    /* Time base */
4400    gen_tbl(env);
4401    /* External access control */
4402    /* XXX : not implemented */
4403    spr_register(env, SPR_EAR, "EAR",
4404                 SPR_NOACCESS, SPR_NOACCESS,
4405                 &spr_read_generic, &spr_write_generic,
4406                 0x00000000);
4407    /* Hardware implementation register */
4408    /* XXX : not implemented */
4409    spr_register(env, SPR_HID0, "HID0",
4410                 SPR_NOACCESS, SPR_NOACCESS,
4411                 &spr_read_generic, &spr_write_generic,
4412                 0x00000000);
4413    /* XXX : not implemented */
4414    spr_register(env, SPR_HID1, "HID1",
4415                 SPR_NOACCESS, SPR_NOACCESS,
4416                 &spr_read_generic, &spr_write_generic,
4417                 0x00000000);
4418    /* XXX : not implemented */
4419    spr_register(env, SPR_HID2, "HID2",
4420                 SPR_NOACCESS, SPR_NOACCESS,
4421                 &spr_read_generic, &spr_write_generic,
4422                 0x00000000);
4423    /* Memory management */
4424    gen_low_BATs(env);
4425    gen_high_BATs(env);
4426    gen_6xx_7xx_soft_tlb(env, 64, 2);
4427    init_excp_G2(env);
4428    env->dcache_line_size = 32;
4429    env->icache_line_size = 32;
4430    /* Allocate hardware IRQ controller */
4431    ppc6xx_irq_init(env_archcpu(env));
4432}
4433
4434POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4435{
4436    DeviceClass *dc = DEVICE_CLASS(oc);
4437    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4438
4439    dc->desc = "PowerPC G2";
4440    pcc->init_proc = init_proc_G2;
4441    pcc->check_pow = check_pow_hid0;
4442    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4443                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4444                       PPC_FLOAT_STFIWX |
4445                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4446                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4447                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4448                       PPC_SEGMENT | PPC_EXTERN;
4449    pcc->msr_mask = (1ull << MSR_POW) |
4450                    (1ull << MSR_TGPR) |
4451                    (1ull << MSR_EE) |
4452                    (1ull << MSR_PR) |
4453                    (1ull << MSR_FP) |
4454                    (1ull << MSR_ME) |
4455                    (1ull << MSR_FE0) |
4456                    (1ull << MSR_SE) |
4457                    (1ull << MSR_DE) |
4458                    (1ull << MSR_FE1) |
4459                    (1ull << MSR_AL) |
4460                    (1ull << MSR_EP) |
4461                    (1ull << MSR_IR) |
4462                    (1ull << MSR_DR) |
4463                    (1ull << MSR_RI);
4464    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4465    pcc->excp_model = POWERPC_EXCP_G2;
4466    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4467    pcc->bfd_mach = bfd_mach_ppc_ec603e;
4468    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4469                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4470}
4471
4472static void init_proc_G2LE(CPUPPCState *env)
4473{
4474    gen_spr_ne_601(env);
4475    gen_spr_sdr1(env);
4476    gen_spr_G2_755(env);
4477    gen_spr_G2(env);
4478    /* Time base */
4479    gen_tbl(env);
4480    /* External access control */
4481    /* XXX : not implemented */
4482    spr_register(env, SPR_EAR, "EAR",
4483                 SPR_NOACCESS, SPR_NOACCESS,
4484                 &spr_read_generic, &spr_write_generic,
4485                 0x00000000);
4486    /* Hardware implementation register */
4487    /* XXX : not implemented */
4488    spr_register(env, SPR_HID0, "HID0",
4489                 SPR_NOACCESS, SPR_NOACCESS,
4490                 &spr_read_generic, &spr_write_generic,
4491                 0x00000000);
4492    /* XXX : not implemented */
4493    spr_register(env, SPR_HID1, "HID1",
4494                 SPR_NOACCESS, SPR_NOACCESS,
4495                 &spr_read_generic, &spr_write_generic,
4496                 0x00000000);
4497    /* XXX : not implemented */
4498    spr_register(env, SPR_HID2, "HID2",
4499                 SPR_NOACCESS, SPR_NOACCESS,
4500                 &spr_read_generic, &spr_write_generic,
4501                 0x00000000);
4502
4503    /* Memory management */
4504    gen_low_BATs(env);
4505    gen_high_BATs(env);
4506    gen_6xx_7xx_soft_tlb(env, 64, 2);
4507    init_excp_G2(env);
4508    env->dcache_line_size = 32;
4509    env->icache_line_size = 32;
4510    /* Allocate hardware IRQ controller */
4511    ppc6xx_irq_init(env_archcpu(env));
4512}
4513
4514POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4515{
4516    DeviceClass *dc = DEVICE_CLASS(oc);
4517    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4518
4519    dc->desc = "PowerPC G2LE";
4520    pcc->init_proc = init_proc_G2LE;
4521    pcc->check_pow = check_pow_hid0;
4522    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4523                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4524                       PPC_FLOAT_STFIWX |
4525                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4526                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4527                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4528                       PPC_SEGMENT | PPC_EXTERN;
4529    pcc->msr_mask = (1ull << MSR_POW) |
4530                    (1ull << MSR_TGPR) |
4531                    (1ull << MSR_ILE) |
4532                    (1ull << MSR_EE) |
4533                    (1ull << MSR_PR) |
4534                    (1ull << MSR_FP) |
4535                    (1ull << MSR_ME) |
4536                    (1ull << MSR_FE0) |
4537                    (1ull << MSR_SE) |
4538                    (1ull << MSR_DE) |
4539                    (1ull << MSR_FE1) |
4540                    (1ull << MSR_AL) |
4541                    (1ull << MSR_EP) |
4542                    (1ull << MSR_IR) |
4543                    (1ull << MSR_DR) |
4544                    (1ull << MSR_RI) |
4545                    (1ull << MSR_LE);
4546    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4547    pcc->excp_model = POWERPC_EXCP_G2;
4548    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4549    pcc->bfd_mach = bfd_mach_ppc_ec603e;
4550    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4551                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4552}
4553
4554static void init_proc_e200(CPUPPCState *env)
4555{
4556    /* Time base */
4557    gen_tbl(env);
4558    gen_spr_BookE(env, 0x000000070000FFFFULL);
4559    /* XXX : not implemented */
4560    spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4561                 &spr_read_spefscr, &spr_write_spefscr,
4562                 &spr_read_spefscr, &spr_write_spefscr,
4563                 0x00000000);
4564    /* Memory management */
4565    gen_spr_BookE206(env, 0x0000005D, NULL, 0);
4566    /* XXX : not implemented */
4567    spr_register(env, SPR_HID0, "HID0",
4568                 SPR_NOACCESS, SPR_NOACCESS,
4569                 &spr_read_generic, &spr_write_generic,
4570                 0x00000000);
4571    /* XXX : not implemented */
4572    spr_register(env, SPR_HID1, "HID1",
4573                 SPR_NOACCESS, SPR_NOACCESS,
4574                 &spr_read_generic, &spr_write_generic,
4575                 0x00000000);
4576    /* XXX : not implemented */
4577    spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4578                 SPR_NOACCESS, SPR_NOACCESS,
4579                 &spr_read_generic, &spr_write_generic,
4580                 0x00000000);
4581    /* XXX : not implemented */
4582    spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4583                 SPR_NOACCESS, SPR_NOACCESS,
4584                 &spr_read_generic, &spr_write_generic,
4585                 0x00000000);
4586    /* XXX : not implemented */
4587    spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4588                 SPR_NOACCESS, SPR_NOACCESS,
4589                 &spr_read_generic, &spr_write_generic,
4590                 0x00000000);
4591    /* XXX : not implemented */
4592    spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4593                 SPR_NOACCESS, SPR_NOACCESS,
4594                 &spr_read_generic, &spr_write_generic,
4595                 0x00000000);
4596    /* XXX : not implemented */
4597    spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4598                 SPR_NOACCESS, SPR_NOACCESS,
4599                 &spr_read_generic, &spr_write_generic,
4600                 0x00000000);
4601    /* XXX : not implemented */
4602    spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4603                 &spr_read_generic, SPR_NOACCESS,
4604                 &spr_read_generic, SPR_NOACCESS,
4605                 0x00000000);
4606    /* XXX : not implemented */
4607    spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4608                 SPR_NOACCESS, SPR_NOACCESS,
4609                 &spr_read_generic, &spr_write_generic,
4610                 0x00000000);
4611    /* XXX : not implemented */
4612    spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4613                 SPR_NOACCESS, SPR_NOACCESS,
4614                 &spr_read_generic, &spr_write_generic,
4615                 0x00000000);
4616    /* XXX : not implemented */
4617    spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4618                 SPR_NOACCESS, SPR_NOACCESS,
4619                 &spr_read_generic, &spr_write_generic,
4620                 0x00000000);
4621    /* XXX : not implemented */
4622    spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4623                 SPR_NOACCESS, SPR_NOACCESS,
4624                 &spr_read_generic, &spr_write_generic,
4625                 0x00000000);
4626    /* XXX : not implemented */
4627    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4628                 SPR_NOACCESS, SPR_NOACCESS,
4629                 &spr_read_generic, &spr_write_generic,
4630                 0x00000000);
4631    /* XXX : not implemented */
4632    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4633                 SPR_NOACCESS, SPR_NOACCESS,
4634                 &spr_read_generic, &spr_write_generic,
4635                 0x00000000);
4636    /* XXX : not implemented */
4637    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4638                 SPR_NOACCESS, SPR_NOACCESS,
4639                 &spr_read_generic, &spr_write_generic,
4640                 0x00000000); /* TOFIX */
4641    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4642                 SPR_NOACCESS, SPR_NOACCESS,
4643                 &spr_read_generic, &spr_write_generic,
4644                 0x00000000);
4645    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4646                 SPR_NOACCESS, SPR_NOACCESS,
4647                 &spr_read_generic, &spr_write_generic,
4648                 0x00000000);
4649#if !defined(CONFIG_USER_ONLY)
4650    env->nb_tlb = 64;
4651    env->nb_ways = 1;
4652    env->id_tlbs = 0;
4653    env->tlb_type = TLB_EMB;
4654#endif
4655    init_excp_e200(env, 0xFFFF0000UL);
4656    env->dcache_line_size = 32;
4657    env->icache_line_size = 32;
4658    /* XXX: TODO: allocate internal IRQ controller */
4659}
4660
4661POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4662{
4663    DeviceClass *dc = DEVICE_CLASS(oc);
4664    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4665
4666    dc->desc = "e200 core";
4667    pcc->init_proc = init_proc_e200;
4668    pcc->check_pow = check_pow_hid0;
4669    /*
4670     * XXX: unimplemented instructions:
4671     * dcblc
4672     * dcbtlst
4673     * dcbtstls
4674     * icblc
4675     * icbtls
4676     * tlbivax
4677     * all SPE multiply-accumulate instructions
4678     */
4679    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4680                       PPC_SPE | PPC_SPE_SINGLE |
4681                       PPC_WRTEE | PPC_RFDI |
4682                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4683                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4684                       PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4685                       PPC_BOOKE;
4686    pcc->msr_mask = (1ull << MSR_UCLE) |
4687                    (1ull << MSR_SPE) |
4688                    (1ull << MSR_POW) |
4689                    (1ull << MSR_CE) |
4690                    (1ull << MSR_EE) |
4691                    (1ull << MSR_PR) |
4692                    (1ull << MSR_FP) |
4693                    (1ull << MSR_ME) |
4694                    (1ull << MSR_FE0) |
4695                    (1ull << MSR_DWE) |
4696                    (1ull << MSR_DE) |
4697                    (1ull << MSR_FE1) |
4698                    (1ull << MSR_IR) |
4699                    (1ull << MSR_DR);
4700    pcc->mmu_model = POWERPC_MMU_BOOKE206;
4701    pcc->excp_model = POWERPC_EXCP_BOOKE;
4702    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4703    pcc->bfd_mach = bfd_mach_ppc_860;
4704    pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4705                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4706                 POWERPC_FLAG_BUS_CLK;
4707}
4708
4709static void init_proc_e300(CPUPPCState *env)
4710{
4711    gen_spr_ne_601(env);
4712    gen_spr_sdr1(env);
4713    gen_spr_603(env);
4714    /* Time base */
4715    gen_tbl(env);
4716    /* hardware implementation registers */
4717    /* XXX : not implemented */
4718    spr_register(env, SPR_HID0, "HID0",
4719                 SPR_NOACCESS, SPR_NOACCESS,
4720                 &spr_read_generic, &spr_write_generic,
4721                 0x00000000);
4722    /* XXX : not implemented */
4723    spr_register(env, SPR_HID1, "HID1",
4724                 SPR_NOACCESS, SPR_NOACCESS,
4725                 &spr_read_generic, &spr_write_generic,
4726                 0x00000000);
4727    /* XXX : not implemented */
4728    spr_register(env, SPR_HID2, "HID2",
4729                 SPR_NOACCESS, SPR_NOACCESS,
4730                 &spr_read_generic, &spr_write_generic,
4731                 0x00000000);
4732    /* Breakpoints */
4733    /* XXX : not implemented */
4734    spr_register(env, SPR_DABR, "DABR",
4735                 SPR_NOACCESS, SPR_NOACCESS,
4736                 &spr_read_generic, &spr_write_generic,
4737                 0x00000000);
4738    /* XXX : not implemented */
4739    spr_register(env, SPR_DABR2, "DABR2",
4740                 SPR_NOACCESS, SPR_NOACCESS,
4741                 &spr_read_generic, &spr_write_generic,
4742                 0x00000000);
4743    /* XXX : not implemented */
4744    spr_register(env, SPR_IABR2, "IABR2",
4745                 SPR_NOACCESS, SPR_NOACCESS,
4746                 &spr_read_generic, &spr_write_generic,
4747                 0x00000000);
4748    /* XXX : not implemented */
4749    spr_register(env, SPR_IBCR, "IBCR",
4750                 SPR_NOACCESS, SPR_NOACCESS,
4751                 &spr_read_generic, &spr_write_generic,
4752                 0x00000000);
4753    /* XXX : not implemented */
4754    spr_register(env, SPR_DBCR, "DBCR",
4755                 SPR_NOACCESS, SPR_NOACCESS,
4756                 &spr_read_generic, &spr_write_generic,
4757                 0x00000000);
4758    /* Memory management */
4759    gen_low_BATs(env);
4760    gen_high_BATs(env);
4761    gen_6xx_7xx_soft_tlb(env, 64, 2);
4762    init_excp_603(env);
4763    env->dcache_line_size = 32;
4764    env->icache_line_size = 32;
4765    /* Allocate hardware IRQ controller */
4766    ppc6xx_irq_init(env_archcpu(env));
4767}
4768
4769POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4770{
4771    DeviceClass *dc = DEVICE_CLASS(oc);
4772    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4773
4774    dc->desc = "e300 core";
4775    pcc->init_proc = init_proc_e300;
4776    pcc->check_pow = check_pow_hid0;
4777    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4778                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4779                       PPC_FLOAT_STFIWX |
4780                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4781                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4782                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4783                       PPC_SEGMENT | PPC_EXTERN;
4784    pcc->msr_mask = (1ull << MSR_POW) |
4785                    (1ull << MSR_TGPR) |
4786                    (1ull << MSR_ILE) |
4787                    (1ull << MSR_EE) |
4788                    (1ull << MSR_PR) |
4789                    (1ull << MSR_FP) |
4790                    (1ull << MSR_ME) |
4791                    (1ull << MSR_FE0) |
4792                    (1ull << MSR_SE) |
4793                    (1ull << MSR_DE) |
4794                    (1ull << MSR_FE1) |
4795                    (1ull << MSR_AL) |
4796                    (1ull << MSR_EP) |
4797                    (1ull << MSR_IR) |
4798                    (1ull << MSR_DR) |
4799                    (1ull << MSR_RI) |
4800                    (1ull << MSR_LE);
4801    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4802    pcc->excp_model = POWERPC_EXCP_603;
4803    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4804    pcc->bfd_mach = bfd_mach_ppc_603;
4805    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4806                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4807}
4808
4809#if !defined(CONFIG_USER_ONLY)
4810static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
4811{
4812    TCGv val = tcg_temp_new();
4813    tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4814    gen_store_spr(SPR_BOOKE_MAS3, val);
4815    tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4816    gen_store_spr(SPR_BOOKE_MAS7, val);
4817    tcg_temp_free(val);
4818}
4819
4820static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
4821{
4822    TCGv mas7 = tcg_temp_new();
4823    TCGv mas3 = tcg_temp_new();
4824    gen_load_spr(mas7, SPR_BOOKE_MAS7);
4825    tcg_gen_shli_tl(mas7, mas7, 32);
4826    gen_load_spr(mas3, SPR_BOOKE_MAS3);
4827    tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4828    tcg_temp_free(mas3);
4829    tcg_temp_free(mas7);
4830}
4831
4832#endif
4833
4834enum fsl_e500_version {
4835    fsl_e500v1,
4836    fsl_e500v2,
4837    fsl_e500mc,
4838    fsl_e5500,
4839    fsl_e6500,
4840};
4841
4842static void init_proc_e500(CPUPPCState *env, int version)
4843{
4844    uint32_t tlbncfg[2];
4845    uint64_t ivor_mask;
4846    uint64_t ivpr_mask = 0xFFFF0000ULL;
4847    uint32_t l1cfg0 = 0x3800  /* 8 ways */
4848                    | 0x0020; /* 32 kb */
4849    uint32_t l1cfg1 = 0x3800  /* 8 ways */
4850                    | 0x0020; /* 32 kb */
4851    uint32_t mmucfg = 0;
4852#if !defined(CONFIG_USER_ONLY)
4853    int i;
4854#endif
4855
4856    /* Time base */
4857    gen_tbl(env);
4858    /*
4859     * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4860     *     complain when accessing them.
4861     * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4862     */
4863    switch (version) {
4864    case fsl_e500v1:
4865    case fsl_e500v2:
4866    default:
4867        ivor_mask = 0x0000000F0000FFFFULL;
4868        break;
4869    case fsl_e500mc:
4870    case fsl_e5500:
4871        ivor_mask = 0x000003FE0000FFFFULL;
4872        break;
4873    case fsl_e6500:
4874        ivor_mask = 0x000003FF0000FFFFULL;
4875        break;
4876    }
4877    gen_spr_BookE(env, ivor_mask);
4878    gen_spr_usprg3(env);
4879    /* Processor identification */
4880    spr_register(env, SPR_BOOKE_PIR, "PIR",
4881                 SPR_NOACCESS, SPR_NOACCESS,
4882                 &spr_read_generic, &spr_write_pir,
4883                 0x00000000);
4884    /* XXX : not implemented */
4885    spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4886                 &spr_read_spefscr, &spr_write_spefscr,
4887                 &spr_read_spefscr, &spr_write_spefscr,
4888                 0x00000000);
4889#if !defined(CONFIG_USER_ONLY)
4890    /* Memory management */
4891    env->nb_pids = 3;
4892    env->nb_ways = 2;
4893    env->id_tlbs = 0;
4894    switch (version) {
4895    case fsl_e500v1:
4896        tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4897        tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4898        break;
4899    case fsl_e500v2:
4900        tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4901        tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4902        break;
4903    case fsl_e500mc:
4904    case fsl_e5500:
4905        tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4906        tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4907        break;
4908    case fsl_e6500:
4909        mmucfg = 0x6510B45;
4910        env->nb_pids = 1;
4911        tlbncfg[0] = 0x08052400;
4912        tlbncfg[1] = 0x40028040;
4913        break;
4914    default:
4915        cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
4916                  env->spr[SPR_PVR]);
4917    }
4918#endif
4919    /* Cache sizes */
4920    switch (version) {
4921    case fsl_e500v1:
4922    case fsl_e500v2:
4923        env->dcache_line_size = 32;
4924        env->icache_line_size = 32;
4925        break;
4926    case fsl_e500mc:
4927    case fsl_e5500:
4928        env->dcache_line_size = 64;
4929        env->icache_line_size = 64;
4930        l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4931        l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4932        break;
4933    case fsl_e6500:
4934        env->dcache_line_size = 32;
4935        env->icache_line_size = 32;
4936        l1cfg0 |= 0x0F83820;
4937        l1cfg1 |= 0x0B83820;
4938        break;
4939    default:
4940        cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
4941                  env->spr[SPR_PVR]);
4942    }
4943    gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
4944    /* XXX : not implemented */
4945    spr_register(env, SPR_HID0, "HID0",
4946                 SPR_NOACCESS, SPR_NOACCESS,
4947                 &spr_read_generic, &spr_write_generic,
4948                 0x00000000);
4949    /* XXX : not implemented */
4950    spr_register(env, SPR_HID1, "HID1",
4951                 SPR_NOACCESS, SPR_NOACCESS,
4952                 &spr_read_generic, &spr_write_generic,
4953                 0x00000000);
4954    /* XXX : not implemented */
4955    spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4956                 SPR_NOACCESS, SPR_NOACCESS,
4957                 &spr_read_generic, &spr_write_generic,
4958                 0x00000000);
4959    /* XXX : not implemented */
4960    spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4961                 SPR_NOACCESS, SPR_NOACCESS,
4962                 &spr_read_generic, &spr_write_generic,
4963                 0x00000000);
4964    /* XXX : not implemented */
4965    spr_register(env, SPR_Exxx_MCAR, "MCAR",
4966                 SPR_NOACCESS, SPR_NOACCESS,
4967                 &spr_read_generic, &spr_write_generic,
4968                 0x00000000);
4969    /* XXX : not implemented */
4970    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4971                 SPR_NOACCESS, SPR_NOACCESS,
4972                 &spr_read_generic, &spr_write_generic,
4973                 0x00000000);
4974    /* XXX : not implemented */
4975    spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4976                 SPR_NOACCESS, SPR_NOACCESS,
4977                 &spr_read_generic, &spr_write_generic,
4978                 0x00000000);
4979    /* XXX : not implemented */
4980    spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4981                 SPR_NOACCESS, SPR_NOACCESS,
4982                 &spr_read_generic, &spr_write_generic,
4983                 0x00000000);
4984    /* XXX : not implemented */
4985    spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4986                 &spr_read_generic, SPR_NOACCESS,
4987                 &spr_read_generic, SPR_NOACCESS,
4988                 l1cfg0);
4989    spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4990                 &spr_read_generic, SPR_NOACCESS,
4991                 &spr_read_generic, SPR_NOACCESS,
4992                 l1cfg1);
4993    spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4994                 SPR_NOACCESS, SPR_NOACCESS,
4995                 &spr_read_generic, &spr_write_e500_l1csr0,
4996                 0x00000000);
4997    spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4998                 SPR_NOACCESS, SPR_NOACCESS,
4999                 &spr_read_generic, &spr_write_e500_l1csr1,
5000                 0x00000000);

5001    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
5002                 SPR_NOACCESS, SPR_NOACCESS,
5003                 &spr_read_generic, &spr_write_generic,
5004                 0x00000000);
5005    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
5006                 SPR_NOACCESS, SPR_NOACCESS,
5007                 &spr_read_generic, &spr_write_generic,
5008                 0x00000000);
5009    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5010                 SPR_NOACCESS, SPR_NOACCESS,
5011                 &spr_read_generic, &spr_write_booke206_mmucsr0,
5012                 0x00000000);
5013    spr_register(env, SPR_BOOKE_EPR, "EPR",
5014                 SPR_NOACCESS, SPR_NOACCESS,
5015                 &spr_read_generic, SPR_NOACCESS,
5016                 0x00000000);
5017    /* XXX better abstract into Emb.xxx features */
5018    if ((version == fsl_e5500) || (version == fsl_e6500)) {
5019        spr_register(env, SPR_BOOKE_EPCR, "EPCR",
5020                     SPR_NOACCESS, SPR_NOACCESS,
5021                     &spr_read_generic, &spr_write_generic,
5022                     0x00000000);
5023        spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
5024                     SPR_NOACCESS, SPR_NOACCESS,
5025                     &spr_read_mas73, &spr_write_mas73,
5026                     0x00000000);
5027        ivpr_mask = (target_ulong)~0xFFFFULL;
5028    }
5029
5030    if (version == fsl_e6500) {
5031        /* Thread identification */
5032        spr_register(env, SPR_TIR, "TIR",
5033                     SPR_NOACCESS, SPR_NOACCESS,
5034                     &spr_read_generic, SPR_NOACCESS,
5035                     0x00000000);
5036        spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
5037                     SPR_NOACCESS, SPR_NOACCESS,
5038                     &spr_read_generic, SPR_NOACCESS,
5039                     0x00000004);
5040        spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
5041                     SPR_NOACCESS, SPR_NOACCESS,
5042                     &spr_read_generic, SPR_NOACCESS,
5043                     0x7FFFFFFC);
5044    }
5045
5046#if !defined(CONFIG_USER_ONLY)
5047    env->nb_tlb = 0;
5048    env->tlb_type = TLB_MAS;
5049    for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
5050        env->nb_tlb += booke206_tlb_size(env, i);
5051    }
5052#endif
5053
5054    init_excp_e200(env, ivpr_mask);
5055    /* Allocate hardware IRQ controller */
5056    ppce500_irq_init(env_archcpu(env));
5057}
5058
5059static void init_proc_e500v1(CPUPPCState *env)
5060{
5061    init_proc_e500(env, fsl_e500v1);
5062}
5063
5064POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
5065{
5066    DeviceClass *dc = DEVICE_CLASS(oc);
5067    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5068
5069    dc->desc = "e500v1 core";
5070    pcc->init_proc = init_proc_e500v1;
5071    pcc->check_pow = check_pow_hid0;
5072    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5073                       PPC_SPE | PPC_SPE_SINGLE |
5074                       PPC_WRTEE | PPC_RFDI |
5075                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5076                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5077                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5078    pcc->insns_flags2 = PPC2_BOOKE206;
5079    pcc->msr_mask = (1ull << MSR_UCLE) |
5080                    (1ull << MSR_SPE) |
5081                    (1ull << MSR_POW) |
5082                    (1ull << MSR_CE) |
5083                    (1ull << MSR_EE) |
5084                    (1ull << MSR_PR) |
5085                    (1ull << MSR_FP) |
5086                    (1ull << MSR_ME) |
5087                    (1ull << MSR_FE0) |
5088                    (1ull << MSR_DWE) |
5089                    (1ull << MSR_DE) |
5090                    (1ull << MSR_FE1) |
5091                    (1ull << MSR_IR) |
5092                    (1ull << MSR_DR);
5093    pcc->mmu_model = POWERPC_MMU_BOOKE206;
5094    pcc->excp_model = POWERPC_EXCP_BOOKE;
5095    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5096    pcc->bfd_mach = bfd_mach_ppc_860;
5097    pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5098                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5099                 POWERPC_FLAG_BUS_CLK;
5100}
5101
5102static void init_proc_e500v2(CPUPPCState *env)
5103{
5104    init_proc_e500(env, fsl_e500v2);
5105}
5106
5107POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
5108{
5109    DeviceClass *dc = DEVICE_CLASS(oc);
5110    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5111
5112    dc->desc = "e500v2 core";
5113    pcc->init_proc = init_proc_e500v2;
5114    pcc->check_pow = check_pow_hid0;
5115    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5116                       PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
5117                       PPC_WRTEE | PPC_RFDI |
5118                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5119                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5120                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5121    pcc->insns_flags2 = PPC2_BOOKE206;
5122    pcc->msr_mask = (1ull << MSR_UCLE) |
5123                    (1ull << MSR_SPE) |
5124                    (1ull << MSR_POW) |
5125                    (1ull << MSR_CE) |
5126                    (1ull << MSR_EE) |
5127                    (1ull << MSR_PR) |
5128                    (1ull << MSR_FP) |
5129                    (1ull << MSR_ME) |
5130                    (1ull << MSR_FE0) |
5131                    (1ull << MSR_DWE) |
5132                    (1ull << MSR_DE) |
5133                    (1ull << MSR_FE1) |
5134                    (1ull << MSR_IR) |
5135                    (1ull << MSR_DR);
5136    pcc->mmu_model = POWERPC_MMU_BOOKE206;
5137    pcc->excp_model = POWERPC_EXCP_BOOKE;
5138    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5139    pcc->bfd_mach = bfd_mach_ppc_860;
5140    pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5141                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5142                 POWERPC_FLAG_BUS_CLK;
5143}
5144
5145static void init_proc_e500mc(CPUPPCState *env)
5146{
5147    init_proc_e500(env, fsl_e500mc);
5148}
5149
5150POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
5151{
5152    DeviceClass *dc = DEVICE_CLASS(oc);
5153    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5154
5155    dc->desc = "e500mc core";
5156    pcc->init_proc = init_proc_e500mc;
5157    pcc->check_pow = check_pow_none;
5158    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5159                       PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5160                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5161                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5162                       PPC_FLOAT | PPC_FLOAT_FRES |
5163                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5164                       PPC_FLOAT_STFIWX | PPC_WAIT |
5165                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5166    pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
5167    pcc->msr_mask = (1ull << MSR_GS) |
5168                    (1ull << MSR_UCLE) |
5169                    (1ull << MSR_CE) |
5170                    (1ull << MSR_EE) |
5171                    (1ull << MSR_PR) |
5172                    (1ull << MSR_FP) |
5173                    (1ull << MSR_ME) |
5174                    (1ull << MSR_FE0) |
5175                    (1ull << MSR_DE) |
5176                    (1ull << MSR_FE1) |
5177                    (1ull << MSR_IR) |
5178                    (1ull << MSR_DR) |
5179                    (1ull << MSR_PX) |
5180                    (1ull << MSR_RI);
5181    pcc->mmu_model = POWERPC_MMU_BOOKE206;
5182    pcc->excp_model = POWERPC_EXCP_BOOKE;
5183    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5184    /* FIXME: figure out the correct flag for e500mc */
5185    pcc->bfd_mach = bfd_mach_ppc_e500;
5186    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5187                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5188}
5189
5190#ifdef TARGET_PPC64
5191static void init_proc_e5500(CPUPPCState *env)
5192{
5193    init_proc_e500(env, fsl_e5500);
5194}
5195
5196POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
5197{
5198    DeviceClass *dc = DEVICE_CLASS(oc);
5199    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5200
5201    dc->desc = "e5500 core";
5202    pcc->init_proc = init_proc_e5500;
5203    pcc->check_pow = check_pow_none;
5204    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5205                       PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5206                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5207                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5208                       PPC_FLOAT | PPC_FLOAT_FRES |
5209                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5210                       PPC_FLOAT_STFIWX | PPC_WAIT |
5211                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5212                       PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
5213    pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
5214                        PPC2_FP_CVT_S64;
5215    pcc->msr_mask = (1ull << MSR_CM) |
5216                    (1ull << MSR_GS) |
5217                    (1ull << MSR_UCLE) |
5218                    (1ull << MSR_CE) |
5219                    (1ull << MSR_EE) |
5220                    (1ull << MSR_PR) |
5221                    (1ull << MSR_FP) |
5222                    (1ull << MSR_ME) |
5223                    (1ull << MSR_FE0) |
5224                    (1ull << MSR_DE) |
5225                    (1ull << MSR_FE1) |
5226                    (1ull << MSR_IR) |
5227                    (1ull << MSR_DR) |
5228                    (1ull << MSR_PX) |
5229                    (1ull << MSR_RI);
5230    pcc->mmu_model = POWERPC_MMU_BOOKE206;
5231    pcc->excp_model = POWERPC_EXCP_BOOKE;
5232    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5233    /* FIXME: figure out the correct flag for e5500 */
5234    pcc->bfd_mach = bfd_mach_ppc_e500;
5235    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5236                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5237}
5238
5239static void init_proc_e6500(CPUPPCState *env)
5240{
5241    init_proc_e500(env, fsl_e6500);
5242}
5243
5244POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
5245{
5246    DeviceClass *dc = DEVICE_CLASS(oc);
5247    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5248
5249    dc->desc = "e6500 core";
5250    pcc->init_proc = init_proc_e6500;
5251    pcc->check_pow = check_pow_none;
5252    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5253                       PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5254                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5255                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5256                       PPC_FLOAT | PPC_FLOAT_FRES |
5257                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5258                       PPC_FLOAT_STFIWX | PPC_WAIT |
5259                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5260                       PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
5261    pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
5262                        PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
5263    pcc->msr_mask = (1ull << MSR_CM) |
5264                    (1ull << MSR_GS) |
5265                    (1ull << MSR_UCLE) |
5266                    (1ull << MSR_CE) |
5267                    (1ull << MSR_EE) |
5268                    (1ull << MSR_PR) |
5269                    (1ull << MSR_FP) |
5270                    (1ull << MSR_ME) |
5271                    (1ull << MSR_FE0) |
5272                    (1ull << MSR_DE) |
5273                    (1ull << MSR_FE1) |
5274                    (1ull << MSR_IS) |
5275                    (1ull << MSR_DS) |
5276                    (1ull << MSR_PX) |
5277                    (1ull << MSR_RI) |
5278                    (1ull << MSR_VR);
5279    pcc->mmu_model = POWERPC_MMU_BOOKE206;
5280    pcc->excp_model = POWERPC_EXCP_BOOKE;
5281    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5282    pcc->bfd_mach = bfd_mach_ppc_e500;
5283    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5284                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
5285}
5286
5287#endif
5288
5289/* Non-embedded PowerPC                                                      */
5290
5291#define POWERPC_MSRR_601     (0x0000000000001040ULL)
5292
5293static void init_proc_601(CPUPPCState *env)
5294{
5295    gen_spr_ne_601(env);
5296    gen_spr_sdr1(env);
5297    gen_spr_601(env);
5298    /* Hardware implementation registers */
5299    /* XXX : not implemented */
5300    spr_register(env, SPR_HID0, "HID0",
5301                 SPR_NOACCESS, SPR_NOACCESS,
5302                 &spr_read_generic, &spr_write_hid0_601,
5303                 0x80010080);
5304    /* XXX : not implemented */
5305    spr_register(env, SPR_HID1, "HID1",
5306                 SPR_NOACCESS, SPR_NOACCESS,
5307                 &spr_read_generic, &spr_write_generic,
5308                 0x00000000);
5309    /* XXX : not implemented */
5310    spr_register(env, SPR_601_HID2, "HID2",
5311                 SPR_NOACCESS, SPR_NOACCESS,
5312                 &spr_read_generic, &spr_write_generic,
5313                 0x00000000);
5314    /* XXX : not implemented */
5315    spr_register(env, SPR_601_HID5, "HID5",
5316                 SPR_NOACCESS, SPR_NOACCESS,
5317                 &spr_read_generic, &spr_write_generic,
5318                 0x00000000);
5319    /* Memory management */
5320    init_excp_601(env);
5321    /*
5322     * XXX: beware that dcache line size is 64
5323     *      but dcbz uses 32 bytes "sectors"
5324     * XXX: this breaks clcs instruction !
5325     */
5326    env->dcache_line_size = 32;
5327    env->icache_line_size = 64;
5328    /* Allocate hardware IRQ controller */
5329    ppc6xx_irq_init(env_archcpu(env));
5330}
5331
5332POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
5333{
5334    DeviceClass *dc = DEVICE_CLASS(oc);
5335    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5336
5337    dc->desc = "PowerPC 601";
5338    pcc->init_proc = init_proc_601;
5339    pcc->check_pow = check_pow_none;
5340    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5341                       PPC_FLOAT |
5342                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5343                       PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5344                       PPC_SEGMENT | PPC_EXTERN;
5345    pcc->msr_mask = (1ull << MSR_EE) |
5346                    (1ull << MSR_PR) |
5347                    (1ull << MSR_FP) |
5348                    (1ull << MSR_ME) |
5349                    (1ull << MSR_FE0) |
5350                    (1ull << MSR_SE) |
5351                    (1ull << MSR_FE1) |
5352                    (1ull << MSR_EP) |
5353                    (1ull << MSR_IR) |
5354                    (1ull << MSR_DR);
5355    pcc->mmu_model = POWERPC_MMU_601;
5356#if defined(CONFIG_SOFTMMU)
5357    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5358#endif
5359    pcc->excp_model = POWERPC_EXCP_601;
5360    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5361    pcc->bfd_mach = bfd_mach_ppc_601;
5362    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5363}
5364
5365#define POWERPC_MSRR_601v    (0x0000000000001040ULL)
5366
5367static void init_proc_601v(CPUPPCState *env)
5368{
5369    init_proc_601(env);
5370    /* XXX : not implemented */
5371    spr_register(env, SPR_601_HID15, "HID15",
5372                 SPR_NOACCESS, SPR_NOACCESS,
5373                 &spr_read_generic, &spr_write_generic,
5374                 0x00000000);
5375}
5376
5377POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
5378{
5379    DeviceClass *dc = DEVICE_CLASS(oc);
5380    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5381
5382    dc->desc = "PowerPC 601v";
5383    pcc->init_proc = init_proc_601v;
5384    pcc->check_pow = check_pow_none;
5385    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5386                       PPC_FLOAT |
5387                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5388                       PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5389                       PPC_SEGMENT | PPC_EXTERN;
5390    pcc->msr_mask = (1ull << MSR_EE) |
5391                    (1ull << MSR_PR) |
5392                    (1ull << MSR_FP) |
5393                    (1ull << MSR_ME) |
5394                    (1ull << MSR_FE0) |
5395                    (1ull << MSR_SE) |
5396                    (1ull << MSR_FE1) |
5397                    (1ull << MSR_EP) |
5398                    (1ull << MSR_IR) |
5399                    (1ull << MSR_DR);
5400    pcc->mmu_model = POWERPC_MMU_601;
5401#if defined(CONFIG_SOFTMMU)
5402    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5403#endif
5404    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5405    pcc->bfd_mach = bfd_mach_ppc_601;
5406    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5407}
5408
5409static void init_proc_602(CPUPPCState *env)
5410{
5411    gen_spr_ne_601(env);
5412    gen_spr_sdr1(env);
5413    gen_spr_602(env);
5414    /* Time base */
5415    gen_tbl(env);
5416    /* hardware implementation registers */
5417    /* XXX : not implemented */
5418    spr_register(env, SPR_HID0, "HID0",
5419                 SPR_NOACCESS, SPR_NOACCESS,
5420                 &spr_read_generic, &spr_write_generic,
5421                 0x00000000);
5422    /* XXX : not implemented */
5423    spr_register(env, SPR_HID1, "HID1",
5424                 SPR_NOACCESS, SPR_NOACCESS,
5425                 &spr_read_generic, &spr_write_generic,
5426                 0x00000000);
5427    /* Memory management */
5428    gen_low_BATs(env);
5429    gen_6xx_7xx_soft_tlb(env, 64, 2);
5430    init_excp_602(env);
5431    env->dcache_line_size = 32;
5432    env->icache_line_size = 32;
5433    /* Allocate hardware IRQ controller */
5434    ppc6xx_irq_init(env_archcpu(env));
5435}
5436
5437POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5438{
5439    DeviceClass *dc = DEVICE_CLASS(oc);
5440    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5441
5442    dc->desc = "PowerPC 602";
5443    pcc->init_proc = init_proc_602;
5444    pcc->check_pow = check_pow_hid0;
5445    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5446                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5447                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5448                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5449                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5450                       PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5451                       PPC_SEGMENT | PPC_602_SPEC;
5452    pcc->msr_mask = (1ull << MSR_VSX) |
5453                    (1ull << MSR_SA) |
5454                    (1ull << MSR_POW) |
5455                    (1ull << MSR_TGPR) |
5456                    (1ull << MSR_ILE) |
5457                    (1ull << MSR_EE) |
5458                    (1ull << MSR_PR) |
5459                    (1ull << MSR_FP) |
5460                    (1ull << MSR_ME) |
5461                    (1ull << MSR_FE0) |
5462                    (1ull << MSR_SE) |
5463                    (1ull << MSR_DE) |
5464                    (1ull << MSR_FE1) |
5465                    (1ull << MSR_EP) |
5466                    (1ull << MSR_IR) |
5467                    (1ull << MSR_DR) |
5468                    (1ull << MSR_RI) |
5469                    (1ull << MSR_LE);
5470    /* XXX: 602 MMU is quite specific. Should add a special case */
5471    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5472    pcc->excp_model = POWERPC_EXCP_602;
5473    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5474    pcc->bfd_mach = bfd_mach_ppc_602;
5475    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5476                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5477}
5478
5479static void init_proc_603(CPUPPCState *env)
5480{
5481    gen_spr_ne_601(env);
5482    gen_spr_sdr1(env);
5483    gen_spr_603(env);
5484    /* Time base */
5485    gen_tbl(env);
5486    /* hardware implementation registers */
5487    /* XXX : not implemented */
5488    spr_register(env, SPR_HID0, "HID0",
5489                 SPR_NOACCESS, SPR_NOACCESS,
5490                 &spr_read_generic, &spr_write_generic,
5491                 0x00000000);
5492    /* XXX : not implemented */
5493    spr_register(env, SPR_HID1, "HID1",
5494                 SPR_NOACCESS, SPR_NOACCESS,
5495                 &spr_read_generic, &spr_write_generic,
5496                 0x00000000);
5497    /* Memory management */
5498    gen_low_BATs(env);
5499    gen_6xx_7xx_soft_tlb(env, 64, 2);
5500    init_excp_603(env);
5501    env->dcache_line_size = 32;
5502    env->icache_line_size = 32;
5503    /* Allocate hardware IRQ controller */
5504    ppc6xx_irq_init(env_archcpu(env));
5505}
5506
5507POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5508{
5509    DeviceClass *dc = DEVICE_CLASS(oc);
5510    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5511
5512    dc->desc = "PowerPC 603";
5513    pcc->init_proc = init_proc_603;
5514    pcc->check_pow = check_pow_hid0;
5515    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5516                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5517                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5518                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5519                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5520                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5521                       PPC_SEGMENT | PPC_EXTERN;
5522    pcc->msr_mask = (1ull << MSR_POW) |
5523                    (1ull << MSR_TGPR) |
5524                    (1ull << MSR_ILE) |
5525                    (1ull << MSR_EE) |
5526                    (1ull << MSR_PR) |
5527                    (1ull << MSR_FP) |
5528                    (1ull << MSR_ME) |
5529                    (1ull << MSR_FE0) |
5530                    (1ull << MSR_SE) |
5531                    (1ull << MSR_DE) |
5532                    (1ull << MSR_FE1) |
5533                    (1ull << MSR_EP) |
5534                    (1ull << MSR_IR) |
5535                    (1ull << MSR_DR) |
5536                    (1ull << MSR_RI) |
5537                    (1ull << MSR_LE);
5538    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5539    pcc->excp_model = POWERPC_EXCP_603;
5540    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5541    pcc->bfd_mach = bfd_mach_ppc_603;
5542    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5543                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5544}
5545
5546static void init_proc_603E(CPUPPCState *env)
5547{
5548    gen_spr_ne_601(env);
5549    gen_spr_sdr1(env);
5550    gen_spr_603(env);
5551    /* Time base */
5552    gen_tbl(env);
5553    /* hardware implementation registers */
5554    /* XXX : not implemented */
5555    spr_register(env, SPR_HID0, "HID0",
5556                 SPR_NOACCESS, SPR_NOACCESS,
5557                 &spr_read_generic, &spr_write_generic,
5558                 0x00000000);
5559    /* XXX : not implemented */
5560    spr_register(env, SPR_HID1, "HID1",
5561                 SPR_NOACCESS, SPR_NOACCESS,
5562                 &spr_read_generic, &spr_write_generic,
5563                 0x00000000);
5564    /* Memory management */
5565    gen_low_BATs(env);
5566    gen_6xx_7xx_soft_tlb(env, 64, 2);
5567    init_excp_603(env);
5568    env->dcache_line_size = 32;
5569    env->icache_line_size = 32;
5570    /* Allocate hardware IRQ controller */
5571    ppc6xx_irq_init(env_archcpu(env));
5572}
5573
5574POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5575{
5576    DeviceClass *dc = DEVICE_CLASS(oc);
5577    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5578
5579    dc->desc = "PowerPC 603e";
5580    pcc->init_proc = init_proc_603E;
5581    pcc->check_pow = check_pow_hid0;
5582    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5583                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5584                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5585                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5586                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5587                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5588                       PPC_SEGMENT | PPC_EXTERN;
5589    pcc->msr_mask = (1ull << MSR_POW) |
5590                    (1ull << MSR_TGPR) |
5591                    (1ull << MSR_ILE) |
5592                    (1ull << MSR_EE) |
5593                    (1ull << MSR_PR) |
5594                    (1ull << MSR_FP) |
5595                    (1ull << MSR_ME) |
5596                    (1ull << MSR_FE0) |
5597                    (1ull << MSR_SE) |
5598                    (1ull << MSR_DE) |
5599                    (1ull << MSR_FE1) |
5600                    (1ull << MSR_EP) |
5601                    (1ull << MSR_IR) |
5602                    (1ull << MSR_DR) |
5603                    (1ull << MSR_RI) |
5604                    (1ull << MSR_LE);
5605    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5606    pcc->excp_model = POWERPC_EXCP_603E;
5607    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5608    pcc->bfd_mach = bfd_mach_ppc_ec603e;
5609    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5610                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5611}
5612
5613static void init_proc_604(CPUPPCState *env)
5614{
5615    gen_spr_ne_601(env);
5616    gen_spr_sdr1(env);
5617    gen_spr_604(env);
5618    /* Time base */
5619    gen_tbl(env);
5620    /* Hardware implementation registers */
5621    /* XXX : not implemented */
5622    spr_register(env, SPR_HID0, "HID0",
5623                 SPR_NOACCESS, SPR_NOACCESS,
5624                 &spr_read_generic, &spr_write_generic,
5625                 0x00000000);
5626    /* Memory management */
5627    gen_low_BATs(env);
5628    init_excp_604(env);
5629    env->dcache_line_size = 32;
5630    env->icache_line_size = 32;
5631    /* Allocate hardware IRQ controller */
5632    ppc6xx_irq_init(env_archcpu(env));
5633}
5634
5635POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5636{
5637    DeviceClass *dc = DEVICE_CLASS(oc);
5638    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5639
5640    dc->desc = "PowerPC 604";
5641    pcc->init_proc = init_proc_604;
5642    pcc->check_pow = check_pow_nocheck;
5643    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5644                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5645                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5646                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5647                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5648                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5649                       PPC_SEGMENT | PPC_EXTERN;
5650    pcc->msr_mask = (1ull << MSR_POW) |
5651                    (1ull << MSR_ILE) |
5652                    (1ull << MSR_EE) |
5653                    (1ull << MSR_PR) |
5654                    (1ull << MSR_FP) |
5655                    (1ull << MSR_ME) |
5656                    (1ull << MSR_FE0) |
5657                    (1ull << MSR_SE) |
5658                    (1ull << MSR_DE) |
5659                    (1ull << MSR_FE1) |
5660                    (1ull << MSR_EP) |
5661                    (1ull << MSR_IR) |
5662                    (1ull << MSR_DR) |
5663                    (1ull << MSR_PMM) |
5664                    (1ull << MSR_RI) |
5665                    (1ull << MSR_LE);
5666    pcc->mmu_model = POWERPC_MMU_32B;
5667#if defined(CONFIG_SOFTMMU)
5668    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5669#endif
5670    pcc->excp_model = POWERPC_EXCP_604;
5671    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5672    pcc->bfd_mach = bfd_mach_ppc_604;
5673    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5674                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5675}
5676
5677static void init_proc_604E(CPUPPCState *env)
5678{
5679    gen_spr_ne_601(env);
5680    gen_spr_sdr1(env);
5681    gen_spr_604(env);
5682    /* XXX : not implemented */
5683    spr_register(env, SPR_7XX_MMCR1, "MMCR1",
5684                 SPR_NOACCESS, SPR_NOACCESS,
5685                 &spr_read_generic, &spr_write_generic,
5686                 0x00000000);
5687    /* XXX : not implemented */
5688    spr_register(env, SPR_7XX_PMC3, "PMC3",
5689                 SPR_NOACCESS, SPR_NOACCESS,
5690                 &spr_read_generic, &spr_write_generic,
5691                 0x00000000);
5692    /* XXX : not implemented */
5693    spr_register(env, SPR_7XX_PMC4, "PMC4",
5694                 SPR_NOACCESS, SPR_NOACCESS,
5695                 &spr_read_generic, &spr_write_generic,
5696                 0x00000000);
5697    /* Time base */
5698    gen_tbl(env);
5699    /* Hardware implementation registers */
5700    /* XXX : not implemented */
5701    spr_register(env, SPR_HID0, "HID0",
5702                 SPR_NOACCESS, SPR_NOACCESS,
5703                 &spr_read_generic, &spr_write_generic,
5704                 0x00000000);
5705    /* XXX : not implemented */
5706    spr_register(env, SPR_HID1, "HID1",
5707                 SPR_NOACCESS, SPR_NOACCESS,
5708                 &spr_read_generic, &spr_write_generic,
5709                 0x00000000);
5710    /* Memory management */
5711    gen_low_BATs(env);
5712    init_excp_604(env);
5713    env->dcache_line_size = 32;
5714    env->icache_line_size = 32;
5715    /* Allocate hardware IRQ controller */
5716    ppc6xx_irq_init(env_archcpu(env));
5717}
5718
5719POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5720{
5721    DeviceClass *dc = DEVICE_CLASS(oc);
5722    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5723
5724    dc->desc = "PowerPC 604E";
5725    pcc->init_proc = init_proc_604E;
5726    pcc->check_pow = check_pow_nocheck;
5727    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5728                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5729                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5730                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5731                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5732                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5733                       PPC_SEGMENT | PPC_EXTERN;
5734    pcc->msr_mask = (1ull << MSR_POW) |
5735                    (1ull << MSR_ILE) |
5736                    (1ull << MSR_EE) |
5737                    (1ull << MSR_PR) |
5738                    (1ull << MSR_FP) |
5739                    (1ull << MSR_ME) |
5740                    (1ull << MSR_FE0) |
5741                    (1ull << MSR_SE) |
5742                    (1ull << MSR_DE) |
5743                    (1ull << MSR_FE1) |
5744                    (1ull << MSR_EP) |
5745                    (1ull << MSR_IR) |
5746                    (1ull << MSR_DR) |
5747                    (1ull << MSR_PMM) |
5748                    (1ull << MSR_RI) |
5749                    (1ull << MSR_LE);
5750    pcc->mmu_model = POWERPC_MMU_32B;
5751#if defined(CONFIG_SOFTMMU)
5752    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5753#endif
5754    pcc->excp_model = POWERPC_EXCP_604;
5755    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5756    pcc->bfd_mach = bfd_mach_ppc_604;
5757    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5758                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5759}
5760
5761static void init_proc_740(CPUPPCState *env)
5762{
5763    gen_spr_ne_601(env);
5764    gen_spr_sdr1(env);
5765    gen_spr_7xx(env);
5766    /* Time base */
5767    gen_tbl(env);
5768    /* Thermal management */
5769    gen_spr_thrm(env);
5770    /* Hardware implementation registers */
5771    /* XXX : not implemented */
5772    spr_register(env, SPR_HID0, "HID0",
5773                 SPR_NOACCESS, SPR_NOACCESS,
5774                 &spr_read_generic, &spr_write_generic,
5775                 0x00000000);
5776    /* XXX : not implemented */
5777    spr_register(env, SPR_HID1, "HID1",
5778                 SPR_NOACCESS, SPR_NOACCESS,
5779                 &spr_read_generic, &spr_write_generic,
5780                 0x00000000);
5781    /* Memory management */
5782    gen_low_BATs(env);
5783    init_excp_7x0(env);
5784    env->dcache_line_size = 32;
5785    env->icache_line_size = 32;
5786    /* Allocate hardware IRQ controller */
5787    ppc6xx_irq_init(env_archcpu(env));
5788}
5789
5790POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5791{
5792    DeviceClass *dc = DEVICE_CLASS(oc);
5793    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5794
5795    dc->desc = "PowerPC 740";
5796    pcc->init_proc = init_proc_740;
5797    pcc->check_pow = check_pow_hid0;
5798    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5799                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5800                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5801                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5802                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5803                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5804                       PPC_SEGMENT | PPC_EXTERN;
5805    pcc->msr_mask = (1ull << MSR_POW) |
5806                    (1ull << MSR_ILE) |
5807                    (1ull << MSR_EE) |
5808                    (1ull << MSR_PR) |
5809                    (1ull << MSR_FP) |
5810                    (1ull << MSR_ME) |
5811                    (1ull << MSR_FE0) |
5812                    (1ull << MSR_SE) |
5813                    (1ull << MSR_DE) |
5814                    (1ull << MSR_FE1) |
5815                    (1ull << MSR_EP) |
5816                    (1ull << MSR_IR) |
5817                    (1ull << MSR_DR) |
5818                    (1ull << MSR_PMM) |
5819                    (1ull << MSR_RI) |
5820                    (1ull << MSR_LE);
5821    pcc->mmu_model = POWERPC_MMU_32B;
5822#if defined(CONFIG_SOFTMMU)
5823    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5824#endif
5825    pcc->excp_model = POWERPC_EXCP_7x0;
5826    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5827    pcc->bfd_mach = bfd_mach_ppc_750;
5828    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5829                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5830}
5831
5832static void init_proc_750(CPUPPCState *env)
5833{
5834    gen_spr_ne_601(env);
5835    gen_spr_sdr1(env);
5836    gen_spr_7xx(env);
5837    /* XXX : not implemented */
5838    spr_register(env, SPR_L2CR, "L2CR",
5839                 SPR_NOACCESS, SPR_NOACCESS,
5840                 &spr_read_generic, spr_access_nop,
5841                 0x00000000);
5842    /* Time base */
5843    gen_tbl(env);
5844    /* Thermal management */
5845    gen_spr_thrm(env);
5846    /* Hardware implementation registers */
5847    /* XXX : not implemented */
5848    spr_register(env, SPR_HID0, "HID0",
5849                 SPR_NOACCESS, SPR_NOACCESS,
5850                 &spr_read_generic, &spr_write_generic,
5851                 0x00000000);
5852    /* XXX : not implemented */
5853    spr_register(env, SPR_HID1, "HID1",
5854                 SPR_NOACCESS, SPR_NOACCESS,
5855                 &spr_read_generic, &spr_write_generic,
5856                 0x00000000);
5857    /* Memory management */
5858    gen_low_BATs(env);
5859    /*
5860     * XXX: high BATs are also present but are known to be bugged on
5861     *      die version 1.x
5862     */
5863    init_excp_7x0(env);
5864    env->dcache_line_size = 32;
5865    env->icache_line_size = 32;
5866    /* Allocate hardware IRQ controller */
5867    ppc6xx_irq_init(env_archcpu(env));
5868}
5869
5870POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5871{
5872    DeviceClass *dc = DEVICE_CLASS(oc);
5873    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5874
5875    dc->desc = "PowerPC 750";
5876    pcc->init_proc = init_proc_750;
5877    pcc->check_pow = check_pow_hid0;
5878    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5879                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5880                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5881                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5882                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5883                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5884                       PPC_SEGMENT | PPC_EXTERN;
5885    pcc->msr_mask = (1ull << MSR_POW) |
5886                    (1ull << MSR_ILE) |
5887                    (1ull << MSR_EE) |
5888                    (1ull << MSR_PR) |
5889                    (1ull << MSR_FP) |
5890                    (1ull << MSR_ME) |
5891                    (1ull << MSR_FE0) |
5892                    (1ull << MSR_SE) |
5893                    (1ull << MSR_DE) |
5894                    (1ull << MSR_FE1) |
5895                    (1ull << MSR_EP) |
5896                    (1ull << MSR_IR) |
5897                    (1ull << MSR_DR) |
5898                    (1ull << MSR_PMM) |
5899                    (1ull << MSR_RI) |
5900                    (1ull << MSR_LE);
5901    pcc->mmu_model = POWERPC_MMU_32B;
5902#if defined(CONFIG_SOFTMMU)
5903    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5904#endif
5905    pcc->excp_model = POWERPC_EXCP_7x0;
5906    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5907    pcc->bfd_mach = bfd_mach_ppc_750;
5908    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5909                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5910}
5911
5912static void init_proc_750cl(CPUPPCState *env)
5913{
5914    gen_spr_ne_601(env);
5915    gen_spr_sdr1(env);
5916    gen_spr_7xx(env);
5917    /* XXX : not implemented */
5918    spr_register(env, SPR_L2CR, "L2CR",
5919                 SPR_NOACCESS, SPR_NOACCESS,
5920                 &spr_read_generic, spr_access_nop,
5921                 0x00000000);
5922    /* Time base */
5923    gen_tbl(env);
5924    /* Thermal management */
5925    /* Those registers are fake on 750CL */
5926    spr_register(env, SPR_THRM1, "THRM1",
5927                 SPR_NOACCESS, SPR_NOACCESS,
5928                 &spr_read_generic, &spr_write_generic,
5929                 0x00000000);
5930    spr_register(env, SPR_THRM2, "THRM2",
5931                 SPR_NOACCESS, SPR_NOACCESS,
5932                 &spr_read_generic, &spr_write_generic,
5933                 0x00000000);
5934    spr_register(env, SPR_THRM3, "THRM3",
5935                 SPR_NOACCESS, SPR_NOACCESS,
5936                 &spr_read_generic, &spr_write_generic,
5937                 0x00000000);
5938    /* XXX: not implemented */
5939    spr_register(env, SPR_750_TDCL, "TDCL",
5940                 SPR_NOACCESS, SPR_NOACCESS,
5941                 &spr_read_generic, &spr_write_generic,
5942                 0x00000000);
5943    spr_register(env, SPR_750_TDCH, "TDCH",
5944                 SPR_NOACCESS, SPR_NOACCESS,
5945                 &spr_read_generic, &spr_write_generic,
5946                 0x00000000);
5947    /* DMA */
5948    /* XXX : not implemented */
5949    spr_register(env, SPR_750_WPAR, "WPAR",
5950                 SPR_NOACCESS, SPR_NOACCESS,
5951                 &spr_read_generic, &spr_write_generic,
5952                 0x00000000);
5953    spr_register(env, SPR_750_DMAL, "DMAL",
5954                 SPR_NOACCESS, SPR_NOACCESS,
5955                 &spr_read_generic, &spr_write_generic,
5956                 0x00000000);
5957    spr_register(env, SPR_750_DMAU, "DMAU",
5958                 SPR_NOACCESS, SPR_NOACCESS,
5959                 &spr_read_generic, &spr_write_generic,
5960                 0x00000000);
5961    /* Hardware implementation registers */
5962    /* XXX : not implemented */
5963    spr_register(env, SPR_HID0, "HID0",
5964                 SPR_NOACCESS, SPR_NOACCESS,
5965                 &spr_read_generic, &spr_write_generic,
5966                 0x00000000);
5967    /* XXX : not implemented */
5968    spr_register(env, SPR_HID1, "HID1",
5969                 SPR_NOACCESS, SPR_NOACCESS,
5970                 &spr_read_generic, &spr_write_generic,
5971                 0x00000000);
5972    /* XXX : not implemented */
5973    spr_register(env, SPR_750CL_HID2, "HID2",
5974                 SPR_NOACCESS, SPR_NOACCESS,
5975                 &spr_read_generic, &spr_write_generic,
5976                 0x00000000);
5977    /* XXX : not implemented */
5978    spr_register(env, SPR_750CL_HID4, "HID4",
5979                 SPR_NOACCESS, SPR_NOACCESS,
5980                 &spr_read_generic, &spr_write_generic,
5981                 0x00000000);
5982    /* Quantization registers */
5983    /* XXX : not implemented */
5984    spr_register(env, SPR_750_GQR0, "GQR0",
5985                 SPR_NOACCESS, SPR_NOACCESS,
5986                 &spr_read_generic, &spr_write_generic,
5987                 0x00000000);
5988    /* XXX : not implemented */
5989    spr_register(env, SPR_750_GQR1, "GQR1",
5990                 SPR_NOACCESS, SPR_NOACCESS,
5991                 &spr_read_generic, &spr_write_generic,
5992                 0x00000000);
5993    /* XXX : not implemented */
5994    spr_register(env, SPR_750_GQR2, "GQR2",
5995                 SPR_NOACCESS, SPR_NOACCESS,
5996                 &spr_read_generic, &spr_write_generic,
5997                 0x00000000);
5998    /* XXX : not implemented */
5999    spr_register(env, SPR_750_GQR3, "GQR3",
6000                 SPR_NOACCESS, SPR_NOACCESS,

6001                 &spr_read_generic, &spr_write_generic,
6002                 0x00000000);
6003    /* XXX : not implemented */
6004    spr_register(env, SPR_750_GQR4, "GQR4",
6005                 SPR_NOACCESS, SPR_NOACCESS,
6006                 &spr_read_generic, &spr_write_generic,
6007                 0x00000000);
6008    /* XXX : not implemented */
6009    spr_register(env, SPR_750_GQR5, "GQR5",
6010                 SPR_NOACCESS, SPR_NOACCESS,
6011                 &spr_read_generic, &spr_write_generic,
6012                 0x00000000);
6013    /* XXX : not implemented */
6014    spr_register(env, SPR_750_GQR6, "GQR6",
6015                 SPR_NOACCESS, SPR_NOACCESS,
6016                 &spr_read_generic, &spr_write_generic,
6017                 0x00000000);
6018    /* XXX : not implemented */
6019    spr_register(env, SPR_750_GQR7, "GQR7",
6020                 SPR_NOACCESS, SPR_NOACCESS,
6021                 &spr_read_generic, &spr_write_generic,
6022                 0x00000000);
6023    /* Memory management */
6024    gen_low_BATs(env);
6025    /* PowerPC 750cl has 8 DBATs and 8 IBATs */
6026    gen_high_BATs(env);
6027    init_excp_750cl(env);
6028    env->dcache_line_size = 32;
6029    env->icache_line_size = 32;
6030    /* Allocate hardware IRQ controller */
6031    ppc6xx_irq_init(env_archcpu(env));
6032}
6033
6034POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
6035{
6036    DeviceClass *dc = DEVICE_CLASS(oc);
6037    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6038
6039    dc->desc = "PowerPC 750 CL";
6040    pcc->init_proc = init_proc_750cl;
6041    pcc->check_pow = check_pow_hid0;
6042    /*
6043     * XXX: not implemented:
6044     * cache lock instructions:
6045     * dcbz_l
6046     * floating point paired instructions
6047     * psq_lux
6048     * psq_lx
6049     * psq_stux
6050     * psq_stx
6051     * ps_abs
6052     * ps_add
6053     * ps_cmpo0
6054     * ps_cmpo1
6055     * ps_cmpu0
6056     * ps_cmpu1
6057     * ps_div
6058     * ps_madd
6059     * ps_madds0
6060     * ps_madds1
6061     * ps_merge00
6062     * ps_merge01
6063     * ps_merge10
6064     * ps_merge11
6065     * ps_mr
6066     * ps_msub
6067     * ps_mul
6068     * ps_muls0
6069     * ps_muls1
6070     * ps_nabs
6071     * ps_neg
6072     * ps_nmadd
6073     * ps_nmsub
6074     * ps_res
6075     * ps_rsqrte
6076     * ps_sel
6077     * ps_sub
6078     * ps_sum0
6079     * ps_sum1
6080     */
6081    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6082                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6083                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6084                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6085                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6086                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6087                       PPC_SEGMENT | PPC_EXTERN;
6088    pcc->msr_mask = (1ull << MSR_POW) |
6089                    (1ull << MSR_ILE) |
6090                    (1ull << MSR_EE) |
6091                    (1ull << MSR_PR) |
6092                    (1ull << MSR_FP) |
6093                    (1ull << MSR_ME) |
6094                    (1ull << MSR_FE0) |
6095                    (1ull << MSR_SE) |
6096                    (1ull << MSR_DE) |
6097                    (1ull << MSR_FE1) |
6098                    (1ull << MSR_EP) |
6099                    (1ull << MSR_IR) |
6100                    (1ull << MSR_DR) |
6101                    (1ull << MSR_PMM) |
6102                    (1ull << MSR_RI) |
6103                    (1ull << MSR_LE);
6104    pcc->mmu_model = POWERPC_MMU_32B;
6105#if defined(CONFIG_SOFTMMU)
6106    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6107#endif
6108    pcc->excp_model = POWERPC_EXCP_7x0;
6109    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6110    pcc->bfd_mach = bfd_mach_ppc_750;
6111    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6112                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6113}
6114
6115static void init_proc_750cx(CPUPPCState *env)
6116{
6117    gen_spr_ne_601(env);
6118    gen_spr_sdr1(env);
6119    gen_spr_7xx(env);
6120    /* XXX : not implemented */
6121    spr_register(env, SPR_L2CR, "L2CR",
6122                 SPR_NOACCESS, SPR_NOACCESS,
6123                 &spr_read_generic, spr_access_nop,
6124                 0x00000000);
6125    /* Time base */
6126    gen_tbl(env);
6127    /* Thermal management */
6128    gen_spr_thrm(env);
6129    /* This register is not implemented but is present for compatibility */
6130    spr_register(env, SPR_SDA, "SDA",
6131                 SPR_NOACCESS, SPR_NOACCESS,
6132                 &spr_read_generic, &spr_write_generic,
6133                 0x00000000);
6134    /* Hardware implementation registers */
6135    /* XXX : not implemented */
6136    spr_register(env, SPR_HID0, "HID0",
6137                 SPR_NOACCESS, SPR_NOACCESS,
6138                 &spr_read_generic, &spr_write_generic,
6139                 0x00000000);
6140    /* XXX : not implemented */
6141    spr_register(env, SPR_HID1, "HID1",
6142                 SPR_NOACCESS, SPR_NOACCESS,
6143                 &spr_read_generic, &spr_write_generic,
6144                 0x00000000);
6145    /* Memory management */
6146    gen_low_BATs(env);
6147    /* PowerPC 750cx has 8 DBATs and 8 IBATs */
6148    gen_high_BATs(env);
6149    init_excp_750cx(env);
6150    env->dcache_line_size = 32;
6151    env->icache_line_size = 32;
6152    /* Allocate hardware IRQ controller */
6153    ppc6xx_irq_init(env_archcpu(env));
6154}
6155
6156POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
6157{
6158    DeviceClass *dc = DEVICE_CLASS(oc);
6159    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6160
6161    dc->desc = "PowerPC 750CX";
6162    pcc->init_proc = init_proc_750cx;
6163    pcc->check_pow = check_pow_hid0;
6164    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6165                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6166                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6167                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6168                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6169                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6170                       PPC_SEGMENT | PPC_EXTERN;
6171    pcc->msr_mask = (1ull << MSR_POW) |
6172                    (1ull << MSR_ILE) |
6173                    (1ull << MSR_EE) |
6174                    (1ull << MSR_PR) |
6175                    (1ull << MSR_FP) |
6176                    (1ull << MSR_ME) |
6177                    (1ull << MSR_FE0) |
6178                    (1ull << MSR_SE) |
6179                    (1ull << MSR_DE) |
6180                    (1ull << MSR_FE1) |
6181                    (1ull << MSR_EP) |
6182                    (1ull << MSR_IR) |
6183                    (1ull << MSR_DR) |
6184                    (1ull << MSR_PMM) |
6185                    (1ull << MSR_RI) |
6186                    (1ull << MSR_LE);
6187    pcc->mmu_model = POWERPC_MMU_32B;
6188#if defined(CONFIG_SOFTMMU)
6189    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6190#endif
6191    pcc->excp_model = POWERPC_EXCP_7x0;
6192    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6193    pcc->bfd_mach = bfd_mach_ppc_750;
6194    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6195                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6196}
6197
6198static void init_proc_750fx(CPUPPCState *env)
6199{
6200    gen_spr_ne_601(env);
6201    gen_spr_sdr1(env);
6202    gen_spr_7xx(env);
6203    /* XXX : not implemented */
6204    spr_register(env, SPR_L2CR, "L2CR",
6205                 SPR_NOACCESS, SPR_NOACCESS,
6206                 &spr_read_generic, spr_access_nop,
6207                 0x00000000);
6208    /* Time base */
6209    gen_tbl(env);
6210    /* Thermal management */
6211    gen_spr_thrm(env);
6212    /* XXX : not implemented */
6213    spr_register(env, SPR_750_THRM4, "THRM4",
6214                 SPR_NOACCESS, SPR_NOACCESS,
6215                 &spr_read_generic, &spr_write_generic,
6216                 0x00000000);
6217    /* Hardware implementation registers */
6218    /* XXX : not implemented */
6219    spr_register(env, SPR_HID0, "HID0",
6220                 SPR_NOACCESS, SPR_NOACCESS,
6221                 &spr_read_generic, &spr_write_generic,
6222                 0x00000000);
6223    /* XXX : not implemented */
6224    spr_register(env, SPR_HID1, "HID1",
6225                 SPR_NOACCESS, SPR_NOACCESS,
6226                 &spr_read_generic, &spr_write_generic,
6227                 0x00000000);
6228    /* XXX : not implemented */
6229    spr_register(env, SPR_750FX_HID2, "HID2",
6230                 SPR_NOACCESS, SPR_NOACCESS,
6231                 &spr_read_generic, &spr_write_generic,
6232                 0x00000000);
6233    /* Memory management */
6234    gen_low_BATs(env);
6235    /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6236    gen_high_BATs(env);
6237    init_excp_7x0(env);
6238    env->dcache_line_size = 32;
6239    env->icache_line_size = 32;
6240    /* Allocate hardware IRQ controller */
6241    ppc6xx_irq_init(env_archcpu(env));
6242}
6243
6244POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
6245{
6246    DeviceClass *dc = DEVICE_CLASS(oc);
6247    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6248
6249    dc->desc = "PowerPC 750FX";
6250    pcc->init_proc = init_proc_750fx;
6251    pcc->check_pow = check_pow_hid0;
6252    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6253                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6254                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6255                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6256                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6257                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6258                       PPC_SEGMENT | PPC_EXTERN;
6259    pcc->msr_mask = (1ull << MSR_POW) |
6260                    (1ull << MSR_ILE) |
6261                    (1ull << MSR_EE) |
6262                    (1ull << MSR_PR) |
6263                    (1ull << MSR_FP) |
6264                    (1ull << MSR_ME) |
6265                    (1ull << MSR_FE0) |
6266                    (1ull << MSR_SE) |
6267                    (1ull << MSR_DE) |
6268                    (1ull << MSR_FE1) |
6269                    (1ull << MSR_EP) |
6270                    (1ull << MSR_IR) |
6271                    (1ull << MSR_DR) |
6272                    (1ull << MSR_PMM) |
6273                    (1ull << MSR_RI) |
6274                    (1ull << MSR_LE);
6275    pcc->mmu_model = POWERPC_MMU_32B;
6276#if defined(CONFIG_SOFTMMU)
6277    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6278#endif
6279    pcc->excp_model = POWERPC_EXCP_7x0;
6280    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6281    pcc->bfd_mach = bfd_mach_ppc_750;
6282    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6283                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6284}
6285
6286static void init_proc_750gx(CPUPPCState *env)
6287{
6288    gen_spr_ne_601(env);
6289    gen_spr_sdr1(env);
6290    gen_spr_7xx(env);
6291    /* XXX : not implemented (XXX: different from 750fx) */
6292    spr_register(env, SPR_L2CR, "L2CR",
6293                 SPR_NOACCESS, SPR_NOACCESS,
6294                 &spr_read_generic, spr_access_nop,
6295                 0x00000000);
6296    /* Time base */
6297    gen_tbl(env);
6298    /* Thermal management */
6299    gen_spr_thrm(env);
6300    /* XXX : not implemented */
6301    spr_register(env, SPR_750_THRM4, "THRM4",
6302                 SPR_NOACCESS, SPR_NOACCESS,
6303                 &spr_read_generic, &spr_write_generic,
6304                 0x00000000);
6305    /* Hardware implementation registers */
6306    /* XXX : not implemented (XXX: different from 750fx) */
6307    spr_register(env, SPR_HID0, "HID0",
6308                 SPR_NOACCESS, SPR_NOACCESS,
6309                 &spr_read_generic, &spr_write_generic,
6310                 0x00000000);
6311    /* XXX : not implemented */
6312    spr_register(env, SPR_HID1, "HID1",
6313                 SPR_NOACCESS, SPR_NOACCESS,
6314                 &spr_read_generic, &spr_write_generic,
6315                 0x00000000);
6316    /* XXX : not implemented (XXX: different from 750fx) */
6317    spr_register(env, SPR_750FX_HID2, "HID2",
6318                 SPR_NOACCESS, SPR_NOACCESS,
6319                 &spr_read_generic, &spr_write_generic,
6320                 0x00000000);
6321    /* Memory management */
6322    gen_low_BATs(env);
6323    /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6324    gen_high_BATs(env);
6325    init_excp_7x0(env);
6326    env->dcache_line_size = 32;
6327    env->icache_line_size = 32;
6328    /* Allocate hardware IRQ controller */
6329    ppc6xx_irq_init(env_archcpu(env));
6330}
6331
6332POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
6333{
6334    DeviceClass *dc = DEVICE_CLASS(oc);
6335    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6336
6337    dc->desc = "PowerPC 750GX";
6338    pcc->init_proc = init_proc_750gx;
6339    pcc->check_pow = check_pow_hid0;
6340    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6341                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6342                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6343                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6344                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6345                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6346                       PPC_SEGMENT | PPC_EXTERN;
6347    pcc->msr_mask = (1ull << MSR_POW) |
6348                    (1ull << MSR_ILE) |
6349                    (1ull << MSR_EE) |
6350                    (1ull << MSR_PR) |
6351                    (1ull << MSR_FP) |
6352                    (1ull << MSR_ME) |
6353                    (1ull << MSR_FE0) |
6354                    (1ull << MSR_SE) |
6355                    (1ull << MSR_DE) |
6356                    (1ull << MSR_FE1) |
6357                    (1ull << MSR_EP) |
6358                    (1ull << MSR_IR) |
6359                    (1ull << MSR_DR) |
6360                    (1ull << MSR_PMM) |
6361                    (1ull << MSR_RI) |
6362                    (1ull << MSR_LE);
6363    pcc->mmu_model = POWERPC_MMU_32B;
6364#if defined(CONFIG_SOFTMMU)
6365    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6366#endif
6367    pcc->excp_model = POWERPC_EXCP_7x0;
6368    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6369    pcc->bfd_mach = bfd_mach_ppc_750;
6370    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6371                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6372}
6373
6374static void init_proc_745(CPUPPCState *env)
6375{
6376    gen_spr_ne_601(env);
6377    gen_spr_sdr1(env);
6378    gen_spr_7xx(env);
6379    gen_spr_G2_755(env);
6380    /* Time base */
6381    gen_tbl(env);
6382    /* Thermal management */
6383    gen_spr_thrm(env);
6384    /* Hardware implementation registers */
6385    /* XXX : not implemented */
6386    spr_register(env, SPR_HID0, "HID0",
6387                 SPR_NOACCESS, SPR_NOACCESS,
6388                 &spr_read_generic, &spr_write_generic,
6389                 0x00000000);
6390    /* XXX : not implemented */
6391    spr_register(env, SPR_HID1, "HID1",
6392                 SPR_NOACCESS, SPR_NOACCESS,
6393                 &spr_read_generic, &spr_write_generic,
6394                 0x00000000);
6395    /* XXX : not implemented */
6396    spr_register(env, SPR_HID2, "HID2",
6397                 SPR_NOACCESS, SPR_NOACCESS,
6398                 &spr_read_generic, &spr_write_generic,
6399                 0x00000000);
6400    /* Memory management */
6401    gen_low_BATs(env);
6402    gen_high_BATs(env);
6403    gen_6xx_7xx_soft_tlb(env, 64, 2);
6404    init_excp_7x5(env);
6405    env->dcache_line_size = 32;
6406    env->icache_line_size = 32;
6407    /* Allocate hardware IRQ controller */
6408    ppc6xx_irq_init(env_archcpu(env));
6409}
6410
6411POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
6412{
6413    DeviceClass *dc = DEVICE_CLASS(oc);
6414    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6415
6416    dc->desc = "PowerPC 745";
6417    pcc->init_proc = init_proc_745;
6418    pcc->check_pow = check_pow_hid0;
6419    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6420                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6421                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6422                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6423                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6424                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6425                       PPC_SEGMENT | PPC_EXTERN;
6426    pcc->msr_mask = (1ull << MSR_POW) |
6427                    (1ull << MSR_ILE) |
6428                    (1ull << MSR_EE) |
6429                    (1ull << MSR_PR) |
6430                    (1ull << MSR_FP) |
6431                    (1ull << MSR_ME) |
6432                    (1ull << MSR_FE0) |
6433                    (1ull << MSR_SE) |
6434                    (1ull << MSR_DE) |
6435                    (1ull << MSR_FE1) |
6436                    (1ull << MSR_EP) |
6437                    (1ull << MSR_IR) |
6438                    (1ull << MSR_DR) |
6439                    (1ull << MSR_PMM) |
6440                    (1ull << MSR_RI) |
6441                    (1ull << MSR_LE);
6442    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6443    pcc->excp_model = POWERPC_EXCP_7x5;
6444    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6445    pcc->bfd_mach = bfd_mach_ppc_750;
6446    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6447                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6448}
6449
6450static void init_proc_755(CPUPPCState *env)
6451{
6452    gen_spr_ne_601(env);
6453    gen_spr_sdr1(env);
6454    gen_spr_7xx(env);
6455    gen_spr_G2_755(env);
6456    /* Time base */
6457    gen_tbl(env);
6458    /* L2 cache control */
6459    /* XXX : not implemented */
6460    spr_register(env, SPR_L2CR, "L2CR",
6461                 SPR_NOACCESS, SPR_NOACCESS,
6462                 &spr_read_generic, spr_access_nop,
6463                 0x00000000);
6464    /* XXX : not implemented */
6465    spr_register(env, SPR_L2PMCR, "L2PMCR",
6466                 SPR_NOACCESS, SPR_NOACCESS,
6467                 &spr_read_generic, &spr_write_generic,
6468                 0x00000000);
6469    /* Thermal management */
6470    gen_spr_thrm(env);
6471    /* Hardware implementation registers */
6472    /* XXX : not implemented */
6473    spr_register(env, SPR_HID0, "HID0",
6474                 SPR_NOACCESS, SPR_NOACCESS,
6475                 &spr_read_generic, &spr_write_generic,
6476                 0x00000000);
6477    /* XXX : not implemented */
6478    spr_register(env, SPR_HID1, "HID1",
6479                 SPR_NOACCESS, SPR_NOACCESS,
6480                 &spr_read_generic, &spr_write_generic,
6481                 0x00000000);
6482    /* XXX : not implemented */
6483    spr_register(env, SPR_HID2, "HID2",
6484                 SPR_NOACCESS, SPR_NOACCESS,
6485                 &spr_read_generic, &spr_write_generic,
6486                 0x00000000);
6487    /* Memory management */
6488    gen_low_BATs(env);
6489    gen_high_BATs(env);
6490    gen_6xx_7xx_soft_tlb(env, 64, 2);
6491    init_excp_7x5(env);
6492    env->dcache_line_size = 32;
6493    env->icache_line_size = 32;
6494    /* Allocate hardware IRQ controller */
6495    ppc6xx_irq_init(env_archcpu(env));
6496}
6497
6498POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
6499{
6500    DeviceClass *dc = DEVICE_CLASS(oc);
6501    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6502
6503    dc->desc = "PowerPC 755";
6504    pcc->init_proc = init_proc_755;
6505    pcc->check_pow = check_pow_hid0;
6506    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6507                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6508                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6509                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6510                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6511                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6512                       PPC_SEGMENT | PPC_EXTERN;
6513    pcc->msr_mask = (1ull << MSR_POW) |
6514                    (1ull << MSR_ILE) |
6515                    (1ull << MSR_EE) |
6516                    (1ull << MSR_PR) |
6517                    (1ull << MSR_FP) |
6518                    (1ull << MSR_ME) |
6519                    (1ull << MSR_FE0) |
6520                    (1ull << MSR_SE) |
6521                    (1ull << MSR_DE) |
6522                    (1ull << MSR_FE1) |
6523                    (1ull << MSR_EP) |
6524                    (1ull << MSR_IR) |
6525                    (1ull << MSR_DR) |
6526                    (1ull << MSR_PMM) |
6527                    (1ull << MSR_RI) |
6528                    (1ull << MSR_LE);
6529    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6530    pcc->excp_model = POWERPC_EXCP_7x5;
6531    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6532    pcc->bfd_mach = bfd_mach_ppc_750;
6533    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6534                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6535}
6536
6537static void init_proc_7400(CPUPPCState *env)
6538{
6539    gen_spr_ne_601(env);
6540    gen_spr_sdr1(env);
6541    gen_spr_7xx(env);
6542    /* Time base */
6543    gen_tbl(env);
6544    /* 74xx specific SPR */
6545    gen_spr_74xx(env);
6546    /* XXX : not implemented */
6547    spr_register(env, SPR_UBAMR, "UBAMR",
6548                 &spr_read_ureg, SPR_NOACCESS,
6549                 &spr_read_ureg, SPR_NOACCESS,
6550                 0x00000000);
6551    /* XXX: this seems not implemented on all revisions. */
6552    /* XXX : not implemented */
6553    spr_register(env, SPR_MSSCR1, "MSSCR1",
6554                 SPR_NOACCESS, SPR_NOACCESS,
6555                 &spr_read_generic, &spr_write_generic,
6556                 0x00000000);
6557    /* Thermal management */
6558    gen_spr_thrm(env);
6559    /* Memory management */
6560    gen_low_BATs(env);
6561    init_excp_7400(env);
6562    env->dcache_line_size = 32;
6563    env->icache_line_size = 32;
6564    /* Allocate hardware IRQ controller */
6565    ppc6xx_irq_init(env_archcpu(env));
6566}
6567
6568POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
6569{
6570    DeviceClass *dc = DEVICE_CLASS(oc);
6571    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6572
6573    dc->desc = "PowerPC 7400 (aka G4)";
6574    pcc->init_proc = init_proc_7400;
6575    pcc->check_pow = check_pow_hid0;
6576    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6577                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6578                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6579                       PPC_FLOAT_STFIWX |
6580                       PPC_CACHE | PPC_CACHE_ICBI |
6581                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6582                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6583                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6584                       PPC_MEM_TLBIA |
6585                       PPC_SEGMENT | PPC_EXTERN |
6586                       PPC_ALTIVEC;
6587    pcc->msr_mask = (1ull << MSR_VR) |
6588                    (1ull << MSR_POW) |
6589                    (1ull << MSR_ILE) |
6590                    (1ull << MSR_EE) |
6591                    (1ull << MSR_PR) |
6592                    (1ull << MSR_FP) |
6593                    (1ull << MSR_ME) |
6594                    (1ull << MSR_FE0) |
6595                    (1ull << MSR_SE) |
6596                    (1ull << MSR_DE) |
6597                    (1ull << MSR_FE1) |
6598                    (1ull << MSR_EP) |
6599                    (1ull << MSR_IR) |
6600                    (1ull << MSR_DR) |
6601                    (1ull << MSR_PMM) |
6602                    (1ull << MSR_RI) |
6603                    (1ull << MSR_LE);
6604    pcc->mmu_model = POWERPC_MMU_32B;
6605#if defined(CONFIG_SOFTMMU)
6606    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6607#endif
6608    pcc->excp_model = POWERPC_EXCP_74xx;
6609    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6610    pcc->bfd_mach = bfd_mach_ppc_7400;
6611    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6612                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6613                 POWERPC_FLAG_BUS_CLK;
6614}
6615
6616static void init_proc_7410(CPUPPCState *env)
6617{
6618    gen_spr_ne_601(env);
6619    gen_spr_sdr1(env);
6620    gen_spr_7xx(env);
6621    /* Time base */
6622    gen_tbl(env);
6623    /* 74xx specific SPR */
6624    gen_spr_74xx(env);
6625    /* XXX : not implemented */
6626    spr_register(env, SPR_UBAMR, "UBAMR",
6627                 &spr_read_ureg, SPR_NOACCESS,
6628                 &spr_read_ureg, SPR_NOACCESS,
6629                 0x00000000);
6630    /* Thermal management */
6631    gen_spr_thrm(env);
6632    /* L2PMCR */
6633    /* XXX : not implemented */
6634    spr_register(env, SPR_L2PMCR, "L2PMCR",
6635                 SPR_NOACCESS, SPR_NOACCESS,
6636                 &spr_read_generic, &spr_write_generic,
6637                 0x00000000);
6638    /* LDSTDB */
6639    /* XXX : not implemented */
6640    spr_register(env, SPR_LDSTDB, "LDSTDB",
6641                 SPR_NOACCESS, SPR_NOACCESS,
6642                 &spr_read_generic, &spr_write_generic,
6643                 0x00000000);
6644    /* Memory management */
6645    gen_low_BATs(env);
6646    init_excp_7400(env);
6647    env->dcache_line_size = 32;
6648    env->icache_line_size = 32;
6649    /* Allocate hardware IRQ controller */
6650    ppc6xx_irq_init(env_archcpu(env));
6651}
6652
6653POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6654{
6655    DeviceClass *dc = DEVICE_CLASS(oc);
6656    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6657
6658    dc->desc = "PowerPC 7410 (aka G4)";
6659    pcc->init_proc = init_proc_7410;
6660    pcc->check_pow = check_pow_hid0;
6661    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6662                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6663                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6664                       PPC_FLOAT_STFIWX |
6665                       PPC_CACHE | PPC_CACHE_ICBI |
6666                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6667                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6668                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6669                       PPC_MEM_TLBIA |
6670                       PPC_SEGMENT | PPC_EXTERN |
6671                       PPC_ALTIVEC;
6672    pcc->msr_mask = (1ull << MSR_VR) |
6673                    (1ull << MSR_POW) |
6674                    (1ull << MSR_ILE) |
6675                    (1ull << MSR_EE) |
6676                    (1ull << MSR_PR) |
6677                    (1ull << MSR_FP) |
6678                    (1ull << MSR_ME) |
6679                    (1ull << MSR_FE0) |
6680                    (1ull << MSR_SE) |
6681                    (1ull << MSR_DE) |
6682                    (1ull << MSR_FE1) |
6683                    (1ull << MSR_EP) |
6684                    (1ull << MSR_IR) |
6685                    (1ull << MSR_DR) |
6686                    (1ull << MSR_PMM) |
6687                    (1ull << MSR_RI) |
6688                    (1ull << MSR_LE);
6689    pcc->mmu_model = POWERPC_MMU_32B;
6690#if defined(CONFIG_SOFTMMU)
6691    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6692#endif
6693    pcc->excp_model = POWERPC_EXCP_74xx;
6694    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6695    pcc->bfd_mach = bfd_mach_ppc_7400;
6696    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6697                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6698                 POWERPC_FLAG_BUS_CLK;
6699}
6700
6701static void init_proc_7440(CPUPPCState *env)
6702{
6703    gen_spr_ne_601(env);
6704    gen_spr_sdr1(env);
6705    gen_spr_7xx(env);
6706    /* Time base */
6707    gen_tbl(env);
6708    /* 74xx specific SPR */
6709    gen_spr_74xx(env);
6710    /* XXX : not implemented */
6711    spr_register(env, SPR_UBAMR, "UBAMR",
6712                 &spr_read_ureg, SPR_NOACCESS,
6713                 &spr_read_ureg, SPR_NOACCESS,
6714                 0x00000000);
6715    /* LDSTCR */
6716    /* XXX : not implemented */
6717    spr_register(env, SPR_LDSTCR, "LDSTCR",
6718                 SPR_NOACCESS, SPR_NOACCESS,
6719                 &spr_read_generic, &spr_write_generic,
6720                 0x00000000);
6721    /* ICTRL */
6722    /* XXX : not implemented */
6723    spr_register(env, SPR_ICTRL, "ICTRL",
6724                 SPR_NOACCESS, SPR_NOACCESS,
6725                 &spr_read_generic, &spr_write_generic,
6726                 0x00000000);
6727    /* MSSSR0 */
6728    /* XXX : not implemented */
6729    spr_register(env, SPR_MSSSR0, "MSSSR0",
6730                 SPR_NOACCESS, SPR_NOACCESS,
6731                 &spr_read_generic, &spr_write_generic,
6732                 0x00000000);
6733    /* PMC */
6734    /* XXX : not implemented */
6735    spr_register(env, SPR_7XX_PMC5, "PMC5",
6736                 SPR_NOACCESS, SPR_NOACCESS,
6737                 &spr_read_generic, &spr_write_generic,
6738                 0x00000000);
6739    /* XXX : not implemented */
6740    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6741                 &spr_read_ureg, SPR_NOACCESS,
6742                 &spr_read_ureg, SPR_NOACCESS,
6743                 0x00000000);
6744    /* XXX : not implemented */
6745    spr_register(env, SPR_7XX_PMC6, "PMC6",
6746                 SPR_NOACCESS, SPR_NOACCESS,
6747                 &spr_read_generic, &spr_write_generic,
6748                 0x00000000);
6749    /* XXX : not implemented */
6750    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6751                 &spr_read_ureg, SPR_NOACCESS,
6752                 &spr_read_ureg, SPR_NOACCESS,
6753                 0x00000000);
6754    /* Memory management */
6755    gen_low_BATs(env);
6756    gen_74xx_soft_tlb(env, 128, 2);
6757    init_excp_7450(env);
6758    env->dcache_line_size = 32;
6759    env->icache_line_size = 32;
6760    /* Allocate hardware IRQ controller */
6761    ppc6xx_irq_init(env_archcpu(env));
6762}
6763
6764POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6765{
6766    DeviceClass *dc = DEVICE_CLASS(oc);
6767    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6768
6769    dc->desc = "PowerPC 7440 (aka G4)";
6770    pcc->init_proc = init_proc_7440;
6771    pcc->check_pow = check_pow_hid0_74xx;
6772    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6773                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6774                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6775                       PPC_FLOAT_STFIWX |
6776                       PPC_CACHE | PPC_CACHE_ICBI |
6777                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6778                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6779                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6780                       PPC_MEM_TLBIA | PPC_74xx_TLB |
6781                       PPC_SEGMENT | PPC_EXTERN |
6782                       PPC_ALTIVEC;
6783    pcc->msr_mask = (1ull << MSR_VR) |
6784                    (1ull << MSR_POW) |
6785                    (1ull << MSR_ILE) |
6786                    (1ull << MSR_EE) |
6787                    (1ull << MSR_PR) |
6788                    (1ull << MSR_FP) |
6789                    (1ull << MSR_ME) |
6790                    (1ull << MSR_FE0) |
6791                    (1ull << MSR_SE) |
6792                    (1ull << MSR_DE) |
6793                    (1ull << MSR_FE1) |
6794                    (1ull << MSR_EP) |
6795                    (1ull << MSR_IR) |
6796                    (1ull << MSR_DR) |
6797                    (1ull << MSR_PMM) |
6798                    (1ull << MSR_RI) |
6799                    (1ull << MSR_LE);
6800    pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6801    pcc->excp_model = POWERPC_EXCP_74xx;
6802    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6803    pcc->bfd_mach = bfd_mach_ppc_7400;
6804    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6805                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6806                 POWERPC_FLAG_BUS_CLK;
6807}
6808
6809static void init_proc_7450(CPUPPCState *env)
6810{
6811    gen_spr_ne_601(env);
6812    gen_spr_sdr1(env);
6813    gen_spr_7xx(env);
6814    /* Time base */
6815    gen_tbl(env);
6816    /* 74xx specific SPR */
6817    gen_spr_74xx(env);
6818    /* Level 3 cache control */
6819    gen_l3_ctrl(env);
6820    /* L3ITCR1 */
6821    /* XXX : not implemented */
6822    spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6823                 SPR_NOACCESS, SPR_NOACCESS,
6824                 &spr_read_generic, &spr_write_generic,
6825                 0x00000000);
6826    /* L3ITCR2 */
6827    /* XXX : not implemented */
6828    spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6829                 SPR_NOACCESS, SPR_NOACCESS,
6830                 &spr_read_generic, &spr_write_generic,
6831                 0x00000000);
6832    /* L3ITCR3 */
6833    /* XXX : not implemented */
6834    spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6835                 SPR_NOACCESS, SPR_NOACCESS,
6836                 &spr_read_generic, &spr_write_generic,
6837                 0x00000000);
6838    /* L3OHCR */
6839    /* XXX : not implemented */
6840    spr_register(env, SPR_L3OHCR, "L3OHCR",
6841                 SPR_NOACCESS, SPR_NOACCESS,
6842                 &spr_read_generic, &spr_write_generic,
6843                 0x00000000);
6844    /* XXX : not implemented */
6845    spr_register(env, SPR_UBAMR, "UBAMR",
6846                 &spr_read_ureg, SPR_NOACCESS,
6847                 &spr_read_ureg, SPR_NOACCESS,
6848                 0x00000000);
6849    /* LDSTCR */
6850    /* XXX : not implemented */
6851    spr_register(env, SPR_LDSTCR, "LDSTCR",
6852                 SPR_NOACCESS, SPR_NOACCESS,
6853                 &spr_read_generic, &spr_write_generic,
6854                 0x00000000);
6855    /* ICTRL */
6856    /* XXX : not implemented */
6857    spr_register(env, SPR_ICTRL, "ICTRL",
6858                 SPR_NOACCESS, SPR_NOACCESS,
6859                 &spr_read_generic, &spr_write_generic,
6860                 0x00000000);
6861    /* MSSSR0 */
6862    /* XXX : not implemented */
6863    spr_register(env, SPR_MSSSR0, "MSSSR0",
6864                 SPR_NOACCESS, SPR_NOACCESS,
6865                 &spr_read_generic, &spr_write_generic,
6866                 0x00000000);
6867    /* PMC */
6868    /* XXX : not implemented */
6869    spr_register(env, SPR_7XX_PMC5, "PMC5",
6870                 SPR_NOACCESS, SPR_NOACCESS,
6871                 &spr_read_generic, &spr_write_generic,
6872                 0x00000000);
6873    /* XXX : not implemented */
6874    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6875                 &spr_read_ureg, SPR_NOACCESS,
6876                 &spr_read_ureg, SPR_NOACCESS,
6877                 0x00000000);
6878    /* XXX : not implemented */
6879    spr_register(env, SPR_7XX_PMC6, "PMC6",
6880                 SPR_NOACCESS, SPR_NOACCESS,
6881                 &spr_read_generic, &spr_write_generic,
6882                 0x00000000);
6883    /* XXX : not implemented */
6884    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6885                 &spr_read_ureg, SPR_NOACCESS,
6886                 &spr_read_ureg, SPR_NOACCESS,
6887                 0x00000000);
6888    /* Memory management */
6889    gen_low_BATs(env);
6890    gen_74xx_soft_tlb(env, 128, 2);
6891    init_excp_7450(env);
6892    env->dcache_line_size = 32;
6893    env->icache_line_size = 32;
6894    /* Allocate hardware IRQ controller */
6895    ppc6xx_irq_init(env_archcpu(env));
6896}
6897
6898POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6899{
6900    DeviceClass *dc = DEVICE_CLASS(oc);
6901    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6902
6903    dc->desc = "PowerPC 7450 (aka G4)";
6904    pcc->init_proc = init_proc_7450;
6905    pcc->check_pow = check_pow_hid0_74xx;
6906    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6907                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6908                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6909                       PPC_FLOAT_STFIWX |
6910                       PPC_CACHE | PPC_CACHE_ICBI |
6911                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6912                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6913                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6914                       PPC_MEM_TLBIA | PPC_74xx_TLB |
6915                       PPC_SEGMENT | PPC_EXTERN |
6916                       PPC_ALTIVEC;
6917    pcc->msr_mask = (1ull << MSR_VR) |
6918                    (1ull << MSR_POW) |
6919                    (1ull << MSR_ILE) |
6920                    (1ull << MSR_EE) |
6921                    (1ull << MSR_PR) |
6922                    (1ull << MSR_FP) |
6923                    (1ull << MSR_ME) |
6924                    (1ull << MSR_FE0) |
6925                    (1ull << MSR_SE) |
6926                    (1ull << MSR_DE) |
6927                    (1ull << MSR_FE1) |
6928                    (1ull << MSR_EP) |
6929                    (1ull << MSR_IR) |
6930                    (1ull << MSR_DR) |
6931                    (1ull << MSR_PMM) |
6932                    (1ull << MSR_RI) |
6933                    (1ull << MSR_LE);
6934    pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6935    pcc->excp_model = POWERPC_EXCP_74xx;
6936    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6937    pcc->bfd_mach = bfd_mach_ppc_7400;
6938    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6939                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6940                 POWERPC_FLAG_BUS_CLK;
6941}
6942
6943static void init_proc_7445(CPUPPCState *env)
6944{
6945    gen_spr_ne_601(env);
6946    gen_spr_sdr1(env);
6947    gen_spr_7xx(env);
6948    /* Time base */
6949    gen_tbl(env);
6950    /* 74xx specific SPR */
6951    gen_spr_74xx(env);
6952    /* LDSTCR */
6953    /* XXX : not implemented */
6954    spr_register(env, SPR_LDSTCR, "LDSTCR",
6955                 SPR_NOACCESS, SPR_NOACCESS,
6956                 &spr_read_generic, &spr_write_generic,
6957                 0x00000000);
6958    /* ICTRL */
6959    /* XXX : not implemented */
6960    spr_register(env, SPR_ICTRL, "ICTRL",
6961                 SPR_NOACCESS, SPR_NOACCESS,
6962                 &spr_read_generic, &spr_write_generic,
6963                 0x00000000);
6964    /* MSSSR0 */
6965    /* XXX : not implemented */
6966    spr_register(env, SPR_MSSSR0, "MSSSR0",
6967                 SPR_NOACCESS, SPR_NOACCESS,
6968                 &spr_read_generic, &spr_write_generic,
6969                 0x00000000);
6970    /* PMC */
6971    /* XXX : not implemented */
6972    spr_register(env, SPR_7XX_PMC5, "PMC5",
6973                 SPR_NOACCESS, SPR_NOACCESS,
6974                 &spr_read_generic, &spr_write_generic,
6975                 0x00000000);
6976    /* XXX : not implemented */
6977    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6978                 &spr_read_ureg, SPR_NOACCESS,
6979                 &spr_read_ureg, SPR_NOACCESS,
6980                 0x00000000);
6981    /* XXX : not implemented */
6982    spr_register(env, SPR_7XX_PMC6, "PMC6",
6983                 SPR_NOACCESS, SPR_NOACCESS,
6984                 &spr_read_generic, &spr_write_generic,
6985                 0x00000000);
6986    /* XXX : not implemented */
6987    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6988                 &spr_read_ureg, SPR_NOACCESS,
6989                 &spr_read_ureg, SPR_NOACCESS,
6990                 0x00000000);
6991    /* SPRGs */
6992    spr_register(env, SPR_SPRG4, "SPRG4",
6993                 SPR_NOACCESS, SPR_NOACCESS,
6994                 &spr_read_generic, &spr_write_generic,
6995                 0x00000000);
6996    spr_register(env, SPR_USPRG4, "USPRG4",
6997                 &spr_read_ureg, SPR_NOACCESS,
6998                 &spr_read_ureg, SPR_NOACCESS,
6999                 0x00000000);
7000    spr_register(env, SPR_SPRG5, "SPRG5",

7001                 SPR_NOACCESS, SPR_NOACCESS,
7002                 &spr_read_generic, &spr_write_generic,
7003                 0x00000000);
7004    spr_register(env, SPR_USPRG5, "USPRG5",
7005                 &spr_read_ureg, SPR_NOACCESS,
7006                 &spr_read_ureg, SPR_NOACCESS,
7007                 0x00000000);
7008    spr_register(env, SPR_SPRG6, "SPRG6",
7009                 SPR_NOACCESS, SPR_NOACCESS,
7010                 &spr_read_generic, &spr_write_generic,
7011                 0x00000000);
7012    spr_register(env, SPR_USPRG6, "USPRG6",
7013                 &spr_read_ureg, SPR_NOACCESS,
7014                 &spr_read_ureg, SPR_NOACCESS,
7015                 0x00000000);
7016    spr_register(env, SPR_SPRG7, "SPRG7",
7017                 SPR_NOACCESS, SPR_NOACCESS,
7018                 &spr_read_generic, &spr_write_generic,
7019                 0x00000000);
7020    spr_register(env, SPR_USPRG7, "USPRG7",
7021                 &spr_read_ureg, SPR_NOACCESS,
7022                 &spr_read_ureg, SPR_NOACCESS,
7023                 0x00000000);
7024    /* Memory management */
7025    gen_low_BATs(env);
7026    gen_high_BATs(env);
7027    gen_74xx_soft_tlb(env, 128, 2);
7028    init_excp_7450(env);
7029    env->dcache_line_size = 32;
7030    env->icache_line_size = 32;
7031    /* Allocate hardware IRQ controller */
7032    ppc6xx_irq_init(env_archcpu(env));
7033}
7034
7035POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
7036{
7037    DeviceClass *dc = DEVICE_CLASS(oc);
7038    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7039
7040    dc->desc = "PowerPC 7445 (aka G4)";
7041    pcc->init_proc = init_proc_7445;
7042    pcc->check_pow = check_pow_hid0_74xx;
7043    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7044                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7045                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7046                       PPC_FLOAT_STFIWX |
7047                       PPC_CACHE | PPC_CACHE_ICBI |
7048                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7049                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
7050                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7051                       PPC_MEM_TLBIA | PPC_74xx_TLB |
7052                       PPC_SEGMENT | PPC_EXTERN |
7053                       PPC_ALTIVEC;
7054    pcc->msr_mask = (1ull << MSR_VR) |
7055                    (1ull << MSR_POW) |
7056                    (1ull << MSR_ILE) |
7057                    (1ull << MSR_EE) |
7058                    (1ull << MSR_PR) |
7059                    (1ull << MSR_FP) |
7060                    (1ull << MSR_ME) |
7061                    (1ull << MSR_FE0) |
7062                    (1ull << MSR_SE) |
7063                    (1ull << MSR_DE) |
7064                    (1ull << MSR_FE1) |
7065                    (1ull << MSR_EP) |
7066                    (1ull << MSR_IR) |
7067                    (1ull << MSR_DR) |
7068                    (1ull << MSR_PMM) |
7069                    (1ull << MSR_RI) |
7070                    (1ull << MSR_LE);
7071    pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7072    pcc->excp_model = POWERPC_EXCP_74xx;
7073    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7074    pcc->bfd_mach = bfd_mach_ppc_7400;
7075    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7076                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7077                 POWERPC_FLAG_BUS_CLK;
7078}
7079
7080static void init_proc_7455(CPUPPCState *env)
7081{
7082    gen_spr_ne_601(env);
7083    gen_spr_sdr1(env);
7084    gen_spr_7xx(env);
7085    /* Time base */
7086    gen_tbl(env);
7087    /* 74xx specific SPR */
7088    gen_spr_74xx(env);
7089    /* Level 3 cache control */
7090    gen_l3_ctrl(env);
7091    /* LDSTCR */
7092    /* XXX : not implemented */
7093    spr_register(env, SPR_LDSTCR, "LDSTCR",
7094                 SPR_NOACCESS, SPR_NOACCESS,
7095                 &spr_read_generic, &spr_write_generic,
7096                 0x00000000);
7097    /* ICTRL */
7098    /* XXX : not implemented */
7099    spr_register(env, SPR_ICTRL, "ICTRL",
7100                 SPR_NOACCESS, SPR_NOACCESS,
7101                 &spr_read_generic, &spr_write_generic,
7102                 0x00000000);
7103    /* MSSSR0 */
7104    /* XXX : not implemented */
7105    spr_register(env, SPR_MSSSR0, "MSSSR0",
7106                 SPR_NOACCESS, SPR_NOACCESS,
7107                 &spr_read_generic, &spr_write_generic,
7108                 0x00000000);
7109    /* PMC */
7110    /* XXX : not implemented */
7111    spr_register(env, SPR_7XX_PMC5, "PMC5",
7112                 SPR_NOACCESS, SPR_NOACCESS,
7113                 &spr_read_generic, &spr_write_generic,
7114                 0x00000000);
7115    /* XXX : not implemented */
7116    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7117                 &spr_read_ureg, SPR_NOACCESS,
7118                 &spr_read_ureg, SPR_NOACCESS,
7119                 0x00000000);
7120    /* XXX : not implemented */
7121    spr_register(env, SPR_7XX_PMC6, "PMC6",
7122                 SPR_NOACCESS, SPR_NOACCESS,
7123                 &spr_read_generic, &spr_write_generic,
7124                 0x00000000);
7125    /* XXX : not implemented */
7126    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7127                 &spr_read_ureg, SPR_NOACCESS,
7128                 &spr_read_ureg, SPR_NOACCESS,
7129                 0x00000000);
7130    /* SPRGs */
7131    spr_register(env, SPR_SPRG4, "SPRG4",
7132                 SPR_NOACCESS, SPR_NOACCESS,
7133                 &spr_read_generic, &spr_write_generic,
7134                 0x00000000);
7135    spr_register(env, SPR_USPRG4, "USPRG4",
7136                 &spr_read_ureg, SPR_NOACCESS,
7137                 &spr_read_ureg, SPR_NOACCESS,
7138                 0x00000000);
7139    spr_register(env, SPR_SPRG5, "SPRG5",
7140                 SPR_NOACCESS, SPR_NOACCESS,
7141                 &spr_read_generic, &spr_write_generic,
7142                 0x00000000);
7143    spr_register(env, SPR_USPRG5, "USPRG5",
7144                 &spr_read_ureg, SPR_NOACCESS,
7145                 &spr_read_ureg, SPR_NOACCESS,
7146                 0x00000000);
7147    spr_register(env, SPR_SPRG6, "SPRG6",
7148                 SPR_NOACCESS, SPR_NOACCESS,
7149                 &spr_read_generic, &spr_write_generic,
7150                 0x00000000);
7151    spr_register(env, SPR_USPRG6, "USPRG6",
7152                 &spr_read_ureg, SPR_NOACCESS,
7153                 &spr_read_ureg, SPR_NOACCESS,
7154                 0x00000000);
7155    spr_register(env, SPR_SPRG7, "SPRG7",
7156                 SPR_NOACCESS, SPR_NOACCESS,
7157                 &spr_read_generic, &spr_write_generic,
7158                 0x00000000);
7159    spr_register(env, SPR_USPRG7, "USPRG7",
7160                 &spr_read_ureg, SPR_NOACCESS,
7161                 &spr_read_ureg, SPR_NOACCESS,
7162                 0x00000000);
7163    /* Memory management */
7164    gen_low_BATs(env);
7165    gen_high_BATs(env);
7166    gen_74xx_soft_tlb(env, 128, 2);
7167    init_excp_7450(env);
7168    env->dcache_line_size = 32;
7169    env->icache_line_size = 32;
7170    /* Allocate hardware IRQ controller */
7171    ppc6xx_irq_init(env_archcpu(env));
7172}
7173
7174POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
7175{
7176    DeviceClass *dc = DEVICE_CLASS(oc);
7177    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7178
7179    dc->desc = "PowerPC 7455 (aka G4)";
7180    pcc->init_proc = init_proc_7455;
7181    pcc->check_pow = check_pow_hid0_74xx;
7182    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7183                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7184                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7185                       PPC_FLOAT_STFIWX |
7186                       PPC_CACHE | PPC_CACHE_ICBI |
7187                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7188                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
7189                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7190                       PPC_MEM_TLBIA | PPC_74xx_TLB |
7191                       PPC_SEGMENT | PPC_EXTERN |
7192                       PPC_ALTIVEC;
7193    pcc->msr_mask = (1ull << MSR_VR) |
7194                    (1ull << MSR_POW) |
7195                    (1ull << MSR_ILE) |
7196                    (1ull << MSR_EE) |
7197                    (1ull << MSR_PR) |
7198                    (1ull << MSR_FP) |
7199                    (1ull << MSR_ME) |
7200                    (1ull << MSR_FE0) |
7201                    (1ull << MSR_SE) |
7202                    (1ull << MSR_DE) |
7203                    (1ull << MSR_FE1) |
7204                    (1ull << MSR_EP) |
7205                    (1ull << MSR_IR) |
7206                    (1ull << MSR_DR) |
7207                    (1ull << MSR_PMM) |
7208                    (1ull << MSR_RI) |
7209                    (1ull << MSR_LE);
7210    pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7211    pcc->excp_model = POWERPC_EXCP_74xx;
7212    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7213    pcc->bfd_mach = bfd_mach_ppc_7400;
7214    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7215                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7216                 POWERPC_FLAG_BUS_CLK;
7217}
7218
7219static void init_proc_7457(CPUPPCState *env)
7220{
7221    gen_spr_ne_601(env);
7222    gen_spr_sdr1(env);
7223    gen_spr_7xx(env);
7224    /* Time base */
7225    gen_tbl(env);
7226    /* 74xx specific SPR */
7227    gen_spr_74xx(env);
7228    /* Level 3 cache control */
7229    gen_l3_ctrl(env);
7230    /* L3ITCR1 */
7231    /* XXX : not implemented */
7232    spr_register(env, SPR_L3ITCR1, "L3ITCR1",
7233                 SPR_NOACCESS, SPR_NOACCESS,
7234                 &spr_read_generic, &spr_write_generic,
7235                 0x00000000);
7236    /* L3ITCR2 */
7237    /* XXX : not implemented */
7238    spr_register(env, SPR_L3ITCR2, "L3ITCR2",
7239                 SPR_NOACCESS, SPR_NOACCESS,
7240                 &spr_read_generic, &spr_write_generic,
7241                 0x00000000);
7242    /* L3ITCR3 */
7243    /* XXX : not implemented */
7244    spr_register(env, SPR_L3ITCR3, "L3ITCR3",
7245                 SPR_NOACCESS, SPR_NOACCESS,
7246                 &spr_read_generic, &spr_write_generic,
7247                 0x00000000);
7248    /* L3OHCR */
7249    /* XXX : not implemented */
7250    spr_register(env, SPR_L3OHCR, "L3OHCR",
7251                 SPR_NOACCESS, SPR_NOACCESS,
7252                 &spr_read_generic, &spr_write_generic,
7253                 0x00000000);
7254    /* LDSTCR */
7255    /* XXX : not implemented */
7256    spr_register(env, SPR_LDSTCR, "LDSTCR",
7257                 SPR_NOACCESS, SPR_NOACCESS,
7258                 &spr_read_generic, &spr_write_generic,
7259                 0x00000000);
7260    /* ICTRL */
7261    /* XXX : not implemented */
7262    spr_register(env, SPR_ICTRL, "ICTRL",
7263                 SPR_NOACCESS, SPR_NOACCESS,
7264                 &spr_read_generic, &spr_write_generic,
7265                 0x00000000);
7266    /* MSSSR0 */
7267    /* XXX : not implemented */
7268    spr_register(env, SPR_MSSSR0, "MSSSR0",
7269                 SPR_NOACCESS, SPR_NOACCESS,
7270                 &spr_read_generic, &spr_write_generic,
7271                 0x00000000);
7272    /* PMC */
7273    /* XXX : not implemented */
7274    spr_register(env, SPR_7XX_PMC5, "PMC5",
7275                 SPR_NOACCESS, SPR_NOACCESS,
7276                 &spr_read_generic, &spr_write_generic,
7277                 0x00000000);
7278    /* XXX : not implemented */
7279    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7280                 &spr_read_ureg, SPR_NOACCESS,
7281                 &spr_read_ureg, SPR_NOACCESS,
7282                 0x00000000);
7283    /* XXX : not implemented */
7284    spr_register(env, SPR_7XX_PMC6, "PMC6",
7285                 SPR_NOACCESS, SPR_NOACCESS,
7286                 &spr_read_generic, &spr_write_generic,
7287                 0x00000000);
7288    /* XXX : not implemented */
7289    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7290                 &spr_read_ureg, SPR_NOACCESS,
7291                 &spr_read_ureg, SPR_NOACCESS,
7292                 0x00000000);
7293    /* SPRGs */
7294    spr_register(env, SPR_SPRG4, "SPRG4",
7295                 SPR_NOACCESS, SPR_NOACCESS,
7296                 &spr_read_generic, &spr_write_generic,
7297                 0x00000000);
7298    spr_register(env, SPR_USPRG4, "USPRG4",
7299                 &spr_read_ureg, SPR_NOACCESS,
7300                 &spr_read_ureg, SPR_NOACCESS,
7301                 0x00000000);
7302    spr_register(env, SPR_SPRG5, "SPRG5",
7303                 SPR_NOACCESS, SPR_NOACCESS,
7304                 &spr_read_generic, &spr_write_generic,
7305                 0x00000000);
7306    spr_register(env, SPR_USPRG5, "USPRG5",
7307                 &spr_read_ureg, SPR_NOACCESS,
7308                 &spr_read_ureg, SPR_NOACCESS,
7309                 0x00000000);
7310    spr_register(env, SPR_SPRG6, "SPRG6",
7311                 SPR_NOACCESS, SPR_NOACCESS,
7312                 &spr_read_generic, &spr_write_generic,
7313                 0x00000000);
7314    spr_register(env, SPR_USPRG6, "USPRG6",
7315                 &spr_read_ureg, SPR_NOACCESS,
7316                 &spr_read_ureg, SPR_NOACCESS,
7317                 0x00000000);
7318    spr_register(env, SPR_SPRG7, "SPRG7",
7319                 SPR_NOACCESS, SPR_NOACCESS,
7320                 &spr_read_generic, &spr_write_generic,
7321                 0x00000000);
7322    spr_register(env, SPR_USPRG7, "USPRG7",
7323                 &spr_read_ureg, SPR_NOACCESS,
7324                 &spr_read_ureg, SPR_NOACCESS,
7325                 0x00000000);
7326    /* Memory management */
7327    gen_low_BATs(env);
7328    gen_high_BATs(env);
7329    gen_74xx_soft_tlb(env, 128, 2);
7330    init_excp_7450(env);
7331    env->dcache_line_size = 32;
7332    env->icache_line_size = 32;
7333    /* Allocate hardware IRQ controller */
7334    ppc6xx_irq_init(env_archcpu(env));
7335}
7336
7337POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
7338{
7339    DeviceClass *dc = DEVICE_CLASS(oc);
7340    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7341
7342    dc->desc = "PowerPC 7457 (aka G4)";
7343    pcc->init_proc = init_proc_7457;
7344    pcc->check_pow = check_pow_hid0_74xx;
7345    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7346                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7347                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7348                       PPC_FLOAT_STFIWX |
7349                       PPC_CACHE | PPC_CACHE_ICBI |
7350                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7351                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
7352                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7353                       PPC_MEM_TLBIA | PPC_74xx_TLB |
7354                       PPC_SEGMENT | PPC_EXTERN |
7355                       PPC_ALTIVEC;
7356    pcc->msr_mask = (1ull << MSR_VR) |
7357                    (1ull << MSR_POW) |
7358                    (1ull << MSR_ILE) |
7359                    (1ull << MSR_EE) |
7360                    (1ull << MSR_PR) |
7361                    (1ull << MSR_FP) |
7362                    (1ull << MSR_ME) |
7363                    (1ull << MSR_FE0) |
7364                    (1ull << MSR_SE) |
7365                    (1ull << MSR_DE) |
7366                    (1ull << MSR_FE1) |
7367                    (1ull << MSR_EP) |
7368                    (1ull << MSR_IR) |
7369                    (1ull << MSR_DR) |
7370                    (1ull << MSR_PMM) |
7371                    (1ull << MSR_RI) |
7372                    (1ull << MSR_LE);
7373    pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7374    pcc->excp_model = POWERPC_EXCP_74xx;
7375    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7376    pcc->bfd_mach = bfd_mach_ppc_7400;
7377    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7378                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7379                 POWERPC_FLAG_BUS_CLK;
7380}
7381
7382static void init_proc_e600(CPUPPCState *env)
7383{
7384    gen_spr_ne_601(env);
7385    gen_spr_sdr1(env);
7386    gen_spr_7xx(env);
7387    /* Time base */
7388    gen_tbl(env);
7389    /* 74xx specific SPR */
7390    gen_spr_74xx(env);
7391    /* XXX : not implemented */
7392    spr_register(env, SPR_UBAMR, "UBAMR",
7393                 &spr_read_ureg, SPR_NOACCESS,
7394                 &spr_read_ureg, SPR_NOACCESS,
7395                 0x00000000);
7396    /* XXX : not implemented */
7397    spr_register(env, SPR_LDSTCR, "LDSTCR",
7398                 SPR_NOACCESS, SPR_NOACCESS,
7399                 &spr_read_generic, &spr_write_generic,
7400                 0x00000000);
7401    /* XXX : not implemented */
7402    spr_register(env, SPR_ICTRL, "ICTRL",
7403                 SPR_NOACCESS, SPR_NOACCESS,
7404                 &spr_read_generic, &spr_write_generic,
7405                 0x00000000);
7406    /* XXX : not implemented */
7407    spr_register(env, SPR_MSSSR0, "MSSSR0",
7408                 SPR_NOACCESS, SPR_NOACCESS,
7409                 &spr_read_generic, &spr_write_generic,
7410                 0x00000000);
7411    /* XXX : not implemented */
7412    spr_register(env, SPR_7XX_PMC5, "PMC5",
7413                 SPR_NOACCESS, SPR_NOACCESS,
7414                 &spr_read_generic, &spr_write_generic,
7415                 0x00000000);
7416    /* XXX : not implemented */
7417    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7418                 &spr_read_ureg, SPR_NOACCESS,
7419                 &spr_read_ureg, SPR_NOACCESS,
7420                 0x00000000);
7421    /* XXX : not implemented */
7422    spr_register(env, SPR_7XX_PMC6, "PMC6",
7423                 SPR_NOACCESS, SPR_NOACCESS,
7424                 &spr_read_generic, &spr_write_generic,
7425                 0x00000000);
7426    /* XXX : not implemented */
7427    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7428                 &spr_read_ureg, SPR_NOACCESS,
7429                 &spr_read_ureg, SPR_NOACCESS,
7430                 0x00000000);
7431    /* SPRGs */
7432    spr_register(env, SPR_SPRG4, "SPRG4",
7433                 SPR_NOACCESS, SPR_NOACCESS,
7434                 &spr_read_generic, &spr_write_generic,
7435                 0x00000000);
7436    spr_register(env, SPR_USPRG4, "USPRG4",
7437                 &spr_read_ureg, SPR_NOACCESS,
7438                 &spr_read_ureg, SPR_NOACCESS,
7439                 0x00000000);
7440    spr_register(env, SPR_SPRG5, "SPRG5",
7441                 SPR_NOACCESS, SPR_NOACCESS,
7442                 &spr_read_generic, &spr_write_generic,
7443                 0x00000000);
7444    spr_register(env, SPR_USPRG5, "USPRG5",
7445                 &spr_read_ureg, SPR_NOACCESS,
7446                 &spr_read_ureg, SPR_NOACCESS,
7447                 0x00000000);
7448    spr_register(env, SPR_SPRG6, "SPRG6",
7449                 SPR_NOACCESS, SPR_NOACCESS,
7450                 &spr_read_generic, &spr_write_generic,
7451                 0x00000000);
7452    spr_register(env, SPR_USPRG6, "USPRG6",
7453                 &spr_read_ureg, SPR_NOACCESS,
7454                 &spr_read_ureg, SPR_NOACCESS,
7455                 0x00000000);
7456    spr_register(env, SPR_SPRG7, "SPRG7",
7457                 SPR_NOACCESS, SPR_NOACCESS,
7458                 &spr_read_generic, &spr_write_generic,
7459                 0x00000000);
7460    spr_register(env, SPR_USPRG7, "USPRG7",
7461                 &spr_read_ureg, SPR_NOACCESS,
7462                 &spr_read_ureg, SPR_NOACCESS,
7463                 0x00000000);
7464    /* Memory management */
7465    gen_low_BATs(env);
7466    gen_high_BATs(env);
7467    gen_74xx_soft_tlb(env, 128, 2);
7468    init_excp_7450(env);
7469    env->dcache_line_size = 32;
7470    env->icache_line_size = 32;
7471    /* Allocate hardware IRQ controller */
7472    ppc6xx_irq_init(env_archcpu(env));
7473}
7474
7475POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
7476{
7477    DeviceClass *dc = DEVICE_CLASS(oc);
7478    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7479
7480    dc->desc = "PowerPC e600";
7481    pcc->init_proc = init_proc_e600;
7482    pcc->check_pow = check_pow_hid0_74xx;
7483    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7484                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7485                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7486                       PPC_FLOAT_STFIWX |
7487                       PPC_CACHE | PPC_CACHE_ICBI |
7488                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7489                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
7490                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7491                       PPC_MEM_TLBIA | PPC_74xx_TLB |
7492                       PPC_SEGMENT | PPC_EXTERN |
7493                       PPC_ALTIVEC;
7494    pcc->insns_flags2 = PPC_NONE;
7495    pcc->msr_mask = (1ull << MSR_VR) |
7496                    (1ull << MSR_POW) |
7497                    (1ull << MSR_ILE) |
7498                    (1ull << MSR_EE) |
7499                    (1ull << MSR_PR) |
7500                    (1ull << MSR_FP) |
7501                    (1ull << MSR_ME) |
7502                    (1ull << MSR_FE0) |
7503                    (1ull << MSR_SE) |
7504                    (1ull << MSR_DE) |
7505                    (1ull << MSR_FE1) |
7506                    (1ull << MSR_EP) |
7507                    (1ull << MSR_IR) |
7508                    (1ull << MSR_DR) |
7509                    (1ull << MSR_PMM) |
7510                    (1ull << MSR_RI) |
7511                    (1ull << MSR_LE);
7512    pcc->mmu_model = POWERPC_MMU_32B;
7513#if defined(CONFIG_SOFTMMU)
7514    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
7515#endif
7516    pcc->excp_model = POWERPC_EXCP_74xx;
7517    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7518    pcc->bfd_mach = bfd_mach_ppc_7400;
7519    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7520                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7521                 POWERPC_FLAG_BUS_CLK;
7522}
7523
7524#if defined(TARGET_PPC64)
7525#if defined(CONFIG_USER_ONLY)
7526#define POWERPC970_HID5_INIT 0x00000080
7527#else
7528#define POWERPC970_HID5_INIT 0x00000000
7529#endif
7530
7531static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
7532                                    int bit, int sprn, int cause)
7533{
7534    TCGv_i32 t1 = tcg_const_i32(bit);
7535    TCGv_i32 t2 = tcg_const_i32(sprn);
7536    TCGv_i32 t3 = tcg_const_i32(cause);
7537
7538    gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
7539
7540    tcg_temp_free_i32(t3);
7541    tcg_temp_free_i32(t2);
7542    tcg_temp_free_i32(t1);
7543}
7544
7545static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
7546                                   int bit, int sprn, int cause)
7547{
7548    TCGv_i32 t1 = tcg_const_i32(bit);
7549    TCGv_i32 t2 = tcg_const_i32(sprn);
7550    TCGv_i32 t3 = tcg_const_i32(cause);
7551
7552    gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
7553
7554    tcg_temp_free_i32(t3);
7555    tcg_temp_free_i32(t2);
7556    tcg_temp_free_i32(t1);
7557}
7558
7559static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
7560{
7561    TCGv spr_up = tcg_temp_new();
7562    TCGv spr = tcg_temp_new();
7563
7564    gen_load_spr(spr, sprn - 1);
7565    tcg_gen_shri_tl(spr_up, spr, 32);
7566    tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
7567
7568    tcg_temp_free(spr);
7569    tcg_temp_free(spr_up);
7570}
7571
7572static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
7573{
7574    TCGv spr = tcg_temp_new();
7575
7576    gen_load_spr(spr, sprn - 1);
7577    tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
7578    gen_store_spr(sprn - 1, spr);
7579
7580    tcg_temp_free(spr);
7581}
7582
7583static int check_pow_970(CPUPPCState *env)
7584{
7585    if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
7586        return 1;
7587    }
7588
7589    return 0;
7590}
7591
7592static void gen_spr_970_hid(CPUPPCState *env)
7593{
7594    /* Hardware implementation registers */
7595    /* XXX : not implemented */
7596    spr_register(env, SPR_HID0, "HID0",
7597                 SPR_NOACCESS, SPR_NOACCESS,
7598                 &spr_read_generic, &spr_write_clear,
7599                 0x60000000);
7600    spr_register(env, SPR_HID1, "HID1",
7601                 SPR_NOACCESS, SPR_NOACCESS,
7602                 &spr_read_generic, &spr_write_generic,
7603                 0x00000000);
7604    spr_register(env, SPR_970_HID5, "HID5",
7605                 SPR_NOACCESS, SPR_NOACCESS,
7606                 &spr_read_generic, &spr_write_generic,
7607                 POWERPC970_HID5_INIT);
7608}
7609
7610static void gen_spr_970_hior(CPUPPCState *env)
7611{
7612    spr_register(env, SPR_HIOR, "SPR_HIOR",
7613                 SPR_NOACCESS, SPR_NOACCESS,
7614                 &spr_read_hior, &spr_write_hior,
7615                 0x00000000);
7616}
7617
7618static void gen_spr_book3s_ctrl(CPUPPCState *env)
7619{
7620    spr_register(env, SPR_CTRL, "SPR_CTRL",
7621                 SPR_NOACCESS, SPR_NOACCESS,
7622                 SPR_NOACCESS, &spr_write_generic,
7623                 0x00000000);
7624    spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7625                 &spr_read_ureg, SPR_NOACCESS,
7626                 &spr_read_ureg, SPR_NOACCESS,
7627                 0x00000000);
7628}
7629
7630static void gen_spr_book3s_altivec(CPUPPCState *env)
7631{
7632    if (!(env->insns_flags & PPC_ALTIVEC)) {
7633        return;
7634    }
7635
7636    spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
7637                     &spr_read_generic, &spr_write_generic,
7638                     &spr_read_generic, &spr_write_generic,
7639                     KVM_REG_PPC_VRSAVE, 0x00000000);
7640
7641    /*
7642     * Can't find information on what this should be on reset.  This
7643     * value is the one used by 74xx processors.
7644     */
7645    vscr_init(env, 0x00010000);
7646}
7647
7648static void gen_spr_book3s_dbg(CPUPPCState *env)
7649{
7650    /*
7651     * TODO: different specs define different scopes for these,
7652     * will have to address this:
7653     * 970: super/write and super/read
7654     * powerisa 2.03..2.04: hypv/write and super/read.
7655     * powerisa 2.05 and newer: hypv/write and hypv/read.
7656     */
7657    spr_register_kvm(env, SPR_DABR, "DABR",
7658                     SPR_NOACCESS, SPR_NOACCESS,
7659                     &spr_read_generic, &spr_write_generic,
7660                     KVM_REG_PPC_DABR, 0x00000000);
7661    spr_register_kvm(env, SPR_DABRX, "DABRX",
7662                     SPR_NOACCESS, SPR_NOACCESS,
7663                     &spr_read_generic, &spr_write_generic,
7664                     KVM_REG_PPC_DABRX, 0x00000000);
7665}
7666
7667static void gen_spr_book3s_207_dbg(CPUPPCState *env)
7668{
7669    spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
7670                        SPR_NOACCESS, SPR_NOACCESS,
7671                        SPR_NOACCESS, SPR_NOACCESS,
7672                        &spr_read_generic, &spr_write_generic,
7673                        KVM_REG_PPC_DAWR, 0x00000000);
7674    spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
7675                        SPR_NOACCESS, SPR_NOACCESS,
7676                        SPR_NOACCESS, SPR_NOACCESS,
7677                        &spr_read_generic, &spr_write_generic,
7678                        KVM_REG_PPC_DAWRX, 0x00000000);
7679    spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
7680                        SPR_NOACCESS, SPR_NOACCESS,
7681                        SPR_NOACCESS, SPR_NOACCESS,
7682                        &spr_read_generic, &spr_write_generic,
7683                        KVM_REG_PPC_CIABR, 0x00000000);
7684}
7685
7686static void gen_spr_970_dbg(CPUPPCState *env)
7687{
7688    /* Breakpoints */
7689    spr_register(env, SPR_IABR, "IABR",
7690                 SPR_NOACCESS, SPR_NOACCESS,
7691                 &spr_read_generic, &spr_write_generic,
7692                 0x00000000);
7693}
7694
7695static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
7696{
7697    spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
7698                     SPR_NOACCESS, SPR_NOACCESS,
7699                     &spr_read_generic, &spr_write_generic,
7700                     KVM_REG_PPC_MMCR0, 0x00000000);
7701    spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
7702                     SPR_NOACCESS, SPR_NOACCESS,
7703                     &spr_read_generic, &spr_write_generic,
7704                     KVM_REG_PPC_MMCR1, 0x00000000);
7705    spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
7706                     SPR_NOACCESS, SPR_NOACCESS,
7707                     &spr_read_generic, &spr_write_generic,
7708                     KVM_REG_PPC_MMCRA, 0x00000000);
7709    spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
7710                     SPR_NOACCESS, SPR_NOACCESS,
7711                     &spr_read_generic, &spr_write_generic,
7712                     KVM_REG_PPC_PMC1, 0x00000000);
7713    spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
7714                     SPR_NOACCESS, SPR_NOACCESS,
7715                     &spr_read_generic, &spr_write_generic,
7716                     KVM_REG_PPC_PMC2, 0x00000000);
7717    spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
7718                     SPR_NOACCESS, SPR_NOACCESS,
7719                     &spr_read_generic, &spr_write_generic,
7720                     KVM_REG_PPC_PMC3, 0x00000000);
7721    spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
7722                     SPR_NOACCESS, SPR_NOACCESS,
7723                     &spr_read_generic, &spr_write_generic,
7724                     KVM_REG_PPC_PMC4, 0x00000000);
7725    spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
7726                     SPR_NOACCESS, SPR_NOACCESS,
7727                     &spr_read_generic, &spr_write_generic,
7728                     KVM_REG_PPC_PMC5, 0x00000000);
7729    spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
7730                     SPR_NOACCESS, SPR_NOACCESS,
7731                     &spr_read_generic, &spr_write_generic,
7732                     KVM_REG_PPC_PMC6, 0x00000000);
7733    spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
7734                     SPR_NOACCESS, SPR_NOACCESS,
7735                     &spr_read_generic, &spr_write_generic,
7736                     KVM_REG_PPC_SIAR, 0x00000000);
7737    spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
7738                     SPR_NOACCESS, SPR_NOACCESS,
7739                     &spr_read_generic, &spr_write_generic,
7740                     KVM_REG_PPC_SDAR, 0x00000000);
7741}
7742
7743static void gen_spr_book3s_pmu_user(CPUPPCState *env)
7744{
7745    spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
7746                 &spr_read_ureg, SPR_NOACCESS,
7747                 &spr_read_ureg, &spr_write_ureg,
7748                 0x00000000);
7749    spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
7750                 &spr_read_ureg, SPR_NOACCESS,
7751                 &spr_read_ureg, &spr_write_ureg,
7752                 0x00000000);
7753    spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
7754                 &spr_read_ureg, SPR_NOACCESS,
7755                 &spr_read_ureg, &spr_write_ureg,
7756                 0x00000000);
7757    spr_register(env, SPR_POWER_UPMC1, "UPMC1",
7758                 &spr_read_ureg, SPR_NOACCESS,
7759                 &spr_read_ureg, &spr_write_ureg,
7760                 0x00000000);
7761    spr_register(env, SPR_POWER_UPMC2, "UPMC2",
7762                 &spr_read_ureg, SPR_NOACCESS,
7763                 &spr_read_ureg, &spr_write_ureg,
7764                 0x00000000);
7765    spr_register(env, SPR_POWER_UPMC3, "UPMC3",
7766                 &spr_read_ureg, SPR_NOACCESS,
7767                 &spr_read_ureg, &spr_write_ureg,
7768                 0x00000000);
7769    spr_register(env, SPR_POWER_UPMC4, "UPMC4",
7770                 &spr_read_ureg, SPR_NOACCESS,
7771                 &spr_read_ureg, &spr_write_ureg,
7772                 0x00000000);
7773    spr_register(env, SPR_POWER_UPMC5, "UPMC5",
7774                 &spr_read_ureg, SPR_NOACCESS,
7775                 &spr_read_ureg, &spr_write_ureg,
7776                 0x00000000);
7777    spr_register(env, SPR_POWER_UPMC6, "UPMC6",
7778                 &spr_read_ureg, SPR_NOACCESS,
7779                 &spr_read_ureg, &spr_write_ureg,
7780                 0x00000000);
7781    spr_register(env, SPR_POWER_USIAR, "USIAR",
7782                 &spr_read_ureg, SPR_NOACCESS,
7783                 &spr_read_ureg, &spr_write_ureg,
7784                 0x00000000);
7785    spr_register(env, SPR_POWER_USDAR, "USDAR",
7786                 &spr_read_ureg, SPR_NOACCESS,
7787                 &spr_read_ureg, &spr_write_ureg,
7788                 0x00000000);
7789}
7790
7791static void gen_spr_970_pmu_sup(CPUPPCState *env)
7792{
7793    spr_register_kvm(env, SPR_970_PMC7, "PMC7",
7794                     SPR_NOACCESS, SPR_NOACCESS,
7795                     &spr_read_generic, &spr_write_generic,
7796                     KVM_REG_PPC_PMC7, 0x00000000);
7797    spr_register_kvm(env, SPR_970_PMC8, "PMC8",
7798                     SPR_NOACCESS, SPR_NOACCESS,
7799                     &spr_read_generic, &spr_write_generic,
7800                     KVM_REG_PPC_PMC8, 0x00000000);
7801}
7802
7803static void gen_spr_970_pmu_user(CPUPPCState *env)
7804{
7805    spr_register(env, SPR_970_UPMC7, "UPMC7",
7806                 &spr_read_ureg, SPR_NOACCESS,
7807                 &spr_read_ureg, &spr_write_ureg,
7808                 0x00000000);
7809    spr_register(env, SPR_970_UPMC8, "UPMC8",
7810                 &spr_read_ureg, SPR_NOACCESS,
7811                 &spr_read_ureg, &spr_write_ureg,
7812                 0x00000000);
7813}
7814
7815static void gen_spr_power8_pmu_sup(CPUPPCState *env)
7816{
7817    spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
7818                     SPR_NOACCESS, SPR_NOACCESS,
7819                     &spr_read_generic, &spr_write_generic,
7820                     KVM_REG_PPC_MMCR2, 0x00000000);
7821    spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
7822                     SPR_NOACCESS, SPR_NOACCESS,
7823                     &spr_read_generic, &spr_write_generic,
7824                     KVM_REG_PPC_MMCRS, 0x00000000);
7825    spr_register_kvm(env, SPR_POWER_SIER, "SIER",
7826                     SPR_NOACCESS, SPR_NOACCESS,
7827                     &spr_read_generic, &spr_write_generic,
7828                     KVM_REG_PPC_SIER, 0x00000000);
7829    spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
7830                     SPR_NOACCESS, SPR_NOACCESS,
7831                     &spr_read_generic, &spr_write_generic,
7832                     KVM_REG_PPC_SPMC1, 0x00000000);
7833    spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
7834                     SPR_NOACCESS, SPR_NOACCESS,
7835                     &spr_read_generic, &spr_write_generic,
7836                     KVM_REG_PPC_SPMC2, 0x00000000);
7837    spr_register_kvm(env, SPR_TACR, "TACR",
7838                     SPR_NOACCESS, SPR_NOACCESS,
7839                     &spr_read_generic, &spr_write_generic,
7840                     KVM_REG_PPC_TACR, 0x00000000);
7841    spr_register_kvm(env, SPR_TCSCR, "TCSCR",
7842                     SPR_NOACCESS, SPR_NOACCESS,
7843                     &spr_read_generic, &spr_write_generic,
7844                     KVM_REG_PPC_TCSCR, 0x00000000);
7845    spr_register_kvm(env, SPR_CSIGR, "CSIGR",
7846                     SPR_NOACCESS, SPR_NOACCESS,
7847                     &spr_read_generic, &spr_write_generic,
7848                     KVM_REG_PPC_CSIGR, 0x00000000);
7849}
7850
7851static void gen_spr_power8_pmu_user(CPUPPCState *env)
7852{
7853    spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
7854                 &spr_read_ureg, SPR_NOACCESS,
7855                 &spr_read_ureg, &spr_write_ureg,
7856                 0x00000000);
7857    spr_register(env, SPR_POWER_USIER, "USIER",
7858                 &spr_read_generic, SPR_NOACCESS,
7859                 &spr_read_generic, &spr_write_generic,
7860                 0x00000000);
7861}
7862
7863static void gen_spr_power5p_ear(CPUPPCState *env)
7864{
7865    /* External access control */
7866    spr_register(env, SPR_EAR, "EAR",
7867                 SPR_NOACCESS, SPR_NOACCESS,
7868                 &spr_read_generic, &spr_write_generic,
7869                 0x00000000);
7870}
7871
7872static void gen_spr_power5p_tb(CPUPPCState *env)
7873{
7874    /* TBU40 (High 40 bits of the Timebase register */
7875    spr_register_hv(env, SPR_TBU40, "TBU40",
7876                    SPR_NOACCESS, SPR_NOACCESS,
7877                    SPR_NOACCESS, SPR_NOACCESS,
7878                    SPR_NOACCESS, &spr_write_tbu40,
7879                    0x00000000);
7880}
7881
7882#if !defined(CONFIG_USER_ONLY)
7883static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
7884{
7885    TCGv hmer = tcg_temp_new();
7886
7887    gen_load_spr(hmer, sprn);
7888    tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
7889    gen_store_spr(sprn, hmer);
7890    spr_store_dump_spr(sprn);
7891    tcg_temp_free(hmer);
7892}
7893
7894static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
7895{
7896    gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
7897}
7898#endif /* !defined(CONFIG_USER_ONLY) */
7899
7900static void gen_spr_970_lpar(CPUPPCState *env)
7901{
7902#if !defined(CONFIG_USER_ONLY)
7903    /*
7904     * PPC970: HID4 covers things later controlled by the LPCR and
7905     * RMOR in later CPUs, but with a different encoding.  We only
7906     * support the 970 in "Apple mode" which has all hypervisor
7907     * facilities disabled by strapping, so we can basically just
7908     * ignore it
7909     */
7910    spr_register(env, SPR_970_HID4, "HID4",
7911                 SPR_NOACCESS, SPR_NOACCESS,
7912                 &spr_read_generic, &spr_write_generic,
7913                 0x00000000);
7914#endif
7915}
7916
7917static void gen_spr_power5p_lpar(CPUPPCState *env)
7918{
7919#if !defined(CONFIG_USER_ONLY)
7920    /* Logical partitionning */
7921    spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
7922                        SPR_NOACCESS, SPR_NOACCESS,
7923                        SPR_NOACCESS, SPR_NOACCESS,
7924                        &spr_read_generic, &spr_write_lpcr,
7925                        KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
7926    spr_register_hv(env, SPR_HDEC, "HDEC",
7927                    SPR_NOACCESS, SPR_NOACCESS,
7928                    SPR_NOACCESS, SPR_NOACCESS,
7929                    &spr_read_hdecr, &spr_write_hdecr, 0);
7930#endif
7931}
7932
7933static void gen_spr_book3s_ids(CPUPPCState *env)
7934{
7935    /* FIXME: Will need to deal with thread vs core only SPRs */
7936
7937    /* Processor identification */
7938    spr_register_hv(env, SPR_PIR, "PIR",
7939                 SPR_NOACCESS, SPR_NOACCESS,
7940                 &spr_read_generic, SPR_NOACCESS,
7941                 &spr_read_generic, NULL,
7942                 0x00000000);
7943    spr_register_hv(env, SPR_HID0, "HID0",
7944                 SPR_NOACCESS, SPR_NOACCESS,
7945                 SPR_NOACCESS, SPR_NOACCESS,
7946                 &spr_read_generic, &spr_write_generic,
7947                 0x00000000);
7948    spr_register_hv(env, SPR_TSCR, "TSCR",
7949                 SPR_NOACCESS, SPR_NOACCESS,
7950                 SPR_NOACCESS, SPR_NOACCESS,
7951                 &spr_read_generic, &spr_write_generic,
7952                 0x00000000);
7953    spr_register_hv(env, SPR_HMER, "HMER",
7954                 SPR_NOACCESS, SPR_NOACCESS,
7955                 SPR_NOACCESS, SPR_NOACCESS,
7956                 &spr_read_generic, &spr_write_hmer,
7957                 0x00000000);
7958    spr_register_hv(env, SPR_HMEER, "HMEER",
7959                 SPR_NOACCESS, SPR_NOACCESS,
7960                 SPR_NOACCESS, SPR_NOACCESS,
7961                 &spr_read_generic, &spr_write_generic,
7962                 0x00000000);
7963    spr_register_hv(env, SPR_TFMR, "TFMR",
7964                 SPR_NOACCESS, SPR_NOACCESS,
7965                 SPR_NOACCESS, SPR_NOACCESS,
7966                 &spr_read_generic, &spr_write_generic,
7967                 0x00000000);
7968    spr_register_hv(env, SPR_LPIDR, "LPIDR",
7969                 SPR_NOACCESS, SPR_NOACCESS,
7970                 SPR_NOACCESS, SPR_NOACCESS,
7971                 &spr_read_generic, &spr_write_lpidr,
7972                 0x00000000);
7973    spr_register_hv(env, SPR_HFSCR, "HFSCR",
7974                 SPR_NOACCESS, SPR_NOACCESS,
7975                 SPR_NOACCESS, SPR_NOACCESS,
7976                 &spr_read_generic, &spr_write_generic,
7977                 0x00000000);
7978    spr_register_hv(env, SPR_MMCRC, "MMCRC",
7979                 SPR_NOACCESS, SPR_NOACCESS,
7980                 SPR_NOACCESS, SPR_NOACCESS,
7981                 &spr_read_generic, &spr_write_generic,
7982                 0x00000000);
7983    spr_register_hv(env, SPR_MMCRH, "MMCRH",
7984                 SPR_NOACCESS, SPR_NOACCESS,
7985                 SPR_NOACCESS, SPR_NOACCESS,
7986                 &spr_read_generic, &spr_write_generic,
7987                 0x00000000);
7988    spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
7989                 SPR_NOACCESS, SPR_NOACCESS,
7990                 SPR_NOACCESS, SPR_NOACCESS,
7991                 &spr_read_generic, &spr_write_generic,
7992                 0x00000000);
7993    spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
7994                 SPR_NOACCESS, SPR_NOACCESS,
7995                 SPR_NOACCESS, SPR_NOACCESS,
7996                 &spr_read_generic, &spr_write_generic,
7997                 0x00000000);
7998    spr_register_hv(env, SPR_HSRR0, "HSRR0",
7999                 SPR_NOACCESS, SPR_NOACCESS,
8000                 SPR_NOACCESS, SPR_NOACCESS,

8001                 &spr_read_generic, &spr_write_generic,
8002                 0x00000000);
8003    spr_register_hv(env, SPR_HSRR1, "HSRR1",
8004                 SPR_NOACCESS, SPR_NOACCESS,
8005                 SPR_NOACCESS, SPR_NOACCESS,
8006                 &spr_read_generic, &spr_write_generic,
8007                 0x00000000);
8008    spr_register_hv(env, SPR_HDAR, "HDAR",
8009                 SPR_NOACCESS, SPR_NOACCESS,
8010                 SPR_NOACCESS, SPR_NOACCESS,
8011                 &spr_read_generic, &spr_write_generic,
8012                 0x00000000);
8013    spr_register_hv(env, SPR_HDSISR, "HDSISR",
8014                 SPR_NOACCESS, SPR_NOACCESS,
8015                 SPR_NOACCESS, SPR_NOACCESS,
8016                 &spr_read_generic, &spr_write_generic,
8017                 0x00000000);
8018    spr_register_hv(env, SPR_HRMOR, "HRMOR",
8019                 SPR_NOACCESS, SPR_NOACCESS,
8020                 SPR_NOACCESS, SPR_NOACCESS,
8021                 &spr_read_generic, &spr_write_generic,
8022                 0x00000000);
8023}
8024
8025static void gen_spr_rmor(CPUPPCState *env)
8026{
8027    spr_register_hv(env, SPR_RMOR, "RMOR",
8028                 SPR_NOACCESS, SPR_NOACCESS,
8029                 SPR_NOACCESS, SPR_NOACCESS,
8030                 &spr_read_generic, &spr_write_generic,
8031                 0x00000000);
8032}
8033
8034static void gen_spr_power8_ids(CPUPPCState *env)
8035{
8036    /* Thread identification */
8037    spr_register(env, SPR_TIR, "TIR",
8038                 SPR_NOACCESS, SPR_NOACCESS,
8039                 &spr_read_generic, SPR_NOACCESS,
8040                 0x00000000);
8041}
8042
8043static void gen_spr_book3s_purr(CPUPPCState *env)
8044{
8045#if !defined(CONFIG_USER_ONLY)
8046    /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
8047    spr_register_kvm_hv(env, SPR_PURR,   "PURR",
8048                        &spr_read_purr, SPR_NOACCESS,
8049                        &spr_read_purr, SPR_NOACCESS,
8050                        &spr_read_purr, &spr_write_purr,
8051                        KVM_REG_PPC_PURR, 0x00000000);
8052    spr_register_kvm_hv(env, SPR_SPURR,   "SPURR",
8053                        &spr_read_purr, SPR_NOACCESS,
8054                        &spr_read_purr, SPR_NOACCESS,
8055                        &spr_read_purr, &spr_write_purr,
8056                        KVM_REG_PPC_SPURR, 0x00000000);
8057#endif
8058}
8059
8060static void gen_spr_power6_dbg(CPUPPCState *env)
8061{
8062#if !defined(CONFIG_USER_ONLY)
8063    spr_register(env, SPR_CFAR, "SPR_CFAR",
8064                 SPR_NOACCESS, SPR_NOACCESS,
8065                 &spr_read_cfar, &spr_write_cfar,
8066                 0x00000000);
8067#endif
8068}
8069
8070static void gen_spr_power5p_common(CPUPPCState *env)
8071{
8072    spr_register_kvm(env, SPR_PPR, "PPR",
8073                     &spr_read_generic, &spr_write_generic,
8074                     &spr_read_generic, &spr_write_generic,
8075                     KVM_REG_PPC_PPR, 0x00000000);
8076}
8077
8078static void gen_spr_power6_common(CPUPPCState *env)
8079{
8080#if !defined(CONFIG_USER_ONLY)
8081    spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
8082                     SPR_NOACCESS, SPR_NOACCESS,
8083                     &spr_read_generic, &spr_write_generic,
8084                     KVM_REG_PPC_DSCR, 0x00000000);
8085#endif
8086    /*
8087     * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
8088     * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
8089     */
8090    spr_register_hv(env, SPR_PCR, "PCR",
8091                 SPR_NOACCESS, SPR_NOACCESS,
8092                 SPR_NOACCESS, SPR_NOACCESS,
8093                 &spr_read_generic, &spr_write_pcr,
8094                 0x00000000);
8095}
8096
8097static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
8098{
8099    gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
8100    spr_read_generic(ctx, gprn, sprn);
8101}
8102
8103static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
8104{
8105    gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
8106    spr_write_generic(ctx, sprn, gprn);
8107}
8108
8109static void gen_spr_power8_tce_address_control(CPUPPCState *env)
8110{
8111    spr_register_kvm(env, SPR_TAR, "TAR",
8112                     &spr_read_tar, &spr_write_tar,
8113                     &spr_read_generic, &spr_write_generic,
8114                     KVM_REG_PPC_TAR, 0x00000000);
8115}
8116
8117static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
8118{
8119    gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8120    spr_read_generic(ctx, gprn, sprn);
8121}
8122
8123static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
8124{
8125    gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8126    spr_write_generic(ctx, sprn, gprn);
8127}
8128
8129static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
8130{
8131    gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8132    spr_read_prev_upper32(ctx, gprn, sprn);
8133}
8134
8135static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
8136{
8137    gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8138    spr_write_prev_upper32(ctx, sprn, gprn);
8139}
8140
8141static void gen_spr_power8_tm(CPUPPCState *env)
8142{
8143    spr_register_kvm(env, SPR_TFHAR, "TFHAR",
8144                     &spr_read_tm, &spr_write_tm,
8145                     &spr_read_tm, &spr_write_tm,
8146                     KVM_REG_PPC_TFHAR, 0x00000000);
8147    spr_register_kvm(env, SPR_TFIAR, "TFIAR",
8148                     &spr_read_tm, &spr_write_tm,
8149                     &spr_read_tm, &spr_write_tm,
8150                     KVM_REG_PPC_TFIAR, 0x00000000);
8151    spr_register_kvm(env, SPR_TEXASR, "TEXASR",
8152                     &spr_read_tm, &spr_write_tm,
8153                     &spr_read_tm, &spr_write_tm,
8154                     KVM_REG_PPC_TEXASR, 0x00000000);
8155    spr_register(env, SPR_TEXASRU, "TEXASRU",
8156                 &spr_read_tm_upper32, &spr_write_tm_upper32,
8157                 &spr_read_tm_upper32, &spr_write_tm_upper32,
8158                 0x00000000);
8159}
8160
8161static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
8162{
8163    gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8164    spr_read_generic(ctx, gprn, sprn);
8165}
8166
8167static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
8168{
8169    gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8170    spr_write_generic(ctx, sprn, gprn);
8171}
8172
8173static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
8174{
8175    gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8176    spr_read_prev_upper32(ctx, gprn, sprn);
8177}
8178
8179static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
8180{
8181    gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8182    spr_write_prev_upper32(ctx, sprn, gprn);
8183}
8184
8185static void gen_spr_power8_ebb(CPUPPCState *env)
8186{
8187    spr_register(env, SPR_BESCRS, "BESCRS",
8188                 &spr_read_ebb, &spr_write_ebb,
8189                 &spr_read_generic, &spr_write_generic,
8190                 0x00000000);
8191    spr_register(env, SPR_BESCRSU, "BESCRSU",
8192                 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
8193                 &spr_read_prev_upper32, &spr_write_prev_upper32,
8194                 0x00000000);
8195    spr_register(env, SPR_BESCRR, "BESCRR",
8196                 &spr_read_ebb, &spr_write_ebb,
8197                 &spr_read_generic, &spr_write_generic,
8198                 0x00000000);
8199    spr_register(env, SPR_BESCRRU, "BESCRRU",
8200                 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
8201                 &spr_read_prev_upper32, &spr_write_prev_upper32,
8202                 0x00000000);
8203    spr_register_kvm(env, SPR_EBBHR, "EBBHR",
8204                     &spr_read_ebb, &spr_write_ebb,
8205                     &spr_read_generic, &spr_write_generic,
8206                     KVM_REG_PPC_EBBHR, 0x00000000);
8207    spr_register_kvm(env, SPR_EBBRR, "EBBRR",
8208                     &spr_read_ebb, &spr_write_ebb,
8209                     &spr_read_generic, &spr_write_generic,
8210                     KVM_REG_PPC_EBBRR, 0x00000000);
8211    spr_register_kvm(env, SPR_BESCR, "BESCR",
8212                     &spr_read_ebb, &spr_write_ebb,
8213                     &spr_read_generic, &spr_write_generic,
8214                     KVM_REG_PPC_BESCR, 0x00000000);
8215}
8216
8217/* Virtual Time Base */
8218static void gen_spr_vtb(CPUPPCState *env)
8219{
8220    spr_register_kvm_hv(env, SPR_VTB, "VTB",
8221                        SPR_NOACCESS, SPR_NOACCESS,
8222                        &spr_read_vtb, SPR_NOACCESS,
8223                        &spr_read_vtb, &spr_write_vtb,
8224                        KVM_REG_PPC_VTB, 0x00000000);
8225}
8226
8227static void gen_spr_power8_fscr(CPUPPCState *env)
8228{
8229#if defined(CONFIG_USER_ONLY)
8230    target_ulong initval = 1ULL << FSCR_TAR;
8231#else
8232    target_ulong initval = 0;
8233#endif
8234    spr_register_kvm(env, SPR_FSCR, "FSCR",
8235                     SPR_NOACCESS, SPR_NOACCESS,
8236                     &spr_read_generic, &spr_write_generic,
8237                     KVM_REG_PPC_FSCR, initval);
8238}
8239
8240static void gen_spr_power8_pspb(CPUPPCState *env)
8241{
8242    spr_register_kvm(env, SPR_PSPB, "PSPB",
8243                     SPR_NOACCESS, SPR_NOACCESS,
8244                     &spr_read_generic, &spr_write_generic32,
8245                     KVM_REG_PPC_PSPB, 0);
8246}
8247
8248static void gen_spr_power8_dpdes(CPUPPCState *env)
8249{
8250#if !defined(CONFIG_USER_ONLY)
8251    /* Directed Privileged Door-bell Exception State, used for IPI */
8252    spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
8253                        SPR_NOACCESS, SPR_NOACCESS,
8254                        &spr_read_dpdes, SPR_NOACCESS,
8255                        &spr_read_dpdes, &spr_write_dpdes,
8256                        KVM_REG_PPC_DPDES, 0x00000000);
8257#endif
8258}
8259
8260static void gen_spr_power8_ic(CPUPPCState *env)
8261{
8262#if !defined(CONFIG_USER_ONLY)
8263    spr_register_hv(env, SPR_IC, "IC",
8264                    SPR_NOACCESS, SPR_NOACCESS,
8265                    &spr_read_generic, SPR_NOACCESS,
8266                    &spr_read_generic, &spr_write_generic,
8267                    0);
8268#endif
8269}
8270
8271static void gen_spr_power8_book4(CPUPPCState *env)
8272{
8273    /* Add a number of P8 book4 registers */
8274#if !defined(CONFIG_USER_ONLY)
8275    spr_register_kvm(env, SPR_ACOP, "ACOP",
8276                     SPR_NOACCESS, SPR_NOACCESS,
8277                     &spr_read_generic, &spr_write_generic,
8278                     KVM_REG_PPC_ACOP, 0);
8279    spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8280                     SPR_NOACCESS, SPR_NOACCESS,
8281                     &spr_read_generic, &spr_write_pidr,
8282                     KVM_REG_PPC_PID, 0);
8283    spr_register_kvm(env, SPR_WORT, "WORT",
8284                     SPR_NOACCESS, SPR_NOACCESS,
8285                     &spr_read_generic, &spr_write_generic,
8286                     KVM_REG_PPC_WORT, 0);
8287#endif
8288}
8289
8290static void gen_spr_power7_book4(CPUPPCState *env)
8291{
8292    /* Add a number of P7 book4 registers */
8293#if !defined(CONFIG_USER_ONLY)
8294    spr_register_kvm(env, SPR_ACOP, "ACOP",
8295                     SPR_NOACCESS, SPR_NOACCESS,
8296                     &spr_read_generic, &spr_write_generic,
8297                     KVM_REG_PPC_ACOP, 0);
8298    spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8299                     SPR_NOACCESS, SPR_NOACCESS,
8300                     &spr_read_generic, &spr_write_generic,
8301                     KVM_REG_PPC_PID, 0);
8302#endif
8303}
8304
8305static void gen_spr_power8_rpr(CPUPPCState *env)
8306{
8307#if !defined(CONFIG_USER_ONLY)
8308    spr_register_hv(env, SPR_RPR, "RPR",
8309                    SPR_NOACCESS, SPR_NOACCESS,
8310                    SPR_NOACCESS, SPR_NOACCESS,
8311                    &spr_read_generic, &spr_write_generic,
8312                    0x00000103070F1F3F);
8313#endif
8314}
8315
8316static void gen_spr_power9_mmu(CPUPPCState *env)
8317{
8318#if !defined(CONFIG_USER_ONLY)
8319    /* Partition Table Control */
8320    spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
8321                        SPR_NOACCESS, SPR_NOACCESS,
8322                        SPR_NOACCESS, SPR_NOACCESS,
8323                        &spr_read_generic, &spr_write_ptcr,
8324                        KVM_REG_PPC_PTCR, 0x00000000);
8325    /* Address Segment Descriptor Register */
8326    spr_register_hv(env, SPR_ASDR, "ASDR",
8327                    SPR_NOACCESS, SPR_NOACCESS,
8328                    SPR_NOACCESS, SPR_NOACCESS,
8329                    &spr_read_generic, &spr_write_generic,
8330                    0x0000000000000000);
8331#endif
8332}
8333
8334static void init_proc_book3s_common(CPUPPCState *env)
8335{
8336    gen_spr_ne_601(env);
8337    gen_tbl(env);
8338    gen_spr_usprg3(env);
8339    gen_spr_book3s_altivec(env);
8340    gen_spr_book3s_pmu_sup(env);
8341    gen_spr_book3s_pmu_user(env);
8342    gen_spr_book3s_ctrl(env);
8343}
8344
8345static void init_proc_970(CPUPPCState *env)
8346{
8347    /* Common Registers */
8348    init_proc_book3s_common(env);
8349    gen_spr_sdr1(env);
8350    gen_spr_book3s_dbg(env);
8351
8352    /* 970 Specific Registers */
8353    gen_spr_970_hid(env);
8354    gen_spr_970_hior(env);
8355    gen_low_BATs(env);
8356    gen_spr_970_pmu_sup(env);
8357    gen_spr_970_pmu_user(env);
8358    gen_spr_970_lpar(env);
8359    gen_spr_970_dbg(env);
8360
8361    /* env variables */
8362    env->dcache_line_size = 128;
8363    env->icache_line_size = 128;
8364
8365    /* Allocate hardware IRQ controller */
8366    init_excp_970(env);
8367    ppc970_irq_init(env_archcpu(env));
8368}
8369
8370POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
8371{
8372    DeviceClass *dc = DEVICE_CLASS(oc);
8373    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8374
8375    dc->desc = "PowerPC 970";
8376    pcc->init_proc = init_proc_970;
8377    pcc->check_pow = check_pow_970;
8378    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8379                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8380                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8381                       PPC_FLOAT_STFIWX |
8382                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8383                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
8384                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8385                       PPC_64B | PPC_ALTIVEC |
8386                       PPC_SEGMENT_64B | PPC_SLBI;
8387    pcc->insns_flags2 = PPC2_FP_CVT_S64;
8388    pcc->msr_mask = (1ull << MSR_SF) |
8389                    (1ull << MSR_VR) |
8390                    (1ull << MSR_POW) |
8391                    (1ull << MSR_EE) |
8392                    (1ull << MSR_PR) |
8393                    (1ull << MSR_FP) |
8394                    (1ull << MSR_ME) |
8395                    (1ull << MSR_FE0) |
8396                    (1ull << MSR_SE) |
8397                    (1ull << MSR_DE) |
8398                    (1ull << MSR_FE1) |
8399                    (1ull << MSR_IR) |
8400                    (1ull << MSR_DR) |
8401                    (1ull << MSR_PMM) |
8402                    (1ull << MSR_RI);
8403    pcc->mmu_model = POWERPC_MMU_64B;
8404#if defined(CONFIG_SOFTMMU)
8405    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8406    pcc->hash64_opts = &ppc_hash64_opts_basic;
8407#endif
8408    pcc->excp_model = POWERPC_EXCP_970;
8409    pcc->bus_model = PPC_FLAGS_INPUT_970;
8410    pcc->bfd_mach = bfd_mach_ppc64;
8411    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8412                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8413                 POWERPC_FLAG_BUS_CLK;
8414    pcc->l1_dcache_size = 0x8000;
8415    pcc->l1_icache_size = 0x10000;
8416}
8417
8418static void init_proc_power5plus(CPUPPCState *env)
8419{
8420    /* Common Registers */
8421    init_proc_book3s_common(env);
8422    gen_spr_sdr1(env);
8423    gen_spr_book3s_dbg(env);
8424
8425    /* POWER5+ Specific Registers */
8426    gen_spr_970_hid(env);
8427    gen_spr_970_hior(env);
8428    gen_low_BATs(env);
8429    gen_spr_970_pmu_sup(env);
8430    gen_spr_970_pmu_user(env);
8431    gen_spr_power5p_common(env);
8432    gen_spr_power5p_lpar(env);
8433    gen_spr_power5p_ear(env);
8434    gen_spr_power5p_tb(env);
8435
8436    /* env variables */
8437    env->dcache_line_size = 128;
8438    env->icache_line_size = 128;
8439
8440    /* Allocate hardware IRQ controller */
8441    init_excp_970(env);
8442    ppc970_irq_init(env_archcpu(env));
8443}
8444
8445POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
8446{
8447    DeviceClass *dc = DEVICE_CLASS(oc);
8448    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8449
8450    dc->fw_name = "PowerPC,POWER5";
8451    dc->desc = "POWER5+";
8452    pcc->init_proc = init_proc_power5plus;
8453    pcc->check_pow = check_pow_970;
8454    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8455                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8456                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8457                       PPC_FLOAT_STFIWX |
8458                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8459                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
8460                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8461                       PPC_64B |
8462                       PPC_SEGMENT_64B | PPC_SLBI;
8463    pcc->insns_flags2 = PPC2_FP_CVT_S64;
8464    pcc->msr_mask = (1ull << MSR_SF) |
8465                    (1ull << MSR_VR) |
8466                    (1ull << MSR_POW) |
8467                    (1ull << MSR_EE) |
8468                    (1ull << MSR_PR) |
8469                    (1ull << MSR_FP) |
8470                    (1ull << MSR_ME) |
8471                    (1ull << MSR_FE0) |
8472                    (1ull << MSR_SE) |
8473                    (1ull << MSR_DE) |
8474                    (1ull << MSR_FE1) |
8475                    (1ull << MSR_IR) |
8476                    (1ull << MSR_DR) |
8477                    (1ull << MSR_PMM) |
8478                    (1ull << MSR_RI);
8479    pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
8480        LPCR_RMI | LPCR_HDICE;
8481    pcc->mmu_model = POWERPC_MMU_2_03;
8482#if defined(CONFIG_SOFTMMU)
8483    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8484    pcc->hash64_opts = &ppc_hash64_opts_basic;
8485    pcc->lrg_decr_bits = 32;
8486#endif
8487    pcc->excp_model = POWERPC_EXCP_970;
8488    pcc->bus_model = PPC_FLAGS_INPUT_970;
8489    pcc->bfd_mach = bfd_mach_ppc64;
8490    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8491                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8492                 POWERPC_FLAG_BUS_CLK;
8493    pcc->l1_dcache_size = 0x8000;
8494    pcc->l1_icache_size = 0x10000;
8495}
8496
8497static void init_proc_POWER7(CPUPPCState *env)
8498{
8499    /* Common Registers */
8500    init_proc_book3s_common(env);
8501    gen_spr_sdr1(env);
8502    gen_spr_book3s_dbg(env);
8503
8504    /* POWER7 Specific Registers */
8505    gen_spr_book3s_ids(env);
8506    gen_spr_rmor(env);
8507    gen_spr_amr(env);
8508    gen_spr_book3s_purr(env);
8509    gen_spr_power5p_common(env);
8510    gen_spr_power5p_lpar(env);
8511    gen_spr_power5p_ear(env);
8512    gen_spr_power5p_tb(env);
8513    gen_spr_power6_common(env);
8514    gen_spr_power6_dbg(env);
8515    gen_spr_power7_book4(env);
8516
8517    /* env variables */
8518    env->dcache_line_size = 128;
8519    env->icache_line_size = 128;
8520
8521    /* Allocate hardware IRQ controller */
8522    init_excp_POWER7(env);
8523    ppcPOWER7_irq_init(env_archcpu(env));
8524}
8525
8526static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
8527{
8528    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
8529        return true;
8530    }
8531    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
8532        return true;
8533    }
8534    return false;
8535}
8536
8537static bool cpu_has_work_POWER7(CPUState *cs)
8538{
8539    PowerPCCPU *cpu = POWERPC_CPU(cs);
8540    CPUPPCState *env = &cpu->env;
8541
8542    if (cs->halted) {
8543        if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8544            return false;
8545        }
8546        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8547            (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
8548            return true;
8549        }
8550        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8551            (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
8552            return true;
8553        }
8554        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
8555            (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
8556            return true;
8557        }
8558        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
8559            (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
8560            return true;
8561        }
8562        if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8563            return true;
8564        }
8565        return false;
8566    } else {
8567        return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8568    }
8569}
8570
8571POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
8572{
8573    DeviceClass *dc = DEVICE_CLASS(oc);
8574    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8575    CPUClass *cc = CPU_CLASS(oc);
8576
8577    dc->fw_name = "PowerPC,POWER7";
8578    dc->desc = "POWER7";
8579    pcc->pvr_match = ppc_pvr_match_power7;
8580    pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
8581    pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8582    pcc->init_proc = init_proc_POWER7;
8583    pcc->check_pow = check_pow_nocheck;
8584    cc->has_work = cpu_has_work_POWER7;
8585    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8586                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8587                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8588                       PPC_FLOAT_FRSQRTES |
8589                       PPC_FLOAT_STFIWX |
8590                       PPC_FLOAT_EXT |
8591                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8592                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
8593                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8594                       PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8595                       PPC_SEGMENT_64B | PPC_SLBI |
8596                       PPC_POPCNTB | PPC_POPCNTWD |
8597                       PPC_CILDST;
8598    pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
8599                        PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8600                        PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8601                        PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
8602                        PPC2_PM_ISA206;
8603    pcc->msr_mask = (1ull << MSR_SF) |
8604                    (1ull << MSR_VR) |
8605                    (1ull << MSR_VSX) |
8606                    (1ull << MSR_EE) |
8607                    (1ull << MSR_PR) |
8608                    (1ull << MSR_FP) |
8609                    (1ull << MSR_ME) |
8610                    (1ull << MSR_FE0) |
8611                    (1ull << MSR_SE) |
8612                    (1ull << MSR_DE) |
8613                    (1ull << MSR_FE1) |
8614                    (1ull << MSR_IR) |
8615                    (1ull << MSR_DR) |
8616                    (1ull << MSR_PMM) |
8617                    (1ull << MSR_RI) |
8618                    (1ull << MSR_LE);
8619    pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
8620        LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
8621        LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
8622        LPCR_MER | LPCR_TC |
8623        LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
8624    pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
8625    pcc->mmu_model = POWERPC_MMU_2_06;
8626#if defined(CONFIG_SOFTMMU)
8627    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8628    pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8629    pcc->lrg_decr_bits = 32;
8630#endif
8631    pcc->excp_model = POWERPC_EXCP_POWER7;
8632    pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8633    pcc->bfd_mach = bfd_mach_ppc64;
8634    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8635                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8636                 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8637                 POWERPC_FLAG_VSX;
8638    pcc->l1_dcache_size = 0x8000;
8639    pcc->l1_icache_size = 0x8000;
8640    pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8641}
8642
8643static void init_proc_POWER8(CPUPPCState *env)
8644{
8645    /* Common Registers */
8646    init_proc_book3s_common(env);
8647    gen_spr_sdr1(env);
8648    gen_spr_book3s_207_dbg(env);
8649
8650    /* POWER8 Specific Registers */
8651    gen_spr_book3s_ids(env);
8652    gen_spr_rmor(env);
8653    gen_spr_amr(env);
8654    gen_spr_iamr(env);
8655    gen_spr_book3s_purr(env);
8656    gen_spr_power5p_common(env);
8657    gen_spr_power5p_lpar(env);
8658    gen_spr_power5p_ear(env);
8659    gen_spr_power5p_tb(env);
8660    gen_spr_power6_common(env);
8661    gen_spr_power6_dbg(env);
8662    gen_spr_power8_tce_address_control(env);
8663    gen_spr_power8_ids(env);
8664    gen_spr_power8_ebb(env);
8665    gen_spr_power8_fscr(env);
8666    gen_spr_power8_pmu_sup(env);
8667    gen_spr_power8_pmu_user(env);
8668    gen_spr_power8_tm(env);
8669    gen_spr_power8_pspb(env);
8670    gen_spr_power8_dpdes(env);
8671    gen_spr_vtb(env);
8672    gen_spr_power8_ic(env);
8673    gen_spr_power8_book4(env);
8674    gen_spr_power8_rpr(env);
8675
8676    /* env variables */
8677    env->dcache_line_size = 128;
8678    env->icache_line_size = 128;
8679
8680    /* Allocate hardware IRQ controller */
8681    init_excp_POWER8(env);
8682    ppcPOWER7_irq_init(env_archcpu(env));
8683}
8684
8685static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
8686{
8687    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
8688        return true;
8689    }
8690    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
8691        return true;
8692    }
8693    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
8694        return true;
8695    }
8696    return false;
8697}
8698
8699static bool cpu_has_work_POWER8(CPUState *cs)
8700{
8701    PowerPCCPU *cpu = POWERPC_CPU(cs);
8702    CPUPPCState *env = &cpu->env;
8703
8704    if (cs->halted) {
8705        if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8706            return false;
8707        }
8708        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8709            (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
8710            return true;
8711        }
8712        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8713            (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
8714            return true;
8715        }
8716        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
8717            (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
8718            return true;
8719        }
8720        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
8721            (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
8722            return true;
8723        }
8724        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8725            (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
8726            return true;
8727        }
8728        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8729            (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
8730            return true;
8731        }
8732        if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8733            return true;
8734        }
8735        return false;
8736    } else {
8737        return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8738    }
8739}
8740
8741POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
8742{
8743    DeviceClass *dc = DEVICE_CLASS(oc);
8744    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8745    CPUClass *cc = CPU_CLASS(oc);
8746
8747    dc->fw_name = "PowerPC,POWER8";
8748    dc->desc = "POWER8";
8749    pcc->pvr_match = ppc_pvr_match_power8;
8750    pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8751    pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8752    pcc->init_proc = init_proc_POWER8;
8753    pcc->check_pow = check_pow_nocheck;
8754    cc->has_work = cpu_has_work_POWER8;
8755    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8756                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8757                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8758                       PPC_FLOAT_FRSQRTES |
8759                       PPC_FLOAT_STFIWX |
8760                       PPC_FLOAT_EXT |
8761                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8762                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
8763                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8764                       PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8765                       PPC_SEGMENT_64B | PPC_SLBI |
8766                       PPC_POPCNTB | PPC_POPCNTWD |
8767                       PPC_CILDST;
8768    pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8769                        PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8770                        PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8771                        PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8772                        PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8773                        PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8774                        PPC2_TM | PPC2_PM_ISA206;
8775    pcc->msr_mask = (1ull << MSR_SF) |
8776                    (1ull << MSR_HV) |
8777                    (1ull << MSR_TM) |
8778                    (1ull << MSR_VR) |
8779                    (1ull << MSR_VSX) |
8780                    (1ull << MSR_EE) |
8781                    (1ull << MSR_PR) |
8782                    (1ull << MSR_FP) |
8783                    (1ull << MSR_ME) |
8784                    (1ull << MSR_FE0) |
8785                    (1ull << MSR_SE) |
8786                    (1ull << MSR_DE) |
8787                    (1ull << MSR_FE1) |
8788                    (1ull << MSR_IR) |
8789                    (1ull << MSR_DR) |
8790                    (1ull << MSR_PMM) |
8791                    (1ull << MSR_RI) |
8792                    (1ull << MSR_TS0) |
8793                    (1ull << MSR_TS1) |
8794                    (1ull << MSR_LE);
8795    pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
8796        LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
8797        LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
8798        LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
8799        LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
8800    pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
8801                   LPCR_P8_PECE3 | LPCR_P8_PECE4;
8802    pcc->mmu_model = POWERPC_MMU_2_07;
8803#if defined(CONFIG_SOFTMMU)
8804    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8805    pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8806    pcc->lrg_decr_bits = 32;
8807    pcc->n_host_threads = 8;
8808#endif
8809    pcc->excp_model = POWERPC_EXCP_POWER8;
8810    pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8811    pcc->bfd_mach = bfd_mach_ppc64;
8812    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8813                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8814                 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8815                 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
8816    pcc->l1_dcache_size = 0x8000;
8817    pcc->l1_icache_size = 0x8000;
8818    pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8819}
8820
8821#ifdef CONFIG_SOFTMMU
8822/*
8823 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
8824 * Encoded as array of int_32s in the form:
8825 *  0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
8826 *  x -> AP encoding
8827 *  y -> radix mode supported page size (encoded as a shift)
8828 */
8829static struct ppc_radix_page_info POWER9_radix_page_info = {
8830    .count = 4,
8831    .entries = {
8832        0x0000000c, /*  4K - enc: 0x0 */
8833        0xa0000010, /* 64K - enc: 0x5 */
8834        0x20000015, /*  2M - enc: 0x1 */
8835        0x4000001e  /*  1G - enc: 0x2 */
8836    }
8837};
8838#endif /* CONFIG_SOFTMMU */
8839
8840static void init_proc_POWER9(CPUPPCState *env)
8841{
8842    /* Common Registers */
8843    init_proc_book3s_common(env);
8844    gen_spr_book3s_207_dbg(env);
8845
8846    /* POWER8 Specific Registers */
8847    gen_spr_book3s_ids(env);
8848    gen_spr_amr(env);
8849    gen_spr_iamr(env);
8850    gen_spr_book3s_purr(env);
8851    gen_spr_power5p_common(env);
8852    gen_spr_power5p_lpar(env);
8853    gen_spr_power5p_ear(env);
8854    gen_spr_power5p_tb(env);
8855    gen_spr_power6_common(env);
8856    gen_spr_power6_dbg(env);
8857    gen_spr_power8_tce_address_control(env);
8858    gen_spr_power8_ids(env);
8859    gen_spr_power8_ebb(env);
8860    gen_spr_power8_fscr(env);
8861    gen_spr_power8_pmu_sup(env);
8862    gen_spr_power8_pmu_user(env);
8863    gen_spr_power8_tm(env);
8864    gen_spr_power8_pspb(env);
8865    gen_spr_power8_dpdes(env);
8866    gen_spr_vtb(env);
8867    gen_spr_power8_ic(env);
8868    gen_spr_power8_book4(env);
8869    gen_spr_power8_rpr(env);
8870    gen_spr_power9_mmu(env);
8871
8872    /* POWER9 Specific registers */
8873    spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
8874                     spr_read_generic, spr_write_generic,
8875                     KVM_REG_PPC_TIDR, 0);
8876
8877    /* FIXME: Filter fields properly based on privilege level */
8878    spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
8879                        spr_read_generic, spr_write_generic,
8880                        KVM_REG_PPC_PSSCR, 0);
8881
8882    /* env variables */
8883    env->dcache_line_size = 128;
8884    env->icache_line_size = 128;
8885
8886    /* Allocate hardware IRQ controller */
8887    init_excp_POWER9(env);
8888    ppcPOWER9_irq_init(env_archcpu(env));
8889}
8890
8891static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
8892{
8893    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
8894        return true;
8895    }
8896    return false;
8897}
8898
8899static bool cpu_has_work_POWER9(CPUState *cs)
8900{
8901    PowerPCCPU *cpu = POWERPC_CPU(cs);
8902    CPUPPCState *env = &cpu->env;
8903
8904    if (cs->halted) {
8905        uint64_t psscr = env->spr[SPR_PSSCR];
8906
8907        if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8908            return false;
8909        }
8910
8911        /* If EC is clear, just return true on any pending interrupt */
8912        if (!(psscr & PSSCR_EC)) {
8913            return true;
8914        }
8915        /* External Exception */
8916        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8917            (env->spr[SPR_LPCR] & LPCR_EEE)) {
8918            bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
8919            if (heic == 0 || !msr_hv || msr_pr) {
8920                return true;
8921            }
8922        }
8923        /* Decrementer Exception */
8924        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8925            (env->spr[SPR_LPCR] & LPCR_DEE)) {
8926            return true;
8927        }
8928        /* Machine Check or Hypervisor Maintenance Exception */
8929        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
8930            1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
8931            return true;
8932        }
8933        /* Privileged Doorbell Exception */
8934        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8935            (env->spr[SPR_LPCR] & LPCR_PDEE)) {
8936            return true;
8937        }
8938        /* Hypervisor Doorbell Exception */
8939        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8940            (env->spr[SPR_LPCR] & LPCR_HDEE)) {
8941            return true;
8942        }
8943        /* Hypervisor virtualization exception */
8944        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
8945            (env->spr[SPR_LPCR] & LPCR_HVEE)) {
8946            return true;
8947        }
8948        if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8949            return true;
8950        }
8951        return false;
8952    } else {
8953        return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8954    }
8955}
8956
8957POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
8958{
8959    DeviceClass *dc = DEVICE_CLASS(oc);
8960    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8961    CPUClass *cc = CPU_CLASS(oc);
8962
8963    dc->fw_name = "PowerPC,POWER9";
8964    dc->desc = "POWER9";
8965    pcc->pvr_match = ppc_pvr_match_power9;
8966    pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
8967    pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
8968                         PCR_COMPAT_2_05;
8969    pcc->init_proc = init_proc_POWER9;
8970    pcc->check_pow = check_pow_nocheck;
8971    cc->has_work = cpu_has_work_POWER9;
8972    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8973                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8974                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8975                       PPC_FLOAT_FRSQRTES |
8976                       PPC_FLOAT_STFIWX |
8977                       PPC_FLOAT_EXT |
8978                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8979                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
8980                       PPC_MEM_TLBSYNC |
8981                       PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8982                       PPC_SEGMENT_64B | PPC_SLBI |
8983                       PPC_POPCNTB | PPC_POPCNTWD |
8984                       PPC_CILDST;
8985    pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8986                        PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8987                        PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8988                        PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8989                        PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8990                        PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8991                        PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
8992    pcc->msr_mask = (1ull << MSR_SF) |
8993                    (1ull << MSR_HV) |
8994                    (1ull << MSR_TM) |
8995                    (1ull << MSR_VR) |
8996                    (1ull << MSR_VSX) |
8997                    (1ull << MSR_EE) |
8998                    (1ull << MSR_PR) |
8999                    (1ull << MSR_FP) |
9000                    (1ull << MSR_ME) |

9001                    (1ull << MSR_FE0) |
9002                    (1ull << MSR_SE) |
9003                    (1ull << MSR_DE) |
9004                    (1ull << MSR_FE1) |
9005                    (1ull << MSR_IR) |
9006                    (1ull << MSR_DR) |
9007                    (1ull << MSR_PMM) |
9008                    (1ull << MSR_RI) |
9009                    (1ull << MSR_LE);
9010    pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
9011        (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
9012        LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
9013        (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
9014                             LPCR_DEE | LPCR_OEE))
9015        | LPCR_MER | LPCR_GTSE | LPCR_TC |
9016        LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
9017    pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
9018    pcc->mmu_model = POWERPC_MMU_3_00;
9019#if defined(CONFIG_SOFTMMU)
9020    pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
9021    /* segment page size remain the same */
9022    pcc->hash64_opts = &ppc_hash64_opts_POWER7;
9023    pcc->radix_page_info = &POWER9_radix_page_info;
9024    pcc->lrg_decr_bits = 56;
9025    pcc->n_host_threads = 4;
9026#endif
9027    pcc->excp_model = POWERPC_EXCP_POWER9;
9028    pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
9029    pcc->bfd_mach = bfd_mach_ppc64;
9030    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
9031                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
9032                 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
9033                 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
9034    pcc->l1_dcache_size = 0x8000;
9035    pcc->l1_icache_size = 0x8000;
9036    pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
9037}
9038
9039#ifdef CONFIG_SOFTMMU
9040/*
9041 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
9042 * Encoded as array of int_32s in the form:
9043 *  0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
9044 *  x -> AP encoding
9045 *  y -> radix mode supported page size (encoded as a shift)
9046 */
9047static struct ppc_radix_page_info POWER10_radix_page_info = {
9048    .count = 4,
9049    .entries = {
9050        0x0000000c, /*  4K - enc: 0x0 */
9051        0xa0000010, /* 64K - enc: 0x5 */
9052        0x20000015, /*  2M - enc: 0x1 */
9053        0x4000001e  /*  1G - enc: 0x2 */
9054    }
9055};
9056#endif /* CONFIG_SOFTMMU */
9057
9058static void init_proc_POWER10(CPUPPCState *env)
9059{
9060    /* Common Registers */
9061    init_proc_book3s_common(env);
9062    gen_spr_book3s_207_dbg(env);
9063
9064    /* POWER8 Specific Registers */
9065    gen_spr_book3s_ids(env);
9066    gen_spr_amr(env);
9067    gen_spr_iamr(env);
9068    gen_spr_book3s_purr(env);
9069    gen_spr_power5p_common(env);
9070    gen_spr_power5p_lpar(env);
9071    gen_spr_power5p_ear(env);
9072    gen_spr_power6_common(env);
9073    gen_spr_power6_dbg(env);
9074    gen_spr_power8_tce_address_control(env);
9075    gen_spr_power8_ids(env);
9076    gen_spr_power8_ebb(env);
9077    gen_spr_power8_fscr(env);
9078    gen_spr_power8_pmu_sup(env);
9079    gen_spr_power8_pmu_user(env);
9080    gen_spr_power8_tm(env);
9081    gen_spr_power8_pspb(env);
9082    gen_spr_vtb(env);
9083    gen_spr_power8_ic(env);
9084    gen_spr_power8_book4(env);
9085    gen_spr_power8_rpr(env);
9086    gen_spr_power9_mmu(env);
9087
9088    /* POWER9 Specific registers */
9089    spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
9090                     spr_read_generic, spr_write_generic,
9091                     KVM_REG_PPC_TIDR, 0);
9092
9093    /* FIXME: Filter fields properly based on privilege level */
9094    spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
9095                        spr_read_generic, spr_write_generic,
9096                        KVM_REG_PPC_PSSCR, 0);
9097
9098    /* env variables */
9099    env->dcache_line_size = 128;
9100    env->icache_line_size = 128;
9101
9102    /* Allocate hardware IRQ controller */
9103    init_excp_POWER10(env);
9104    ppcPOWER9_irq_init(env_archcpu(env));
9105}
9106
9107static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
9108{
9109    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
9110        return true;
9111    }
9112    return false;
9113}
9114
9115static bool cpu_has_work_POWER10(CPUState *cs)
9116{
9117    PowerPCCPU *cpu = POWERPC_CPU(cs);
9118    CPUPPCState *env = &cpu->env;
9119
9120    if (cs->halted) {
9121        uint64_t psscr = env->spr[SPR_PSSCR];
9122
9123        if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
9124            return false;
9125        }
9126
9127        /* If EC is clear, just return true on any pending interrupt */
9128        if (!(psscr & PSSCR_EC)) {
9129            return true;
9130        }
9131        /* External Exception */
9132        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
9133            (env->spr[SPR_LPCR] & LPCR_EEE)) {
9134            bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
9135            if (heic == 0 || !msr_hv || msr_pr) {
9136                return true;
9137            }
9138        }
9139        /* Decrementer Exception */
9140        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
9141            (env->spr[SPR_LPCR] & LPCR_DEE)) {
9142            return true;
9143        }
9144        /* Machine Check or Hypervisor Maintenance Exception */
9145        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
9146            1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
9147            return true;
9148        }
9149        /* Privileged Doorbell Exception */
9150        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
9151            (env->spr[SPR_LPCR] & LPCR_PDEE)) {
9152            return true;
9153        }
9154        /* Hypervisor Doorbell Exception */
9155        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
9156            (env->spr[SPR_LPCR] & LPCR_HDEE)) {
9157            return true;
9158        }
9159        /* Hypervisor virtualization exception */
9160        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
9161            (env->spr[SPR_LPCR] & LPCR_HVEE)) {
9162            return true;
9163        }
9164        if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
9165            return true;
9166        }
9167        return false;
9168    } else {
9169        return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
9170    }
9171}
9172
9173POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
9174{
9175    DeviceClass *dc = DEVICE_CLASS(oc);
9176    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9177    CPUClass *cc = CPU_CLASS(oc);
9178
9179    dc->fw_name = "PowerPC,POWER10";
9180    dc->desc = "POWER10";
9181    pcc->pvr_match = ppc_pvr_match_power10;
9182    pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
9183                    PCR_COMPAT_3_00;
9184    pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
9185                         PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
9186    pcc->init_proc = init_proc_POWER10;
9187    pcc->check_pow = check_pow_nocheck;
9188    cc->has_work = cpu_has_work_POWER10;
9189    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
9190                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
9191                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
9192                       PPC_FLOAT_FRSQRTES |
9193                       PPC_FLOAT_STFIWX |
9194                       PPC_FLOAT_EXT |
9195                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
9196                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
9197                       PPC_MEM_TLBSYNC |
9198                       PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
9199                       PPC_SEGMENT_64B | PPC_SLBI |
9200                       PPC_POPCNTB | PPC_POPCNTWD |
9201                       PPC_CILDST;
9202    pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
9203                        PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
9204                        PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
9205                        PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
9206                        PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
9207                        PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
9208                        PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
9209    pcc->msr_mask = (1ull << MSR_SF) |
9210                    (1ull << MSR_HV) |
9211                    (1ull << MSR_TM) |
9212                    (1ull << MSR_VR) |
9213                    (1ull << MSR_VSX) |
9214                    (1ull << MSR_EE) |
9215                    (1ull << MSR_PR) |
9216                    (1ull << MSR_FP) |
9217                    (1ull << MSR_ME) |
9218                    (1ull << MSR_FE0) |
9219                    (1ull << MSR_SE) |
9220                    (1ull << MSR_DE) |
9221                    (1ull << MSR_FE1) |
9222                    (1ull << MSR_IR) |
9223                    (1ull << MSR_DR) |
9224                    (1ull << MSR_PMM) |
9225                    (1ull << MSR_RI) |
9226                    (1ull << MSR_LE);
9227    pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
9228        (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
9229        LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
9230        (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
9231                             LPCR_DEE | LPCR_OEE))
9232        | LPCR_MER | LPCR_GTSE | LPCR_TC |
9233        LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
9234    pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
9235    pcc->mmu_model = POWERPC_MMU_3_00;
9236#if defined(CONFIG_SOFTMMU)
9237    pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
9238    /* segment page size remain the same */
9239    pcc->hash64_opts = &ppc_hash64_opts_POWER7;
9240    pcc->radix_page_info = &POWER10_radix_page_info;
9241    pcc->lrg_decr_bits = 56;
9242#endif
9243    pcc->excp_model = POWERPC_EXCP_POWER9;
9244    pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
9245    pcc->bfd_mach = bfd_mach_ppc64;
9246    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
9247                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
9248                 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
9249                 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
9250    pcc->l1_dcache_size = 0x8000;
9251    pcc->l1_icache_size = 0x8000;
9252    pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
9253}
9254
9255#if !defined(CONFIG_USER_ONLY)
9256void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
9257{
9258    CPUPPCState *env = &cpu->env;
9259
9260    cpu->vhyp = vhyp;
9261
9262    /*
9263     * With a virtual hypervisor mode we never allow the CPU to go
9264     * hypervisor mode itself
9265     */
9266    env->msr_mask &= ~MSR_HVB;
9267}
9268
9269#endif /* !defined(CONFIG_USER_ONLY) */
9270
9271#endif /* defined(TARGET_PPC64) */
9272
9273/*****************************************************************************/
9274/* Generic CPU instantiation routine                                         */
9275static void init_ppc_proc(PowerPCCPU *cpu)
9276{
9277    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9278    CPUPPCState *env = &cpu->env;
9279#if !defined(CONFIG_USER_ONLY)
9280    int i;
9281
9282    env->irq_inputs = NULL;
9283    /* Set all exception vectors to an invalid address */
9284    for (i = 0; i < POWERPC_EXCP_NB; i++) {
9285        env->excp_vectors[i] = (target_ulong)(-1ULL);
9286    }
9287    env->ivor_mask = 0x00000000;
9288    env->ivpr_mask = 0x00000000;
9289    /* Default MMU definitions */
9290    env->nb_BATs = 0;
9291    env->nb_tlb = 0;
9292    env->nb_ways = 0;
9293    env->tlb_type = TLB_NONE;
9294#endif
9295    /* Register SPR common to all PowerPC implementations */
9296    gen_spr_generic(env);
9297    spr_register(env, SPR_PVR, "PVR",
9298                 /* Linux permits userspace to read PVR */
9299#if defined(CONFIG_LINUX_USER)
9300                 &spr_read_generic,
9301#else
9302                 SPR_NOACCESS,
9303#endif
9304                 SPR_NOACCESS,
9305                 &spr_read_generic, SPR_NOACCESS,
9306                 pcc->pvr);
9307    /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9308    if (pcc->svr != POWERPC_SVR_NONE) {
9309        if (pcc->svr & POWERPC_SVR_E500) {
9310            spr_register(env, SPR_E500_SVR, "SVR",
9311                         SPR_NOACCESS, SPR_NOACCESS,
9312                         &spr_read_generic, SPR_NOACCESS,
9313                         pcc->svr & ~POWERPC_SVR_E500);
9314        } else {
9315            spr_register(env, SPR_SVR, "SVR",
9316                         SPR_NOACCESS, SPR_NOACCESS,
9317                         &spr_read_generic, SPR_NOACCESS,
9318                         pcc->svr);
9319        }
9320    }
9321    /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9322    (*pcc->init_proc)(env);
9323
9324#if !defined(CONFIG_USER_ONLY)
9325    ppc_gdb_gen_spr_xml(cpu);
9326#endif
9327
9328    /* MSR bits & flags consistency checks */
9329    if (env->msr_mask & (1 << 25)) {
9330        switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9331        case POWERPC_FLAG_SPE:
9332        case POWERPC_FLAG_VRE:
9333            break;
9334        default:
9335            fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9336                    "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9337            exit(1);
9338        }
9339    } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9340        fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9341                "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9342        exit(1);
9343    }
9344    if (env->msr_mask & (1 << 17)) {
9345        switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9346        case POWERPC_FLAG_TGPR:
9347        case POWERPC_FLAG_CE:
9348            break;
9349        default:
9350            fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9351                    "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9352            exit(1);
9353        }
9354    } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9355        fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9356                "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9357        exit(1);
9358    }
9359    if (env->msr_mask & (1 << 10)) {
9360        switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9361                              POWERPC_FLAG_UBLE)) {
9362        case POWERPC_FLAG_SE:
9363        case POWERPC_FLAG_DWE:
9364        case POWERPC_FLAG_UBLE:
9365            break;
9366        default:
9367            fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9368                    "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9369                    "POWERPC_FLAG_UBLE\n");
9370            exit(1);
9371        }
9372    } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9373                             POWERPC_FLAG_UBLE)) {
9374        fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9375                "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9376                "POWERPC_FLAG_UBLE\n");
9377            exit(1);
9378    }
9379    if (env->msr_mask & (1 << 9)) {
9380        switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9381        case POWERPC_FLAG_BE:
9382        case POWERPC_FLAG_DE:
9383            break;
9384        default:
9385            fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9386                    "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9387            exit(1);
9388        }
9389    } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9390        fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9391                "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9392        exit(1);
9393    }
9394    if (env->msr_mask & (1 << 2)) {
9395        switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9396        case POWERPC_FLAG_PX:
9397        case POWERPC_FLAG_PMM:
9398            break;
9399        default:
9400            fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9401                    "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9402            exit(1);
9403        }
9404    } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9405        fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9406                "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9407        exit(1);
9408    }
9409    if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9410        fprintf(stderr, "PowerPC flags inconsistency\n"
9411                "Should define the time-base and decrementer clock source\n");
9412        exit(1);
9413    }
9414    /* Allocate TLBs buffer when needed */
9415#if !defined(CONFIG_USER_ONLY)
9416    if (env->nb_tlb != 0) {
9417        int nb_tlb = env->nb_tlb;
9418        if (env->id_tlbs != 0) {
9419            nb_tlb *= 2;
9420        }
9421        switch (env->tlb_type) {
9422        case TLB_6XX:
9423            env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
9424            break;
9425        case TLB_EMB:
9426            env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
9427            break;
9428        case TLB_MAS:
9429            env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
9430            break;
9431        }
9432        /* Pre-compute some useful values */
9433        env->tlb_per_way = env->nb_tlb / env->nb_ways;
9434    }
9435    if (env->irq_inputs == NULL) {
9436        warn_report("no internal IRQ controller registered."
9437                    " Attempt QEMU to crash very soon !");
9438    }
9439#endif
9440    if (env->check_pow == NULL) {
9441        warn_report("no power management check handler registered."
9442                    " Attempt QEMU to crash very soon !");
9443    }
9444}
9445
9446#if defined(PPC_DUMP_CPU)
9447static void dump_ppc_sprs(CPUPPCState *env)
9448{
9449    ppc_spr_t *spr;
9450#if !defined(CONFIG_USER_ONLY)
9451    uint32_t sr, sw;
9452#endif
9453    uint32_t ur, uw;
9454    int i, j, n;
9455
9456    printf("Special purpose registers:\n");
9457    for (i = 0; i < 32; i++) {
9458        for (j = 0; j < 32; j++) {
9459            n = (i << 5) | j;
9460            spr = &env->spr_cb[n];
9461            uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9462            ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9463#if !defined(CONFIG_USER_ONLY)
9464            sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9465            sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9466            if (sw || sr || uw || ur) {
9467                printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9468                       (i << 5) | j, (i << 5) | j, spr->name,
9469                       sw ? 'w' : '-', sr ? 'r' : '-',
9470                       uw ? 'w' : '-', ur ? 'r' : '-');
9471            }
9472#else
9473            if (uw || ur) {
9474                printf("SPR: %4d (%03x) %-8s u%c%c\n",
9475                       (i << 5) | j, (i << 5) | j, spr->name,
9476                       uw ? 'w' : '-', ur ? 'r' : '-');
9477            }
9478#endif
9479        }
9480    }
9481    fflush(stdout);
9482    fflush(stderr);
9483}
9484#endif
9485
9486/*****************************************************************************/
9487
9488/* Opcode types */
9489enum {
9490    PPC_DIRECT   = 0, /* Opcode routine        */
9491    PPC_INDIRECT = 1, /* Indirect opcode table */
9492};
9493
9494#define PPC_OPCODE_MASK 0x3
9495
9496static inline int is_indirect_opcode(void *handler)
9497{
9498    return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
9499}
9500
9501static inline opc_handler_t **ind_table(void *handler)
9502{
9503    return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
9504}
9505
9506/* Instruction table creation */
9507/* Opcodes tables creation */
9508static void fill_new_table(opc_handler_t **table, int len)
9509{
9510    int i;
9511
9512    for (i = 0; i < len; i++) {
9513        table[i] = &invalid_handler;
9514    }
9515}
9516
9517static int create_new_table(opc_handler_t **table, unsigned char idx)
9518{
9519    opc_handler_t **tmp;
9520
9521    tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
9522    fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
9523    table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
9524
9525    return 0;
9526}
9527
9528static int insert_in_table(opc_handler_t **table, unsigned char idx,
9529                            opc_handler_t *handler)
9530{
9531    if (table[idx] != &invalid_handler) {
9532        return -1;
9533    }
9534    table[idx] = handler;
9535
9536    return 0;
9537}
9538
9539static int register_direct_insn(opc_handler_t **ppc_opcodes,
9540                                unsigned char idx, opc_handler_t *handler)
9541{
9542    if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9543        printf("*** ERROR: opcode %02x already assigned in main "
9544               "opcode table\n", idx);
9545#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9546        printf("           Registered handler '%s' - new handler '%s'\n",
9547               ppc_opcodes[idx]->oname, handler->oname);
9548#endif
9549        return -1;
9550    }
9551
9552    return 0;
9553}
9554
9555static int register_ind_in_table(opc_handler_t **table,
9556                                 unsigned char idx1, unsigned char idx2,
9557                                 opc_handler_t *handler)
9558{
9559    if (table[idx1] == &invalid_handler) {
9560        if (create_new_table(table, idx1) < 0) {
9561            printf("*** ERROR: unable to create indirect table "
9562                   "idx=%02x\n", idx1);
9563            return -1;
9564        }
9565    } else {
9566        if (!is_indirect_opcode(table[idx1])) {
9567            printf("*** ERROR: idx %02x already assigned to a direct "
9568                   "opcode\n", idx1);
9569#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9570            printf("           Registered handler '%s' - new handler '%s'\n",
9571                   ind_table(table[idx1])[idx2]->oname, handler->oname);
9572#endif
9573            return -1;
9574        }
9575    }
9576    if (handler != NULL &&
9577        insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9578        printf("*** ERROR: opcode %02x already assigned in "
9579               "opcode table %02x\n", idx2, idx1);
9580#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9581        printf("           Registered handler '%s' - new handler '%s'\n",
9582               ind_table(table[idx1])[idx2]->oname, handler->oname);
9583#endif
9584        return -1;
9585    }
9586
9587    return 0;
9588}
9589
9590static int register_ind_insn(opc_handler_t **ppc_opcodes,
9591                             unsigned char idx1, unsigned char idx2,
9592                             opc_handler_t *handler)
9593{
9594    return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9595}
9596
9597static int register_dblind_insn(opc_handler_t **ppc_opcodes,
9598                                unsigned char idx1, unsigned char idx2,
9599                                unsigned char idx3, opc_handler_t *handler)
9600{
9601    if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9602        printf("*** ERROR: unable to join indirect table idx "
9603               "[%02x-%02x]\n", idx1, idx2);
9604        return -1;
9605    }
9606    if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9607                              handler) < 0) {
9608        printf("*** ERROR: unable to insert opcode "
9609               "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9610        return -1;
9611    }
9612
9613    return 0;
9614}
9615
9616static int register_trplind_insn(opc_handler_t **ppc_opcodes,
9617                                 unsigned char idx1, unsigned char idx2,
9618                                 unsigned char idx3, unsigned char idx4,
9619                                 opc_handler_t *handler)
9620{
9621    opc_handler_t **table;
9622
9623    if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9624        printf("*** ERROR: unable to join indirect table idx "
9625               "[%02x-%02x]\n", idx1, idx2);
9626        return -1;
9627    }
9628    table = ind_table(ppc_opcodes[idx1]);
9629    if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
9630        printf("*** ERROR: unable to join 2nd-level indirect table idx "
9631               "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9632        return -1;
9633    }
9634    table = ind_table(table[idx2]);
9635    if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
9636        printf("*** ERROR: unable to insert opcode "
9637               "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
9638        return -1;
9639    }
9640    return 0;
9641}
9642static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
9643{
9644    if (insn->opc2 != 0xFF) {
9645        if (insn->opc3 != 0xFF) {
9646            if (insn->opc4 != 0xFF) {
9647                if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9648                                          insn->opc3, insn->opc4,
9649                                          &insn->handler) < 0) {
9650                    return -1;
9651                }
9652            } else {
9653                if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9654                                         insn->opc3, &insn->handler) < 0) {
9655                    return -1;
9656                }
9657            }
9658        } else {
9659            if (register_ind_insn(ppc_opcodes, insn->opc1,
9660                                  insn->opc2, &insn->handler) < 0) {
9661                return -1;
9662            }
9663        }
9664    } else {
9665        if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) {
9666            return -1;
9667        }
9668    }
9669
9670    return 0;
9671}
9672
9673static int test_opcode_table(opc_handler_t **table, int len)
9674{
9675    int i, count, tmp;
9676
9677    for (i = 0, count = 0; i < len; i++) {
9678        /* Consistency fixup */
9679        if (table[i] == NULL) {
9680            table[i] = &invalid_handler;
9681        }
9682        if (table[i] != &invalid_handler) {
9683            if (is_indirect_opcode(table[i])) {
9684                tmp = test_opcode_table(ind_table(table[i]),
9685                    PPC_CPU_INDIRECT_OPCODES_LEN);
9686                if (tmp == 0) {
9687                    free(table[i]);
9688                    table[i] = &invalid_handler;
9689                } else {
9690                    count++;
9691                }
9692            } else {
9693                count++;
9694            }
9695        }
9696    }
9697
9698    return count;
9699}
9700
9701static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
9702{
9703    if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) {
9704        printf("*** WARNING: no opcode defined !\n");
9705    }
9706}
9707
9708/*****************************************************************************/
9709static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
9710{
9711    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9712    opcode_t *opc;
9713
9714    fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN);
9715    for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9716        if (((opc->handler.type & pcc->insns_flags) != 0) ||
9717            ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
9718            if (register_insn(cpu->opcodes, opc) < 0) {
9719                error_setg(errp, "ERROR initializing PowerPC instruction "
9720                           "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
9721                           opc->opc3);
9722                return;
9723            }
9724        }
9725    }
9726    fix_opcode_tables(cpu->opcodes);
9727    fflush(stdout);
9728    fflush(stderr);
9729}
9730
9731#if defined(PPC_DUMP_CPU)
9732static void dump_ppc_insns(CPUPPCState *env)
9733{
9734    opc_handler_t **table, *handler;
9735    const char *p, *q;
9736    uint8_t opc1, opc2, opc3, opc4;
9737
9738    printf("Instructions set:\n");
9739    /* opc1 is 6 bits long */
9740    for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
9741        table = env->opcodes;
9742        handler = table[opc1];
9743        if (is_indirect_opcode(handler)) {
9744            /* opc2 is 5 bits long */
9745            for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
9746                table = env->opcodes;
9747                handler = env->opcodes[opc1];
9748                table = ind_table(handler);
9749                handler = table[opc2];
9750                if (is_indirect_opcode(handler)) {
9751                    table = ind_table(handler);
9752                    /* opc3 is 5 bits long */
9753                    for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
9754                            opc3++) {
9755                        handler = table[opc3];
9756                        if (is_indirect_opcode(handler)) {
9757                            table = ind_table(handler);
9758                            /* opc4 is 5 bits long */
9759                            for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN;
9760                                 opc4++) {
9761                                handler = table[opc4];
9762                                if (handler->handler != &gen_invalid) {
9763                                    printf("INSN: %02x %02x %02x %02x -- "
9764                                           "(%02d %04d %02d) : %s\n",
9765                                           opc1, opc2, opc3, opc4,
9766                                           opc1, (opc3 << 5) | opc2, opc4,
9767                                           handler->oname);
9768                                }
9769                            }
9770                        } else {
9771                            if (handler->handler != &gen_invalid) {
9772                                /* Special hack to properly dump SPE insns */
9773                                p = strchr(handler->oname, '_');
9774                                if (p == NULL) {
9775                                    printf("INSN: %02x %02x %02x (%02d %04d) : "
9776                                           "%s\n",
9777                                           opc1, opc2, opc3, opc1,
9778                                           (opc3 << 5) | opc2,
9779                                           handler->oname);
9780                                } else {
9781                                    q = "speundef";
9782                                    if ((p - handler->oname) != strlen(q)
9783                                        || (memcmp(handler->oname, q, strlen(q))
9784                                            != 0)) {
9785                                        /* First instruction */
9786                                        printf("INSN: %02x %02x %02x"
9787                                               "(%02d %04d) : %.*s\n",
9788                                               opc1, opc2 << 1, opc3, opc1,
9789                                               (opc3 << 6) | (opc2 << 1),
9790                                               (int)(p - handler->oname),
9791                                               handler->oname);
9792                                    }
9793                                    if (strcmp(p + 1, q) != 0) {
9794                                        /* Second instruction */
9795                                        printf("INSN: %02x %02x %02x "
9796                                               "(%02d %04d) : %s\n", opc1,
9797                                               (opc2 << 1) | 1, opc3, opc1,
9798                                               (opc3 << 6) | (opc2 << 1) | 1,
9799                                               p + 1);
9800                                    }
9801                                }
9802                            }
9803                        }
9804                    }
9805                } else {
9806                    if (handler->handler != &gen_invalid) {
9807                        printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9808                               opc1, opc2, opc1, opc2, handler->oname);
9809                    }
9810                }
9811            }
9812        } else {
9813            if (handler->handler != &gen_invalid) {
9814                printf("INSN: %02x -- -- (%02d ----) : %s\n",
9815                       opc1, opc1, handler->oname);
9816            }
9817        }
9818    }
9819}
9820#endif
9821
9822static bool avr_need_swap(CPUPPCState *env)
9823{
9824#ifdef HOST_WORDS_BIGENDIAN
9825    return msr_le;
9826#else
9827    return !msr_le;
9828#endif
9829}
9830
9831#if !defined(CONFIG_USER_ONLY)
9832static int gdb_find_spr_idx(CPUPPCState *env, int n)
9833{
9834    int i;
9835
9836    for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
9837        ppc_spr_t *spr = &env->spr_cb[i];
9838
9839        if (spr->name && spr->gdb_id == n) {
9840            return i;
9841        }
9842    }
9843    return -1;
9844}
9845
9846static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n)
9847{
9848    int reg;
9849    int len;
9850
9851    reg = gdb_find_spr_idx(env, n);
9852    if (reg < 0) {
9853        return 0;
9854    }
9855
9856    len = TARGET_LONG_SIZE;
9857    gdb_get_regl(buf, env->spr[reg]);
9858    ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len);
9859    return len;
9860}
9861
9862static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9863{
9864    int reg;
9865    int len;
9866
9867    reg = gdb_find_spr_idx(env, n);
9868    if (reg < 0) {
9869        return 0;
9870    }
9871
9872    len = TARGET_LONG_SIZE;
9873    ppc_maybe_bswap_register(env, mem_buf, len);
9874    env->spr[reg] = ldn_p(mem_buf, len);
9875
9876    return len;
9877}
9878#endif
9879
9880static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n)
9881{
9882    uint8_t *mem_buf;
9883    if (n < 32) {
9884        gdb_get_reg64(buf, *cpu_fpr_ptr(env, n));
9885        mem_buf = gdb_get_reg_ptr(buf, 8);
9886        ppc_maybe_bswap_register(env, mem_buf, 8);
9887        return 8;
9888    }
9889    if (n == 32) {
9890        gdb_get_reg32(buf, env->fpscr);
9891        mem_buf = gdb_get_reg_ptr(buf, 4);
9892        ppc_maybe_bswap_register(env, mem_buf, 4);
9893        return 4;
9894    }
9895    return 0;
9896}
9897
9898static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9899{
9900    if (n < 32) {
9901        ppc_maybe_bswap_register(env, mem_buf, 8);
9902        *cpu_fpr_ptr(env, n) = ldfq_p(mem_buf);
9903        return 8;
9904    }
9905    if (n == 32) {
9906        ppc_maybe_bswap_register(env, mem_buf, 4);
9907        helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
9908        return 4;
9909    }
9910    return 0;
9911}
9912
9913static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n)
9914{
9915    uint8_t *mem_buf;
9916
9917    if (n < 32) {
9918        ppc_avr_t *avr = cpu_avr_ptr(env, n);
9919        if (!avr_need_swap(env)) {
9920            gdb_get_reg128(buf, avr->u64[0] , avr->u64[1]);
9921        } else {
9922            gdb_get_reg128(buf, avr->u64[1] , avr->u64[0]);
9923        }
9924        mem_buf = gdb_get_reg_ptr(buf, 16);
9925        ppc_maybe_bswap_register(env, mem_buf, 8);
9926        ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9927        return 16;
9928    }
9929    if (n == 32) {
9930        gdb_get_reg32(buf, helper_mfvscr(env));
9931        mem_buf = gdb_get_reg_ptr(buf, 4);
9932        ppc_maybe_bswap_register(env, mem_buf, 4);
9933        return 4;
9934    }
9935    if (n == 33) {
9936        gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]);
9937        mem_buf = gdb_get_reg_ptr(buf, 4);
9938        ppc_maybe_bswap_register(env, mem_buf, 4);
9939        return 4;
9940    }
9941    return 0;
9942}
9943
9944static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9945{
9946    if (n < 32) {
9947        ppc_avr_t *avr = cpu_avr_ptr(env, n);
9948        ppc_maybe_bswap_register(env, mem_buf, 8);
9949        ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9950        if (!avr_need_swap(env)) {
9951            avr->u64[0] = ldq_p(mem_buf);
9952            avr->u64[1] = ldq_p(mem_buf + 8);
9953        } else {
9954            avr->u64[1] = ldq_p(mem_buf);
9955            avr->u64[0] = ldq_p(mem_buf + 8);
9956        }
9957        return 16;
9958    }
9959    if (n == 32) {
9960        ppc_maybe_bswap_register(env, mem_buf, 4);
9961        helper_mtvscr(env, ldl_p(mem_buf));
9962        return 4;
9963    }
9964    if (n == 33) {
9965        ppc_maybe_bswap_register(env, mem_buf, 4);
9966        env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9967        return 4;
9968    }
9969    return 0;
9970}
9971
9972static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n)
9973{
9974    if (n < 32) {
9975#if defined(TARGET_PPC64)
9976        gdb_get_reg32(buf, env->gpr[n] >> 32);
9977        ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
9978#else
9979        gdb_get_reg32(buf, env->gprh[n]);
9980#endif
9981        return 4;
9982    }
9983    if (n == 32) {
9984        gdb_get_reg64(buf, env->spe_acc);
9985        ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
9986        return 8;
9987    }
9988    if (n == 33) {
9989        gdb_get_reg32(buf, env->spe_fscr);
9990        ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
9991        return 4;
9992    }
9993    return 0;
9994}
9995
9996static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9997{
9998    if (n < 32) {
9999#if defined(TARGET_PPC64)
10000        target_ulong lo = (uint32_t)env->gpr[n];

10001        target_ulong hi;
10002
10003        ppc_maybe_bswap_register(env, mem_buf, 4);
10004
10005        hi = (target_ulong)ldl_p(mem_buf) << 32;
10006        env->gpr[n] = lo | hi;
10007#else
10008        env->gprh[n] = ldl_p(mem_buf);
10009#endif
10010        return 4;
10011    }
10012    if (n == 32) {
10013        ppc_maybe_bswap_register(env, mem_buf, 8);
10014        env->spe_acc = ldq_p(mem_buf);
10015        return 8;
10016    }
10017    if (n == 33) {
10018        ppc_maybe_bswap_register(env, mem_buf, 4);
10019        env->spe_fscr = ldl_p(mem_buf);
10020        return 4;
10021    }
10022    return 0;
10023}
10024
10025static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n)
10026{
10027    if (n < 32) {
10028        gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n));
10029        ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
10030        return 8;
10031    }
10032    return 0;
10033}
10034
10035static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
10036{
10037    if (n < 32) {
10038        ppc_maybe_bswap_register(env, mem_buf, 8);
10039        *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf);
10040        return 8;
10041    }
10042    return 0;
10043}
10044
10045static int ppc_fixup_cpu(PowerPCCPU *cpu)
10046{
10047    CPUPPCState *env = &cpu->env;
10048
10049    /*
10050     * TCG doesn't (yet) emulate some groups of instructions that are
10051     * implemented on some otherwise supported CPUs (e.g. VSX and
10052     * decimal floating point instructions on POWER7).  We remove
10053     * unsupported instruction groups from the cpu state's instruction
10054     * masks and hope the guest can cope.  For at least the pseries
10055     * machine, the unavailability of these instructions can be
10056     * advertised to the guest via the device tree.
10057     */
10058    if ((env->insns_flags & ~PPC_TCG_INSNS)
10059        || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
10060        warn_report("Disabling some instructions which are not "
10061                    "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")",
10062                    env->insns_flags & ~PPC_TCG_INSNS,
10063                    env->insns_flags2 & ~PPC_TCG_INSNS2);
10064    }
10065    env->insns_flags &= PPC_TCG_INSNS;
10066    env->insns_flags2 &= PPC_TCG_INSNS2;
10067    return 0;
10068}
10069
10070static void ppc_cpu_realize(DeviceState *dev, Error **errp)
10071{
10072    CPUState *cs = CPU(dev);
10073    PowerPCCPU *cpu = POWERPC_CPU(dev);
10074    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10075    Error *local_err = NULL;
10076
10077    cpu_exec_realizefn(cs, &local_err);
10078    if (local_err != NULL) {
10079        error_propagate(errp, local_err);
10080        return;
10081    }
10082    if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
10083        cpu->vcpu_id = cs->cpu_index;
10084    }
10085
10086    if (tcg_enabled()) {
10087        if (ppc_fixup_cpu(cpu) != 0) {
10088            error_setg(errp, "Unable to emulate selected CPU with TCG");
10089            goto unrealize;
10090        }
10091    }
10092
10093    create_ppc_opcodes(cpu, &local_err);
10094    if (local_err != NULL) {
10095        error_propagate(errp, local_err);
10096        goto unrealize;
10097    }
10098    init_ppc_proc(cpu);
10099
10100    if (pcc->insns_flags & PPC_FLOAT) {
10101        gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
10102                                 33, "power-fpu.xml", 0);
10103    }
10104    if (pcc->insns_flags & PPC_ALTIVEC) {
10105        gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
10106                                 34, "power-altivec.xml", 0);
10107    }
10108    if (pcc->insns_flags & PPC_SPE) {
10109        gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
10110                                 34, "power-spe.xml", 0);
10111    }
10112    if (pcc->insns_flags2 & PPC2_VSX) {
10113        gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
10114                                 32, "power-vsx.xml", 0);
10115    }
10116#ifndef CONFIG_USER_ONLY
10117    gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg,
10118                             pcc->gdb_num_sprs, "power-spr.xml", 0);
10119#endif
10120    qemu_init_vcpu(cs);
10121
10122    pcc->parent_realize(dev, errp);
10123
10124#if defined(PPC_DUMP_CPU)
10125    {
10126        CPUPPCState *env = &cpu->env;
10127        const char *mmu_model, *excp_model, *bus_model;
10128        switch (env->mmu_model) {
10129        case POWERPC_MMU_32B:
10130            mmu_model = "PowerPC 32";
10131            break;
10132        case POWERPC_MMU_SOFT_6xx:
10133            mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
10134            break;
10135        case POWERPC_MMU_SOFT_74xx:
10136            mmu_model = "PowerPC 74xx with software driven TLBs";
10137            break;
10138        case POWERPC_MMU_SOFT_4xx:
10139            mmu_model = "PowerPC 4xx with software driven TLBs";
10140            break;
10141        case POWERPC_MMU_SOFT_4xx_Z:
10142            mmu_model = "PowerPC 4xx with software driven TLBs "
10143                "and zones protections";
10144            break;
10145        case POWERPC_MMU_REAL:
10146            mmu_model = "PowerPC real mode only";
10147            break;
10148        case POWERPC_MMU_MPC8xx:
10149            mmu_model = "PowerPC MPC8xx";
10150            break;
10151        case POWERPC_MMU_BOOKE:
10152            mmu_model = "PowerPC BookE";
10153            break;
10154        case POWERPC_MMU_BOOKE206:
10155            mmu_model = "PowerPC BookE 2.06";
10156            break;
10157        case POWERPC_MMU_601:
10158            mmu_model = "PowerPC 601";
10159            break;
10160#if defined(TARGET_PPC64)
10161        case POWERPC_MMU_64B:
10162            mmu_model = "PowerPC 64";
10163            break;
10164#endif
10165        default:
10166            mmu_model = "Unknown or invalid";
10167            break;
10168        }
10169        switch (env->excp_model) {
10170        case POWERPC_EXCP_STD:
10171            excp_model = "PowerPC";
10172            break;
10173        case POWERPC_EXCP_40x:
10174            excp_model = "PowerPC 40x";
10175            break;
10176        case POWERPC_EXCP_601:
10177            excp_model = "PowerPC 601";
10178            break;
10179        case POWERPC_EXCP_602:
10180            excp_model = "PowerPC 602";
10181            break;
10182        case POWERPC_EXCP_603:
10183            excp_model = "PowerPC 603";
10184            break;
10185        case POWERPC_EXCP_603E:
10186            excp_model = "PowerPC 603e";
10187            break;
10188        case POWERPC_EXCP_604:
10189            excp_model = "PowerPC 604";
10190            break;
10191        case POWERPC_EXCP_7x0:
10192            excp_model = "PowerPC 740/750";
10193            break;
10194        case POWERPC_EXCP_7x5:
10195            excp_model = "PowerPC 745/755";
10196            break;
10197        case POWERPC_EXCP_74xx:
10198            excp_model = "PowerPC 74xx";
10199            break;
10200        case POWERPC_EXCP_BOOKE:
10201            excp_model = "PowerPC BookE";
10202            break;
10203#if defined(TARGET_PPC64)
10204        case POWERPC_EXCP_970:
10205            excp_model = "PowerPC 970";
10206            break;
10207#endif
10208        default:
10209            excp_model = "Unknown or invalid";
10210            break;
10211        }
10212        switch (env->bus_model) {
10213        case PPC_FLAGS_INPUT_6xx:
10214            bus_model = "PowerPC 6xx";
10215            break;
10216        case PPC_FLAGS_INPUT_BookE:
10217            bus_model = "PowerPC BookE";
10218            break;
10219        case PPC_FLAGS_INPUT_405:
10220            bus_model = "PowerPC 405";
10221            break;
10222        case PPC_FLAGS_INPUT_401:
10223            bus_model = "PowerPC 401/403";
10224            break;
10225        case PPC_FLAGS_INPUT_RCPU:
10226            bus_model = "RCPU / MPC8xx";
10227            break;
10228#if defined(TARGET_PPC64)
10229        case PPC_FLAGS_INPUT_970:
10230            bus_model = "PowerPC 970";
10231            break;
10232#endif
10233        default:
10234            bus_model = "Unknown or invalid";
10235            break;
10236        }
10237        printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
10238               "    MMU model        : %s\n",
10239               object_class_get_name(OBJECT_CLASS(pcc)),
10240               pcc->pvr, pcc->msr_mask, mmu_model);
10241#if !defined(CONFIG_USER_ONLY)
10242        if (env->tlb.tlb6) {
10243            printf("                       %d %s TLB in %d ways\n",
10244                   env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10245                   env->nb_ways);
10246        }
10247#endif
10248        printf("    Exceptions model : %s\n"
10249               "    Bus model        : %s\n",
10250               excp_model, bus_model);
10251        printf("    MSR features     :\n");
10252        if (env->flags & POWERPC_FLAG_SPE) {
10253            printf("                        signal processing engine enable"
10254                   "\n");
10255        } else if (env->flags & POWERPC_FLAG_VRE) {
10256            printf("                        vector processor enable\n");
10257        }
10258        if (env->flags & POWERPC_FLAG_TGPR) {
10259            printf("                        temporary GPRs\n");
10260        } else if (env->flags & POWERPC_FLAG_CE) {
10261            printf("                        critical input enable\n");
10262        }
10263        if (env->flags & POWERPC_FLAG_SE) {
10264            printf("                        single-step trace mode\n");
10265        } else if (env->flags & POWERPC_FLAG_DWE) {
10266            printf("                        debug wait enable\n");
10267        } else if (env->flags & POWERPC_FLAG_UBLE) {
10268            printf("                        user BTB lock enable\n");
10269        }
10270        if (env->flags & POWERPC_FLAG_BE) {
10271            printf("                        branch-step trace mode\n");
10272        } else if (env->flags & POWERPC_FLAG_DE) {
10273            printf("                        debug interrupt enable\n");
10274        }
10275        if (env->flags & POWERPC_FLAG_PX) {
10276            printf("                        inclusive protection\n");
10277        } else if (env->flags & POWERPC_FLAG_PMM) {
10278            printf("                        performance monitor mark\n");
10279        }
10280        if (env->flags == POWERPC_FLAG_NONE) {
10281            printf("                        none\n");
10282        }
10283        printf("    Time-base/decrementer clock source: %s\n",
10284               env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
10285        dump_ppc_insns(env);
10286        dump_ppc_sprs(env);
10287        fflush(stdout);
10288    }
10289#endif
10290    return;
10291
10292unrealize:
10293    cpu_exec_unrealizefn(cs);
10294}
10295
10296static void ppc_cpu_unrealize(DeviceState *dev, Error **errp)
10297{
10298    PowerPCCPU *cpu = POWERPC_CPU(dev);
10299    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10300    Error *local_err = NULL;
10301    opc_handler_t **table, **table_2;
10302    int i, j, k;
10303
10304    pcc->parent_unrealize(dev, &local_err);
10305    if (local_err != NULL) {
10306        error_propagate(errp, local_err);
10307        return;
10308    }
10309
10310    for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
10311        if (cpu->opcodes[i] == &invalid_handler) {
10312            continue;
10313        }
10314        if (is_indirect_opcode(cpu->opcodes[i])) {
10315            table = ind_table(cpu->opcodes[i]);
10316            for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
10317                if (table[j] == &invalid_handler) {
10318                    continue;
10319                }
10320                if (is_indirect_opcode(table[j])) {
10321                    table_2 = ind_table(table[j]);
10322                    for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
10323                        if (table_2[k] != &invalid_handler &&
10324                            is_indirect_opcode(table_2[k])) {
10325                            g_free((opc_handler_t *)((uintptr_t)table_2[k] &
10326                                                     ~PPC_INDIRECT));
10327                        }
10328                    }
10329                    g_free((opc_handler_t *)((uintptr_t)table[j] &
10330                                             ~PPC_INDIRECT));
10331                }
10332            }
10333            g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] &
10334                ~PPC_INDIRECT));
10335        }
10336    }
10337}
10338
10339static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
10340{
10341    ObjectClass *oc = (ObjectClass *)a;
10342    uint32_t pvr = *(uint32_t *)b;
10343    PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
10344
10345    /* -cpu host does a PVR lookup during construction */
10346    if (unlikely(strcmp(object_class_get_name(oc),
10347                        TYPE_HOST_POWERPC_CPU) == 0)) {
10348        return -1;
10349    }
10350
10351    return pcc->pvr == pvr ? 0 : -1;
10352}
10353
10354PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
10355{
10356    GSList *list, *item;
10357    PowerPCCPUClass *pcc = NULL;
10358
10359    list = object_class_get_list(TYPE_POWERPC_CPU, false);
10360    item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
10361    if (item != NULL) {
10362        pcc = POWERPC_CPU_CLASS(item->data);
10363    }
10364    g_slist_free(list);
10365
10366    return pcc;
10367}
10368
10369static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
10370{
10371    ObjectClass *oc = (ObjectClass *)a;
10372    uint32_t pvr = *(uint32_t *)b;
10373    PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
10374
10375    /* -cpu host does a PVR lookup during construction */
10376    if (unlikely(strcmp(object_class_get_name(oc),
10377                        TYPE_HOST_POWERPC_CPU) == 0)) {
10378        return -1;
10379    }
10380
10381    if (pcc->pvr_match(pcc, pvr)) {
10382        return 0;
10383    }
10384
10385    return -1;
10386}
10387
10388PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
10389{
10390    GSList *list, *item;
10391    PowerPCCPUClass *pcc = NULL;
10392
10393    list = object_class_get_list(TYPE_POWERPC_CPU, true);
10394    item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
10395    if (item != NULL) {
10396        pcc = POWERPC_CPU_CLASS(item->data);
10397    }
10398    g_slist_free(list);
10399
10400    return pcc;
10401}
10402
10403static const char *ppc_cpu_lookup_alias(const char *alias)
10404{
10405    int ai;
10406
10407    for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
10408        if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
10409            return ppc_cpu_aliases[ai].model;
10410        }
10411    }
10412
10413    return NULL;
10414}
10415
10416static ObjectClass *ppc_cpu_class_by_name(const char *name)
10417{
10418    char *cpu_model, *typename;
10419    ObjectClass *oc;
10420    const char *p;
10421    unsigned long pvr;
10422
10423    /*
10424     * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
10425     * 0x prefix if present)
10426     */
10427    if (!qemu_strtoul(name, &p, 16, &pvr)) {
10428        int len = p - name;
10429        len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
10430        if ((len == 8) && (*p == '\0')) {
10431            return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
10432        }
10433    }
10434
10435    cpu_model = g_ascii_strdown(name, -1);
10436    p = ppc_cpu_lookup_alias(cpu_model);
10437    if (p) {
10438        g_free(cpu_model);
10439        cpu_model = g_strdup(p);
10440    }
10441
10442    typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
10443    oc = object_class_by_name(typename);
10444    g_free(typename);
10445    g_free(cpu_model);
10446
10447    return oc;
10448}
10449
10450static void ppc_cpu_parse_featurestr(const char *type, char *features,
10451                                     Error **errp)
10452{
10453    Object *machine = qdev_get_machine();
10454    const PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(object_class_by_name(type));
10455
10456    if (!features) {
10457        return;
10458    }
10459
10460    if (object_property_find(machine, "max-cpu-compat", NULL)) {
10461        int i;
10462        char **inpieces;
10463        char *s = features;
10464        Error *local_err = NULL;
10465        char *compat_str = NULL;
10466
10467        /*
10468         * Backwards compatibility hack:
10469         *
10470         *   CPUs had a "compat=" property which didn't make sense for
10471         *   anything except pseries.  It was replaced by "max-cpu-compat"
10472         *   machine option.  This supports old command lines like
10473         *       -cpu POWER8,compat=power7
10474         *   By stripping the compat option and applying it to the machine
10475         *   before passing it on to the cpu level parser.
10476         */
10477        inpieces = g_strsplit(features, ",", 0);
10478        *s = '\0';
10479        for (i = 0; inpieces[i]; i++) {
10480            if (g_str_has_prefix(inpieces[i], "compat=")) {
10481                warn_report_once("CPU 'compat' property is deprecated; "
10482                    "use max-cpu-compat machine property instead");
10483                compat_str = inpieces[i];
10484                continue;
10485            }
10486            if ((i != 0) && (s != features)) {
10487                s = g_stpcpy(s, ",");
10488            }
10489            s = g_stpcpy(s, inpieces[i]);
10490        }
10491
10492        if (compat_str) {
10493            char *v = compat_str + strlen("compat=");
10494            object_property_set_str(machine, v, "max-cpu-compat", &local_err);
10495        }
10496        g_strfreev(inpieces);
10497        if (local_err) {
10498            error_propagate(errp, local_err);
10499            return;
10500        }
10501    }
10502
10503    /* do property processing with generic handler */
10504    pcc->parent_parse_features(type, features, errp);
10505}
10506
10507PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
10508{
10509    ObjectClass *oc = OBJECT_CLASS(pcc);
10510
10511    while (oc && !object_class_is_abstract(oc)) {
10512        oc = object_class_get_parent(oc);
10513    }
10514    assert(oc);
10515
10516    return POWERPC_CPU_CLASS(oc);
10517}
10518
10519/* Sort by PVR, ordering special case "host" last. */
10520static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
10521{
10522    ObjectClass *oc_a = (ObjectClass *)a;
10523    ObjectClass *oc_b = (ObjectClass *)b;
10524    PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
10525    PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
10526    const char *name_a = object_class_get_name(oc_a);
10527    const char *name_b = object_class_get_name(oc_b);
10528
10529    if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
10530        return 1;
10531    } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
10532        return -1;
10533    } else {
10534        /* Avoid an integer overflow during subtraction */
10535        if (pcc_a->pvr < pcc_b->pvr) {
10536            return -1;
10537        } else if (pcc_a->pvr > pcc_b->pvr) {
10538            return 1;
10539        } else {
10540            return 0;
10541        }
10542    }
10543}
10544
10545static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
10546{
10547    ObjectClass *oc = data;
10548    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10549    DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
10550    const char *typename = object_class_get_name(oc);
10551    char *name;
10552    int i;
10553
10554    if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
10555        return;
10556    }
10557
10558    name = g_strndup(typename,
10559                     strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
10560    qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
10561    for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
10562        PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
10563        ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
10564
10565        if (alias_oc != oc) {
10566            continue;
10567        }
10568        /*
10569         * If running with KVM, we might update the family alias later, so
10570         * avoid printing the wrong alias here and use "preferred" instead
10571         */
10572        if (strcmp(alias->alias, family->desc) == 0) {
10573            qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
10574                        alias->alias, family->desc);
10575        } else {
10576            qemu_printf("PowerPC %-16s (alias for %s)\n",
10577                        alias->alias, name);
10578        }
10579    }
10580    g_free(name);
10581}
10582
10583void ppc_cpu_list(void)
10584{
10585    GSList *list;
10586
10587    list = object_class_get_list(TYPE_POWERPC_CPU, false);
10588    list = g_slist_sort(list, ppc_cpu_list_compare);
10589    g_slist_foreach(list, ppc_cpu_list_entry, NULL);
10590    g_slist_free(list);
10591
10592#ifdef CONFIG_KVM
10593    qemu_printf("\n");
10594    qemu_printf("PowerPC %-16s\n", "host");
10595#endif
10596}
10597
10598static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
10599{
10600    ObjectClass *oc = data;
10601    CpuDefinitionInfoList **first = user_data;
10602    const char *typename;
10603    CpuDefinitionInfoList *entry;
10604    CpuDefinitionInfo *info;
10605
10606    typename = object_class_get_name(oc);
10607    info = g_malloc0(sizeof(*info));
10608    info->name = g_strndup(typename,
10609                           strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
10610
10611    entry = g_malloc0(sizeof(*entry));
10612    entry->value = info;
10613    entry->next = *first;
10614    *first = entry;
10615}
10616
10617CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
10618{
10619    CpuDefinitionInfoList *cpu_list = NULL;
10620    GSList *list;
10621    int i;
10622
10623    list = object_class_get_list(TYPE_POWERPC_CPU, false);
10624    g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
10625    g_slist_free(list);
10626
10627    for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
10628        PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
10629        ObjectClass *oc;
10630        CpuDefinitionInfoList *entry;
10631        CpuDefinitionInfo *info;
10632
10633        oc = ppc_cpu_class_by_name(alias->model);
10634        if (oc == NULL) {
10635            continue;
10636        }
10637
10638        info = g_malloc0(sizeof(*info));
10639        info->name = g_strdup(alias->alias);
10640        info->q_typename = g_strdup(object_class_get_name(oc));
10641
10642        entry = g_malloc0(sizeof(*entry));
10643        entry->value = info;
10644        entry->next = cpu_list;
10645        cpu_list = entry;
10646    }
10647
10648    return cpu_list;
10649}
10650
10651static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
10652{
10653    PowerPCCPU *cpu = POWERPC_CPU(cs);
10654
10655    cpu->env.nip = value;
10656}
10657
10658static bool ppc_cpu_has_work(CPUState *cs)
10659{
10660    PowerPCCPU *cpu = POWERPC_CPU(cs);
10661    CPUPPCState *env = &cpu->env;
10662
10663    return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
10664}
10665
10666static void ppc_cpu_reset(DeviceState *dev)
10667{
10668    CPUState *s = CPU(dev);
10669    PowerPCCPU *cpu = POWERPC_CPU(s);
10670    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10671    CPUPPCState *env = &cpu->env;
10672    target_ulong msr;
10673    int i;
10674
10675    pcc->parent_reset(dev);
10676
10677    msr = (target_ulong)0;
10678    msr |= (target_ulong)MSR_HVB;
10679    msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
10680    msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
10681    msr |= (target_ulong)1 << MSR_EP;
10682#if defined(DO_SINGLE_STEP) && 0
10683    /* Single step trace mode */
10684    msr |= (target_ulong)1 << MSR_SE;
10685    msr |= (target_ulong)1 << MSR_BE;
10686#endif
10687#if defined(CONFIG_USER_ONLY)
10688    msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
10689    msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
10690    msr |= (target_ulong)1 << MSR_FE1;
10691    msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
10692    msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
10693    msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
10694    msr |= (target_ulong)1 << MSR_PR;
10695#if defined(TARGET_PPC64)
10696    msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
10697#endif
10698#if !defined(TARGET_WORDS_BIGENDIAN)
10699    msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
10700    if (!((env->msr_mask >> MSR_LE) & 1)) {
10701        fprintf(stderr, "Selected CPU does not support little-endian.\n");
10702        exit(1);
10703    }
10704#endif
10705#endif
10706
10707#if defined(TARGET_PPC64)
10708    if (env->mmu_model & POWERPC_MMU_64) {
10709        msr |= (1ULL << MSR_SF);
10710    }
10711#endif
10712
10713    hreg_store_msr(env, msr, 1);
10714
10715#if !defined(CONFIG_USER_ONLY)
10716    env->nip = env->hreset_vector | env->excp_prefix;
10717    if (env->mmu_model != POWERPC_MMU_REAL) {
10718        ppc_tlb_invalidate_all(env);
10719    }
10720#endif
10721
10722    hreg_compute_hflags(env);
10723    env->reserve_addr = (target_ulong)-1ULL;
10724    /* Be sure no exception or interrupt is pending */
10725    env->pending_interrupts = 0;
10726    s->exception_index = POWERPC_EXCP_NONE;
10727    env->error_code = 0;
10728    ppc_irq_reset(cpu);
10729
10730    /* tininess for underflow is detected before rounding */
10731    set_float_detect_tininess(float_tininess_before_rounding,
10732                              &env->fp_status);
10733
10734    for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
10735        ppc_spr_t *spr = &env->spr_cb[i];
10736
10737        if (!spr->name) {
10738            continue;
10739        }
10740        env->spr[i] = spr->default_value;
10741    }
10742}
10743
10744#ifndef CONFIG_USER_ONLY
10745static bool ppc_cpu_is_big_endian(CPUState *cs)
10746{
10747    PowerPCCPU *cpu = POWERPC_CPU(cs);
10748    CPUPPCState *env = &cpu->env;
10749
10750    cpu_synchronize_state(cs);
10751
10752    return !msr_le;
10753}
10754
10755static void ppc_cpu_exec_enter(CPUState *cs)
10756{
10757    PowerPCCPU *cpu = POWERPC_CPU(cs);
10758
10759    if (cpu->vhyp) {
10760        PPCVirtualHypervisorClass *vhc =
10761            PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
10762        vhc->cpu_exec_enter(cpu->vhyp, cpu);
10763    }
10764}
10765
10766static void ppc_cpu_exec_exit(CPUState *cs)
10767{
10768    PowerPCCPU *cpu = POWERPC_CPU(cs);
10769
10770    if (cpu->vhyp) {
10771        PPCVirtualHypervisorClass *vhc =
10772            PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
10773        vhc->cpu_exec_exit(cpu->vhyp, cpu);
10774    }
10775}
10776#endif
10777
10778static void ppc_cpu_instance_init(Object *obj)
10779{
10780    PowerPCCPU *cpu = POWERPC_CPU(obj);
10781    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10782    CPUPPCState *env = &cpu->env;
10783
10784    cpu_set_cpustate_pointers(cpu);
10785    cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
10786
10787    env->msr_mask = pcc->msr_mask;
10788    env->mmu_model = pcc->mmu_model;
10789    env->excp_model = pcc->excp_model;
10790    env->bus_model = pcc->bus_model;
10791    env->insns_flags = pcc->insns_flags;
10792    env->insns_flags2 = pcc->insns_flags2;
10793    env->flags = pcc->flags;
10794    env->bfd_mach = pcc->bfd_mach;
10795    env->check_pow = pcc->check_pow;
10796
10797    /*
10798     * Mark HV mode as supported if the CPU has an MSR_HV bit in the
10799     * msr_mask. The mask can later be cleared by PAPR mode but the hv
10800     * mode support will remain, thus enforcing that we cannot use
10801     * priv. instructions in guest in PAPR mode. For 970 we currently
10802     * simply don't set HV in msr_mask thus simulating an "Apple mode"
10803     * 970. If we ever want to support 970 HV mode, we'll have to add
10804     * a processor attribute of some sort.
10805     */
10806#if !defined(CONFIG_USER_ONLY)
10807    env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
10808#endif
10809
10810    ppc_hash64_init(cpu);
10811}
10812
10813static void ppc_cpu_instance_finalize(Object *obj)
10814{
10815    PowerPCCPU *cpu = POWERPC_CPU(obj);
10816
10817    ppc_hash64_finalize(cpu);
10818}
10819
10820static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
10821{
10822    return pcc->pvr == pvr;
10823}
10824
10825static gchar *ppc_gdb_arch_name(CPUState *cs)
10826{
10827#if defined(TARGET_PPC64)
10828    return g_strdup("powerpc:common64");
10829#else
10830    return g_strdup("powerpc:common");
10831#endif
10832}
10833
10834static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
10835{
10836    PowerPCCPU *cpu = POWERPC_CPU(cs);
10837    CPUPPCState *env = &cpu->env;
10838
10839    if ((env->hflags >> MSR_LE) & 1) {
10840        info->endian = BFD_ENDIAN_LITTLE;
10841    }
10842    info->mach = env->bfd_mach;
10843    if (!env->bfd_mach) {
10844#ifdef TARGET_PPC64
10845        info->mach = bfd_mach_ppc64;
10846#else
10847        info->mach = bfd_mach_ppc;
10848#endif
10849    }
10850    info->disassembler_options = (char *)"any";
10851    info->print_insn = print_insn_ppc;
10852
10853    info->cap_arch = CS_ARCH_PPC;
10854#ifdef TARGET_PPC64
10855    info->cap_mode = CS_MODE_64;
10856#endif
10857}
10858
10859static Property ppc_cpu_properties[] = {
10860    DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
10861    DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
10862                     false),
10863    DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
10864                     false),
10865    DEFINE_PROP_END_OF_LIST(),
10866};
10867
10868static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10869{
10870    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10871    CPUClass *cc = CPU_CLASS(oc);
10872    DeviceClass *dc = DEVICE_CLASS(oc);
10873
10874    device_class_set_parent_realize(dc, ppc_cpu_realize,
10875                                    &pcc->parent_realize);
10876    device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
10877                                      &pcc->parent_unrealize);
10878    pcc->pvr_match = ppc_pvr_match_default;
10879    pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
10880    device_class_set_props(dc, ppc_cpu_properties);
10881
10882    device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
10883
10884    cc->class_by_name = ppc_cpu_class_by_name;
10885    pcc->parent_parse_features = cc->parse_features;
10886    cc->parse_features = ppc_cpu_parse_featurestr;
10887    cc->has_work = ppc_cpu_has_work;
10888    cc->do_interrupt = ppc_cpu_do_interrupt;
10889    cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
10890    cc->dump_state = ppc_cpu_dump_state;
10891    cc->dump_statistics = ppc_cpu_dump_statistics;
10892    cc->set_pc = ppc_cpu_set_pc;
10893    cc->gdb_read_register = ppc_cpu_gdb_read_register;
10894    cc->gdb_write_register = ppc_cpu_gdb_write_register;
10895    cc->do_unaligned_access = ppc_cpu_do_unaligned_access;
10896#ifndef CONFIG_USER_ONLY
10897    cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
10898    cc->vmsd = &vmstate_ppc_cpu;
10899#endif
10900#if defined(CONFIG_SOFTMMU)
10901    cc->write_elf64_note = ppc64_cpu_write_elf64_note;
10902    cc->write_elf32_note = ppc32_cpu_write_elf32_note;
10903#endif
10904
10905    cc->gdb_num_core_regs = 71;
10906#ifndef CONFIG_USER_ONLY
10907    cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
10908#endif
10909#ifdef USE_APPLE_GDB
10910    cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
10911    cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
10912    cc->gdb_num_core_regs = 71 + 32;
10913#endif
10914
10915    cc->gdb_arch_name = ppc_gdb_arch_name;
10916#if defined(TARGET_PPC64)
10917    cc->gdb_core_xml_file = "power64-core.xml";
10918#else
10919    cc->gdb_core_xml_file = "power-core.xml";
10920#endif
10921#ifndef CONFIG_USER_ONLY
10922    cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
10923#endif
10924#ifdef CONFIG_TCG
10925    cc->tcg_initialize = ppc_translate_init;
10926    cc->tlb_fill = ppc_cpu_tlb_fill;
10927#endif
10928#ifndef CONFIG_USER_ONLY
10929    cc->cpu_exec_enter = ppc_cpu_exec_enter;
10930    cc->cpu_exec_exit = ppc_cpu_exec_exit;
10931#endif
10932
10933    cc->disas_set_info = ppc_disas_set_info;
10934
10935    dc->fw_name = "PowerPC,UNKNOWN";
10936}
10937
10938static const TypeInfo ppc_cpu_type_info = {
10939    .name = TYPE_POWERPC_CPU,
10940    .parent = TYPE_CPU,
10941    .instance_size = sizeof(PowerPCCPU),
10942    .instance_init = ppc_cpu_instance_init,
10943    .instance_finalize = ppc_cpu_instance_finalize,
10944    .abstract = true,
10945    .class_size = sizeof(PowerPCCPUClass),
10946    .class_init = ppc_cpu_class_init,
10947};
10948
10949static const TypeInfo ppc_vhyp_type_info = {
10950    .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
10951    .parent = TYPE_INTERFACE,
10952    .class_size = sizeof(PPCVirtualHypervisorClass),
10953};
10954
10955static void ppc_cpu_register_types(void)
10956{
10957    type_register_static(&ppc_cpu_type_info);
10958    type_register_static(&ppc_vhyp_type_info);
10959}
10960
10961type_init(ppc_cpu_register_types)
10962