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24#ifndef HW_IDE_AHCI_INTERNAL_H
25#define HW_IDE_AHCI_INTERNAL_H
26
27#include "hw/ide/ahci.h"
28#include "hw/ide/internal.h"
29#include "hw/sysbus.h"
30#include "hw/pci/pci.h"
31
32#define AHCI_MEM_BAR_SIZE 0x1000
33#define AHCI_MAX_PORTS 32
34#define AHCI_MAX_SG 168
35#define AHCI_DMA_BOUNDARY 0xffffffff
36#define AHCI_USE_CLUSTERING 0
37#define AHCI_MAX_CMDS 32
38#define AHCI_CMD_SZ 32
39#define AHCI_CMD_SLOT_SZ (AHCI_MAX_CMDS * AHCI_CMD_SZ)
40#define AHCI_RX_FIS_SZ 256
41#define AHCI_CMD_TBL_CDB 0x40
42#define AHCI_CMD_TBL_HDR_SZ 0x80
43#define AHCI_CMD_TBL_SZ (AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16))
44#define AHCI_CMD_TBL_AR_SZ (AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS)
45#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + \
46 AHCI_RX_FIS_SZ)
47
48#define AHCI_IRQ_ON_SG (1U << 31)
49#define AHCI_CMD_ATAPI (1 << 5)
50#define AHCI_CMD_WRITE (1 << 6)
51#define AHCI_CMD_PREFETCH (1 << 7)
52#define AHCI_CMD_RESET (1 << 8)
53#define AHCI_CMD_CLR_BUSY (1 << 10)
54
55#define RX_FIS_D2H_REG 0x40
56#define RX_FIS_SDB 0x58
57#define RX_FIS_UNK 0x60
58
59
60enum AHCIHostReg {
61 AHCI_HOST_REG_CAP = 0,
62 AHCI_HOST_REG_CTL = 1,
63 AHCI_HOST_REG_IRQ_STAT = 2,
64 AHCI_HOST_REG_PORTS_IMPL = 3,
65 AHCI_HOST_REG_VERSION = 4,
66 AHCI_HOST_REG_CCC_CTL = 5,
67 AHCI_HOST_REG_CCC_PORTS = 6,
68 AHCI_HOST_REG_EM_LOC = 7,
69 AHCI_HOST_REG_EM_CTL = 8,
70 AHCI_HOST_REG_CAP2 = 9,
71 AHCI_HOST_REG_BOHC = 10,
72 AHCI_HOST_REG__COUNT = 11
73};
74
75
76#define HOST_CTL_RESET (1 << 0)
77#define HOST_CTL_IRQ_EN (1 << 1)
78#define HOST_CTL_AHCI_EN (1U << 31)
79
80
81#define HOST_CAP_SSC (1 << 14)
82#define HOST_CAP_AHCI (1 << 18)
83#define HOST_CAP_CLO (1 << 24)
84#define HOST_CAP_SSS (1 << 27)
85#define HOST_CAP_NCQ (1 << 30)
86#define HOST_CAP_64 (1U << 31)
87
88
89enum AHCIPortReg {
90 AHCI_PORT_REG_LST_ADDR = 0,
91 AHCI_PORT_REG_LST_ADDR_HI = 1,
92 AHCI_PORT_REG_FIS_ADDR = 2,
93 AHCI_PORT_REG_FIS_ADDR_HI = 3,
94 AHCI_PORT_REG_IRQ_STAT = 4,
95 AHCI_PORT_REG_IRQ_MASK = 5,
96 AHCI_PORT_REG_CMD = 6,
97
98 AHCI_PORT_REG_TFDATA = 8,
99 AHCI_PORT_REG_SIG = 9,
100 AHCI_PORT_REG_SCR_STAT = 10,
101 AHCI_PORT_REG_SCR_CTL = 11,
102 AHCI_PORT_REG_SCR_ERR = 12,
103 AHCI_PORT_REG_SCR_ACT = 13,
104 AHCI_PORT_REG_CMD_ISSUE = 14,
105 AHCI_PORT_REG_SCR_NOTIF = 15,
106 AHCI_PORT_REG_FIS_CTL = 16,
107 AHCI_PORT_REG_DEV_SLEEP = 17,
108
109 AHCI_PORT_REG_VENDOR_1 = 28,
110 AHCI_PORT_REG_VENDOR_2 = 29,
111 AHCI_PORT_REG_VENDOR_3 = 30,
112 AHCI_PORT_REG_VENDOR_4 = 31,
113 AHCI_PORT_REG__COUNT = 32
114};
115
116
117enum AHCIPortIRQ {
118 AHCI_PORT_IRQ_BIT_DHRS = 0,
119 AHCI_PORT_IRQ_BIT_PSS = 1,
120 AHCI_PORT_IRQ_BIT_DSS = 2,
121 AHCI_PORT_IRQ_BIT_SDBS = 3,
122 AHCI_PORT_IRQ_BIT_UFS = 4,
123 AHCI_PORT_IRQ_BIT_DPS = 5,
124 AHCI_PORT_IRQ_BIT_PCS = 6,
125 AHCI_PORT_IRQ_BIT_DMPS = 7,
126
127 AHCI_PORT_IRQ_BIT_PRCS = 22,
128 AHCI_PORT_IRQ_BIT_IPMS = 23,
129 AHCI_PORT_IRQ_BIT_OFS = 24,
130
131 AHCI_PORT_IRQ_BIT_INFS = 26,
132 AHCI_PORT_IRQ_BIT_IFS = 27,
133 AHCI_PORT_IRQ_BIT_HBDS = 28,
134 AHCI_PORT_IRQ_BIT_HBFS = 29,
135 AHCI_PORT_IRQ_BIT_TFES = 30,
136 AHCI_PORT_IRQ_BIT_CPDS = 31,
137 AHCI_PORT_IRQ__COUNT = 32
138};
139
140
141
142#define PORT_IRQ_COLD_PRES (1U << 31)
143#define PORT_IRQ_TF_ERR (1 << 30)
144#define PORT_IRQ_HBUS_ERR (1 << 29)
145#define PORT_IRQ_HBUS_DATA_ERR (1 << 28)
146#define PORT_IRQ_IF_ERR (1 << 27)
147#define PORT_IRQ_IF_NONFATAL (1 << 26)
148
149#define PORT_IRQ_OVERFLOW (1 << 24)
150#define PORT_IRQ_BAD_PMP (1 << 23)
151#define PORT_IRQ_PHYRDY (1 << 22)
152
153#define PORT_IRQ_DEV_ILCK (1 << 7)
154#define PORT_IRQ_CONNECT (1 << 6)
155#define PORT_IRQ_SG_DONE (1 << 5)
156#define PORT_IRQ_UNK_FIS (1 << 4)
157#define PORT_IRQ_SDB_FIS (1 << 3)
158#define PORT_IRQ_DMAS_FIS (1 << 2)
159#define PORT_IRQ_PIOS_FIS (1 << 1)
160#define PORT_IRQ_D2H_REG_FIS (1 << 0)
161
162#define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \
163 PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \
164 PORT_IRQ_UNK_FIS)
165#define PORT_IRQ_ERROR (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR | \
166 PORT_IRQ_HBUS_DATA_ERR)
167#define DEF_PORT_IRQ (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | \
168 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | \
169 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS)
170
171
172#define PORT_CMD_ATAPI (1 << 24)
173#define PORT_CMD_LIST_ON (1 << 15)
174#define PORT_CMD_FIS_ON (1 << 14)
175#define PORT_CMD_FIS_RX (1 << 4)
176#define PORT_CMD_CLO (1 << 3)
177#define PORT_CMD_POWER_ON (1 << 2)
178#define PORT_CMD_SPIN_UP (1 << 1)
179#define PORT_CMD_START (1 << 0)
180
181#define PORT_CMD_ICC_MASK (0xfU << 28)
182#define PORT_CMD_ICC_ACTIVE (0x1 << 28)
183#define PORT_CMD_ICC_PARTIAL (0x2 << 28)
184#define PORT_CMD_ICC_SLUMBER (0x6 << 28)
185
186#define PORT_CMD_RO_MASK 0x007dffe0
187
188
189#define AHCI_FLAG_NO_NCQ (1 << 24)
190#define AHCI_FLAG_IGN_IRQ_IF_ERR (1 << 25)
191#define AHCI_FLAG_HONOR_PI (1 << 26)
192#define AHCI_FLAG_IGN_SERR_INTERNAL (1 << 27)
193#define AHCI_FLAG_32BIT_ONLY (1 << 28)
194
195#define ATA_SRST (1 << 2)
196
197#define STATE_RUN 0
198#define STATE_RESET 1
199
200#define SATA_SCR_SSTATUS_DET_NODEV 0x0
201#define SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP 0x3
202
203#define SATA_SCR_SSTATUS_SPD_NODEV 0x00
204#define SATA_SCR_SSTATUS_SPD_GEN1 0x10
205
206#define SATA_SCR_SSTATUS_IPM_NODEV 0x000
207#define SATA_SCR_SSTATUS_IPM_ACTIVE 0X100
208
209#define AHCI_SCR_SCTL_DET 0xf
210
211#define SATA_FIS_TYPE_REGISTER_H2D 0x27
212#define SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER 0x80
213#define SATA_FIS_TYPE_REGISTER_D2H 0x34
214#define SATA_FIS_TYPE_PIO_SETUP 0x5f
215#define SATA_FIS_TYPE_SDB 0xA1
216
217#define AHCI_CMD_HDR_CMD_FIS_LEN 0x1f
218#define AHCI_CMD_HDR_PRDT_LEN 16
219
220#define SATA_SIGNATURE_CDROM 0xeb140101
221#define SATA_SIGNATURE_DISK 0x00000101
222
223#define AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR 0x2c
224
225#define AHCI_PORT_REGS_START_ADDR 0x100
226#define AHCI_PORT_ADDR_OFFSET_MASK 0x7f
227#define AHCI_PORT_ADDR_OFFSET_LEN 0x80
228
229#define AHCI_NUM_COMMAND_SLOTS 31
230#define AHCI_SUPPORTED_SPEED 20
231#define AHCI_SUPPORTED_SPEED_GEN1 1
232#define AHCI_VERSION_1_0 0x10000
233
234#define AHCI_PROGMODE_MAJOR_REV_1 1
235
236#define AHCI_COMMAND_TABLE_ACMD 0x40
237
238#define AHCI_PRDT_SIZE_MASK 0x3fffff
239
240#define IDE_FEATURE_DMA 1
241
242#define READ_FPDMA_QUEUED 0x60
243#define WRITE_FPDMA_QUEUED 0x61
244#define NCQ_NON_DATA 0x63
245#define RECEIVE_FPDMA_QUEUED 0x65
246#define SEND_FPDMA_QUEUED 0x64
247
248#define NCQ_FIS_FUA_MASK 0x80
249#define NCQ_FIS_RARC_MASK 0x01
250
251#define RES_FIS_DSFIS 0x00
252#define RES_FIS_PSFIS 0x20
253#define RES_FIS_RFIS 0x40
254#define RES_FIS_SDBFIS 0x58
255#define RES_FIS_UFIS 0x60
256
257#define SATA_CAP_SIZE 0x8
258#define SATA_CAP_REV 0x2
259#define SATA_CAP_BAR 0x4
260
261typedef struct AHCIPortRegs {
262 uint32_t lst_addr;
263 uint32_t lst_addr_hi;
264 uint32_t fis_addr;
265 uint32_t fis_addr_hi;
266 uint32_t irq_stat;
267 uint32_t irq_mask;
268 uint32_t cmd;
269 uint32_t unused0;
270 uint32_t tfdata;
271 uint32_t sig;
272 uint32_t scr_stat;
273 uint32_t scr_ctl;
274 uint32_t scr_err;
275 uint32_t scr_act;
276 uint32_t cmd_issue;
277 uint32_t reserved;
278} AHCIPortRegs;
279
280typedef struct AHCICmdHdr {
281 uint16_t opts;
282 uint16_t prdtl;
283 uint32_t status;
284 uint64_t tbl_addr;
285 uint32_t reserved[4];
286} QEMU_PACKED AHCICmdHdr;
287
288typedef struct AHCI_SG {
289 uint64_t addr;
290 uint32_t reserved;
291 uint32_t flags_size;
292} QEMU_PACKED AHCI_SG;
293
294typedef struct NCQTransferState {
295 AHCIDevice *drive;
296 BlockAIOCB *aiocb;
297 AHCICmdHdr *cmdh;
298 QEMUSGList sglist;
299 BlockAcctCookie acct;
300 uint32_t sector_count;
301 uint64_t lba;
302 uint8_t tag;
303 uint8_t cmd;
304 uint8_t slot;
305 bool used;
306 bool halt;
307} NCQTransferState;
308
309struct AHCIDevice {
310 IDEDMA dma;
311 IDEBus port;
312 int port_no;
313 uint32_t port_state;
314 uint32_t finished;
315 AHCIPortRegs port_regs;
316 struct AHCIState *hba;
317 QEMUBH *check_bh;
318 uint8_t *lst;
319 uint8_t *res_fis;
320 bool done_first_drq;
321 int32_t busy_slot;
322 bool init_d2h_sent;
323 AHCICmdHdr *cur_cmd;
324 NCQTransferState ncq_tfs[AHCI_MAX_CMDS];
325};
326
327struct AHCIPCIState {
328
329 PCIDevice parent_obj;
330
331
332 AHCIState ahci;
333};
334
335#define ICH_AHCI(obj) \
336 OBJECT_CHECK(AHCIPCIState, (obj), TYPE_ICH9_AHCI)
337
338extern const VMStateDescription vmstate_ahci;
339
340#define VMSTATE_AHCI(_field, _state) { \
341 .name = (stringify(_field)), \
342 .size = sizeof(AHCIState), \
343 .vmsd = &vmstate_ahci, \
344 .flags = VMS_STRUCT, \
345 .offset = vmstate_offset_value(_state, _field, AHCIState), \
346}
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359
360typedef struct NCQFrame {
361 uint8_t fis_type;
362 uint8_t c;
363 uint8_t command;
364 uint8_t sector_count_low;
365 uint8_t lba0;
366 uint8_t lba1;
367 uint8_t lba2;
368 uint8_t fua;
369 uint8_t lba3;
370 uint8_t lba4;
371 uint8_t lba5;
372 uint8_t sector_count_high;
373 uint8_t tag;
374 uint8_t prio;
375 uint8_t icc;
376 uint8_t control;
377 uint8_t aux0;
378 uint8_t aux1;
379 uint8_t aux2;
380 uint8_t aux3;
381} QEMU_PACKED NCQFrame;
382
383typedef struct SDBFIS {
384 uint8_t type;
385 uint8_t flags;
386 uint8_t status;
387 uint8_t error;
388 uint32_t payload;
389} QEMU_PACKED SDBFIS;
390
391void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports);
392void ahci_init(AHCIState *s, DeviceState *qdev);
393void ahci_uninit(AHCIState *s);
394
395void ahci_reset(AHCIState *s);
396
397#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
398
399#endif
400