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34#include "qemu/osdep.h"
35#include "hw/irq.h"
36#include "hw/net/mii.h"
37#include "hw/qdev-properties.h"
38#include "hw/sysbus.h"
39#include "net/net.h"
40#include "qemu/module.h"
41#include "net/eth.h"
42#include "trace.h"
43
44
45
46
47#undef USE_RECSMALL
48
49#define GET_FIELD(v, field) (((v) & (field)) >> (field ## _LBN))
50#define GET_REGBIT(s, reg, field) ((s)->regs[reg] & (reg ## _ ## field))
51#define GET_REGFIELD(s, reg, field) \
52 GET_FIELD((s)->regs[reg], reg ## _ ## field)
53
54#define SET_FIELD(v, field, data) \
55 ((v) = (((v) & ~(field)) | (((data) << (field ## _LBN)) & (field))))
56#define SET_REGFIELD(s, reg, field, data) \
57 SET_FIELD((s)->regs[reg], reg ## _ ## field, data)
58
59
60enum {
61 MII_REG_MAX = 16,
62};
63
64typedef struct Mii {
65 uint16_t regs[MII_REG_MAX];
66 bool link_ok;
67} Mii;
68
69static void mii_set_link(Mii *s, bool link_ok)
70{
71 if (link_ok) {
72 s->regs[MII_BMSR] |= MII_BMSR_LINK_ST;
73 s->regs[MII_ANLPAR] |= MII_ANLPAR_TXFD | MII_ANLPAR_TX |
74 MII_ANLPAR_10FD | MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
75 } else {
76 s->regs[MII_BMSR] &= ~MII_BMSR_LINK_ST;
77 s->regs[MII_ANLPAR] &= 0x01ff;
78 }
79 s->link_ok = link_ok;
80}
81
82static void mii_reset(Mii *s)
83{
84 memset(s->regs, 0, sizeof(s->regs));
85 s->regs[MII_BMCR] = MII_BMCR_AUTOEN;
86 s->regs[MII_BMSR] = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD |
87 MII_BMSR_10T_FD | MII_BMSR_10T_HD | MII_BMSR_MFPS |
88 MII_BMSR_AN_COMP | MII_BMSR_AUTONEG;
89 s->regs[MII_PHYID1] = 0x2000;
90 s->regs[MII_PHYID2] = 0x5c90;
91 s->regs[MII_ANAR] = MII_ANAR_TXFD | MII_ANAR_TX |
92 MII_ANAR_10FD | MII_ANAR_10 | MII_ANAR_CSMACD;
93 mii_set_link(s, s->link_ok);
94}
95
96static void mii_ro(Mii *s, uint16_t v)
97{
98}
99
100static void mii_write_bmcr(Mii *s, uint16_t v)
101{
102 if (v & MII_BMCR_RESET) {
103 mii_reset(s);
104 } else {
105 s->regs[MII_BMCR] = v;
106 }
107}
108
109static void mii_write_host(Mii *s, unsigned idx, uint16_t v)
110{
111 static void (*reg_write[MII_REG_MAX])(Mii *s, uint16_t v) = {
112 [MII_BMCR] = mii_write_bmcr,
113 [MII_BMSR] = mii_ro,
114 [MII_PHYID1] = mii_ro,
115 [MII_PHYID2] = mii_ro,
116 };
117
118 if (idx < MII_REG_MAX) {
119 trace_open_eth_mii_write(idx, v);
120 if (reg_write[idx]) {
121 reg_write[idx](s, v);
122 } else {
123 s->regs[idx] = v;
124 }
125 }
126}
127
128static uint16_t mii_read_host(Mii *s, unsigned idx)
129{
130 trace_open_eth_mii_read(idx, s->regs[idx]);
131 return s->regs[idx];
132}
133
134
135enum {
136 MODER,
137 INT_SOURCE,
138 INT_MASK,
139 IPGT,
140 IPGR1,
141 IPGR2,
142 PACKETLEN,
143 COLLCONF,
144 TX_BD_NUM,
145 CTRLMODER,
146 MIIMODER,
147 MIICOMMAND,
148 MIIADDRESS,
149 MIITX_DATA,
150 MIIRX_DATA,
151 MIISTATUS,
152 MAC_ADDR0,
153 MAC_ADDR1,
154 HASH0,
155 HASH1,
156 TXCTRL,
157 REG_MAX,
158};
159
160enum {
161 MODER_RECSMALL = 0x10000,
162 MODER_PAD = 0x8000,
163 MODER_HUGEN = 0x4000,
164 MODER_RST = 0x800,
165 MODER_LOOPBCK = 0x80,
166 MODER_PRO = 0x20,
167 MODER_IAM = 0x10,
168 MODER_BRO = 0x8,
169 MODER_TXEN = 0x2,
170 MODER_RXEN = 0x1,
171};
172
173enum {
174 INT_SOURCE_BUSY = 0x10,
175 INT_SOURCE_RXB = 0x4,
176 INT_SOURCE_TXB = 0x1,
177};
178
179enum {
180 PACKETLEN_MINFL = 0xffff0000,
181 PACKETLEN_MINFL_LBN = 16,
182 PACKETLEN_MAXFL = 0xffff,
183 PACKETLEN_MAXFL_LBN = 0,
184};
185
186enum {
187 MIICOMMAND_WCTRLDATA = 0x4,
188 MIICOMMAND_RSTAT = 0x2,
189 MIICOMMAND_SCANSTAT = 0x1,
190};
191
192enum {
193 MIIADDRESS_RGAD = 0x1f00,
194 MIIADDRESS_RGAD_LBN = 8,
195 MIIADDRESS_FIAD = 0x1f,
196 MIIADDRESS_FIAD_LBN = 0,
197};
198
199enum {
200 MIITX_DATA_CTRLDATA = 0xffff,
201 MIITX_DATA_CTRLDATA_LBN = 0,
202};
203
204enum {
205 MIIRX_DATA_PRSD = 0xffff,
206 MIIRX_DATA_PRSD_LBN = 0,
207};
208
209enum {
210 MIISTATUS_LINKFAIL = 0x1,
211 MIISTATUS_LINKFAIL_LBN = 0,
212};
213
214enum {
215 MAC_ADDR0_BYTE2 = 0xff000000,
216 MAC_ADDR0_BYTE2_LBN = 24,
217 MAC_ADDR0_BYTE3 = 0xff0000,
218 MAC_ADDR0_BYTE3_LBN = 16,
219 MAC_ADDR0_BYTE4 = 0xff00,
220 MAC_ADDR0_BYTE4_LBN = 8,
221 MAC_ADDR0_BYTE5 = 0xff,
222 MAC_ADDR0_BYTE5_LBN = 0,
223};
224
225enum {
226 MAC_ADDR1_BYTE0 = 0xff00,
227 MAC_ADDR1_BYTE0_LBN = 8,
228 MAC_ADDR1_BYTE1 = 0xff,
229 MAC_ADDR1_BYTE1_LBN = 0,
230};
231
232enum {
233 TXD_LEN = 0xffff0000,
234 TXD_LEN_LBN = 16,
235 TXD_RD = 0x8000,
236 TXD_IRQ = 0x4000,
237 TXD_WR = 0x2000,
238 TXD_PAD = 0x1000,
239 TXD_CRC = 0x800,
240 TXD_UR = 0x100,
241 TXD_RTRY = 0xf0,
242 TXD_RTRY_LBN = 4,
243 TXD_RL = 0x8,
244 TXD_LC = 0x4,
245 TXD_DF = 0x2,
246 TXD_CS = 0x1,
247};
248
249enum {
250 RXD_LEN = 0xffff0000,
251 RXD_LEN_LBN = 16,
252 RXD_E = 0x8000,
253 RXD_IRQ = 0x4000,
254 RXD_WRAP = 0x2000,
255 RXD_CF = 0x100,
256 RXD_M = 0x80,
257 RXD_OR = 0x40,
258 RXD_IS = 0x20,
259 RXD_DN = 0x10,
260 RXD_TL = 0x8,
261 RXD_SF = 0x4,
262 RXD_CRC = 0x2,
263 RXD_LC = 0x1,
264};
265
266typedef struct desc {
267 uint32_t len_flags;
268 uint32_t buf_ptr;
269} desc;
270
271#define DEFAULT_PHY 1
272
273#define TYPE_OPEN_ETH "open_eth"
274#define OPEN_ETH(obj) OBJECT_CHECK(OpenEthState, (obj), TYPE_OPEN_ETH)
275
276typedef struct OpenEthState {
277 SysBusDevice parent_obj;
278
279 NICState *nic;
280 NICConf conf;
281 MemoryRegion reg_io;
282 MemoryRegion desc_io;
283 qemu_irq irq;
284
285 Mii mii;
286 uint32_t regs[REG_MAX];
287 unsigned tx_desc;
288 unsigned rx_desc;
289 desc desc[128];
290} OpenEthState;
291
292static desc *rx_desc(OpenEthState *s)
293{
294 return s->desc + s->rx_desc;
295}
296
297static desc *tx_desc(OpenEthState *s)
298{
299 return s->desc + s->tx_desc;
300}
301
302static void open_eth_update_irq(OpenEthState *s,
303 uint32_t old, uint32_t new)
304{
305 if (!old != !new) {
306 trace_open_eth_update_irq(new);
307 qemu_set_irq(s->irq, new);
308 }
309}
310
311static void open_eth_int_source_write(OpenEthState *s,
312 uint32_t val)
313{
314 uint32_t old_val = s->regs[INT_SOURCE];
315
316 s->regs[INT_SOURCE] = val;
317 open_eth_update_irq(s, old_val & s->regs[INT_MASK],
318 s->regs[INT_SOURCE] & s->regs[INT_MASK]);
319}
320
321static void open_eth_set_link_status(NetClientState *nc)
322{
323 OpenEthState *s = qemu_get_nic_opaque(nc);
324
325 if (GET_REGBIT(s, MIICOMMAND, SCANSTAT)) {
326 SET_REGFIELD(s, MIISTATUS, LINKFAIL, nc->link_down);
327 }
328 mii_set_link(&s->mii, !nc->link_down);
329}
330
331static void open_eth_reset(void *opaque)
332{
333 OpenEthState *s = opaque;
334
335 memset(s->regs, 0, sizeof(s->regs));
336 s->regs[MODER] = 0xa000;
337 s->regs[IPGT] = 0x12;
338 s->regs[IPGR1] = 0xc;
339 s->regs[IPGR2] = 0x12;
340 s->regs[PACKETLEN] = 0x400600;
341 s->regs[COLLCONF] = 0xf003f;
342 s->regs[TX_BD_NUM] = 0x40;
343 s->regs[MIIMODER] = 0x64;
344
345 s->tx_desc = 0;
346 s->rx_desc = 0x40;
347
348 mii_reset(&s->mii);
349 open_eth_set_link_status(qemu_get_queue(s->nic));
350}
351
352static bool open_eth_can_receive(NetClientState *nc)
353{
354 OpenEthState *s = qemu_get_nic_opaque(nc);
355
356 return GET_REGBIT(s, MODER, RXEN) && (s->regs[TX_BD_NUM] < 0x80);
357}
358
359static ssize_t open_eth_receive(NetClientState *nc,
360 const uint8_t *buf, size_t size)
361{
362 OpenEthState *s = qemu_get_nic_opaque(nc);
363 size_t maxfl = GET_REGFIELD(s, PACKETLEN, MAXFL);
364 size_t minfl = GET_REGFIELD(s, PACKETLEN, MINFL);
365 size_t fcsl = 4;
366 bool miss = true;
367
368 trace_open_eth_receive((unsigned)size);
369
370 if (size >= 6) {
371 static const uint8_t bcast_addr[] = {
372 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
373 };
374 if (memcmp(buf, bcast_addr, sizeof(bcast_addr)) == 0) {
375 miss = GET_REGBIT(s, MODER, BRO);
376 } else if ((buf[0] & 0x1) || GET_REGBIT(s, MODER, IAM)) {
377 unsigned mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
378 miss = !(s->regs[HASH0 + mcast_idx / 32] &
379 (1 << (mcast_idx % 32)));
380 trace_open_eth_receive_mcast(
381 mcast_idx, s->regs[HASH0], s->regs[HASH1]);
382 } else {
383 miss = GET_REGFIELD(s, MAC_ADDR1, BYTE0) != buf[0] ||
384 GET_REGFIELD(s, MAC_ADDR1, BYTE1) != buf[1] ||
385 GET_REGFIELD(s, MAC_ADDR0, BYTE2) != buf[2] ||
386 GET_REGFIELD(s, MAC_ADDR0, BYTE3) != buf[3] ||
387 GET_REGFIELD(s, MAC_ADDR0, BYTE4) != buf[4] ||
388 GET_REGFIELD(s, MAC_ADDR0, BYTE5) != buf[5];
389 }
390 }
391
392 if (miss && !GET_REGBIT(s, MODER, PRO)) {
393 trace_open_eth_receive_reject();
394 return size;
395 }
396
397#ifdef USE_RECSMALL
398 if (GET_REGBIT(s, MODER, RECSMALL) || size >= minfl) {
399#else
400 {
401#endif
402 static const uint8_t zero[64] = {0};
403 desc *desc = rx_desc(s);
404 size_t copy_size = GET_REGBIT(s, MODER, HUGEN) ? 65536 : maxfl;
405
406 if (!(desc->len_flags & RXD_E)) {
407 open_eth_int_source_write(s,
408 s->regs[INT_SOURCE] | INT_SOURCE_BUSY);
409 return size;
410 }
411
412 desc->len_flags &= ~(RXD_CF | RXD_M | RXD_OR |
413 RXD_IS | RXD_DN | RXD_TL | RXD_SF | RXD_CRC | RXD_LC);
414
415 if (copy_size > size) {
416 copy_size = size;
417 } else {
418 fcsl = 0;
419 }
420 if (miss) {
421 desc->len_flags |= RXD_M;
422 }
423 if (GET_REGBIT(s, MODER, HUGEN) && size > maxfl) {
424 desc->len_flags |= RXD_TL;
425 }
426#ifdef USE_RECSMALL
427 if (size < minfl) {
428 desc->len_flags |= RXD_SF;
429 }
430#endif
431
432 cpu_physical_memory_write(desc->buf_ptr, buf, copy_size);
433
434 if (GET_REGBIT(s, MODER, PAD) && copy_size < minfl) {
435 if (minfl - copy_size > fcsl) {
436 fcsl = 0;
437 } else {
438 fcsl -= minfl - copy_size;
439 }
440 while (copy_size < minfl) {
441 size_t zero_sz = minfl - copy_size < sizeof(zero) ?
442 minfl - copy_size : sizeof(zero);
443
444 cpu_physical_memory_write(desc->buf_ptr + copy_size,
445 zero, zero_sz);
446 copy_size += zero_sz;
447 }
448 }
449
450
451
452
453
454 cpu_physical_memory_write(desc->buf_ptr + copy_size, zero, fcsl);
455 copy_size += fcsl;
456
457 SET_FIELD(desc->len_flags, RXD_LEN, copy_size);
458
459 if ((desc->len_flags & RXD_WRAP) || s->rx_desc == 0x7f) {
460 s->rx_desc = s->regs[TX_BD_NUM];
461 } else {
462 ++s->rx_desc;
463 }
464 desc->len_flags &= ~RXD_E;
465
466 trace_open_eth_receive_desc(desc->buf_ptr, desc->len_flags);
467
468 if (desc->len_flags & RXD_IRQ) {
469 open_eth_int_source_write(s,
470 s->regs[INT_SOURCE] | INT_SOURCE_RXB);
471 }
472 }
473 return size;
474}
475
476static NetClientInfo net_open_eth_info = {
477 .type = NET_CLIENT_DRIVER_NIC,
478 .size = sizeof(NICState),
479 .can_receive = open_eth_can_receive,
480 .receive = open_eth_receive,
481 .link_status_changed = open_eth_set_link_status,
482};
483
484static void open_eth_start_xmit(OpenEthState *s, desc *tx)
485{
486 uint8_t *buf = NULL;
487 uint8_t buffer[0x600];
488 unsigned len = GET_FIELD(tx->len_flags, TXD_LEN);
489 unsigned tx_len = len;
490
491 if ((tx->len_flags & TXD_PAD) &&
492 tx_len < GET_REGFIELD(s, PACKETLEN, MINFL)) {
493 tx_len = GET_REGFIELD(s, PACKETLEN, MINFL);
494 }
495 if (!GET_REGBIT(s, MODER, HUGEN) &&
496 tx_len > GET_REGFIELD(s, PACKETLEN, MAXFL)) {
497 tx_len = GET_REGFIELD(s, PACKETLEN, MAXFL);
498 }
499
500 trace_open_eth_start_xmit(tx->buf_ptr, len, tx_len);
501
502 if (tx_len > sizeof(buffer)) {
503 buf = g_new(uint8_t, tx_len);
504 } else {
505 buf = buffer;
506 }
507 if (len > tx_len) {
508 len = tx_len;
509 }
510 cpu_physical_memory_read(tx->buf_ptr, buf, len);
511 if (tx_len > len) {
512 memset(buf + len, 0, tx_len - len);
513 }
514 qemu_send_packet(qemu_get_queue(s->nic), buf, tx_len);
515 if (tx_len > sizeof(buffer)) {
516 g_free(buf);
517 }
518
519 if (tx->len_flags & TXD_WR) {
520 s->tx_desc = 0;
521 } else {
522 ++s->tx_desc;
523 if (s->tx_desc >= s->regs[TX_BD_NUM]) {
524 s->tx_desc = 0;
525 }
526 }
527 tx->len_flags &= ~(TXD_RD | TXD_UR |
528 TXD_RTRY | TXD_RL | TXD_LC | TXD_DF | TXD_CS);
529 if (tx->len_flags & TXD_IRQ) {
530 open_eth_int_source_write(s, s->regs[INT_SOURCE] | INT_SOURCE_TXB);
531 }
532
533}
534
535static void open_eth_check_start_xmit(OpenEthState *s)
536{
537 desc *tx = tx_desc(s);
538 if (GET_REGBIT(s, MODER, TXEN) && s->regs[TX_BD_NUM] > 0 &&
539 (tx->len_flags & TXD_RD) &&
540 GET_FIELD(tx->len_flags, TXD_LEN) > 4) {
541 open_eth_start_xmit(s, tx);
542 }
543}
544
545static uint64_t open_eth_reg_read(void *opaque,
546 hwaddr addr, unsigned int size)
547{
548 static uint32_t (*reg_read[REG_MAX])(OpenEthState *s) = {
549 };
550 OpenEthState *s = opaque;
551 unsigned idx = addr / 4;
552 uint64_t v = 0;
553
554 if (idx < REG_MAX) {
555 if (reg_read[idx]) {
556 v = reg_read[idx](s);
557 } else {
558 v = s->regs[idx];
559 }
560 }
561 trace_open_eth_reg_read((uint32_t)addr, (uint32_t)v);
562 return v;
563}
564
565static void open_eth_notify_can_receive(OpenEthState *s)
566{
567 NetClientState *nc = qemu_get_queue(s->nic);
568
569 if (open_eth_can_receive(nc)) {
570 qemu_flush_queued_packets(nc);
571 }
572}
573
574static void open_eth_ro(OpenEthState *s, uint32_t val)
575{
576}
577
578static void open_eth_moder_host_write(OpenEthState *s, uint32_t val)
579{
580 uint32_t set = val & ~s->regs[MODER];
581
582 if (set & MODER_RST) {
583 open_eth_reset(s);
584 }
585
586 s->regs[MODER] = val;
587
588 if (set & MODER_RXEN) {
589 s->rx_desc = s->regs[TX_BD_NUM];
590 open_eth_notify_can_receive(s);
591 }
592 if (set & MODER_TXEN) {
593 s->tx_desc = 0;
594 open_eth_check_start_xmit(s);
595 }
596}
597
598static void open_eth_int_source_host_write(OpenEthState *s, uint32_t val)
599{
600 uint32_t old = s->regs[INT_SOURCE];
601
602 s->regs[INT_SOURCE] &= ~val;
603 open_eth_update_irq(s, old & s->regs[INT_MASK],
604 s->regs[INT_SOURCE] & s->regs[INT_MASK]);
605}
606
607static void open_eth_int_mask_host_write(OpenEthState *s, uint32_t val)
608{
609 uint32_t old = s->regs[INT_MASK];
610
611 s->regs[INT_MASK] = val;
612 open_eth_update_irq(s, s->regs[INT_SOURCE] & old,
613 s->regs[INT_SOURCE] & s->regs[INT_MASK]);
614}
615
616static void open_eth_tx_bd_num_host_write(OpenEthState *s, uint32_t val)
617{
618 if (val < 0x80) {
619 bool enable = s->regs[TX_BD_NUM] == 0x80;
620
621 s->regs[TX_BD_NUM] = val;
622 if (enable) {
623 open_eth_notify_can_receive(s);
624 }
625 }
626}
627
628static void open_eth_mii_command_host_write(OpenEthState *s, uint32_t val)
629{
630 unsigned fiad = GET_REGFIELD(s, MIIADDRESS, FIAD);
631 unsigned rgad = GET_REGFIELD(s, MIIADDRESS, RGAD);
632
633 if (val & MIICOMMAND_WCTRLDATA) {
634 if (fiad == DEFAULT_PHY) {
635 mii_write_host(&s->mii, rgad,
636 GET_REGFIELD(s, MIITX_DATA, CTRLDATA));
637 }
638 }
639 if (val & MIICOMMAND_RSTAT) {
640 if (fiad == DEFAULT_PHY) {
641 SET_REGFIELD(s, MIIRX_DATA, PRSD,
642 mii_read_host(&s->mii, rgad));
643 } else {
644 s->regs[MIIRX_DATA] = 0xffff;
645 }
646 SET_REGFIELD(s, MIISTATUS, LINKFAIL, qemu_get_queue(s->nic)->link_down);
647 }
648}
649
650static void open_eth_mii_tx_host_write(OpenEthState *s, uint32_t val)
651{
652 SET_REGFIELD(s, MIITX_DATA, CTRLDATA, val);
653 if (GET_REGFIELD(s, MIIADDRESS, FIAD) == DEFAULT_PHY) {
654 mii_write_host(&s->mii, GET_REGFIELD(s, MIIADDRESS, RGAD),
655 GET_REGFIELD(s, MIITX_DATA, CTRLDATA));
656 }
657}
658
659static void open_eth_reg_write(void *opaque,
660 hwaddr addr, uint64_t val, unsigned int size)
661{
662 static void (*reg_write[REG_MAX])(OpenEthState *s, uint32_t val) = {
663 [MODER] = open_eth_moder_host_write,
664 [INT_SOURCE] = open_eth_int_source_host_write,
665 [INT_MASK] = open_eth_int_mask_host_write,
666 [TX_BD_NUM] = open_eth_tx_bd_num_host_write,
667 [MIICOMMAND] = open_eth_mii_command_host_write,
668 [MIITX_DATA] = open_eth_mii_tx_host_write,
669 [MIISTATUS] = open_eth_ro,
670 };
671 OpenEthState *s = opaque;
672 unsigned idx = addr / 4;
673
674 if (idx < REG_MAX) {
675 trace_open_eth_reg_write((uint32_t)addr, (uint32_t)val);
676 if (reg_write[idx]) {
677 reg_write[idx](s, val);
678 } else {
679 s->regs[idx] = val;
680 }
681 }
682}
683
684static uint64_t open_eth_desc_read(void *opaque,
685 hwaddr addr, unsigned int size)
686{
687 OpenEthState *s = opaque;
688 uint64_t v = 0;
689
690 addr &= 0x3ff;
691 memcpy(&v, (uint8_t *)s->desc + addr, size);
692 trace_open_eth_desc_read((uint32_t)addr, (uint32_t)v);
693 return v;
694}
695
696static void open_eth_desc_write(void *opaque,
697 hwaddr addr, uint64_t val, unsigned int size)
698{
699 OpenEthState *s = opaque;
700
701 addr &= 0x3ff;
702 trace_open_eth_desc_write((uint32_t)addr, (uint32_t)val);
703 memcpy((uint8_t *)s->desc + addr, &val, size);
704 open_eth_check_start_xmit(s);
705}
706
707
708static const MemoryRegionOps open_eth_reg_ops = {
709 .read = open_eth_reg_read,
710 .write = open_eth_reg_write,
711};
712
713static const MemoryRegionOps open_eth_desc_ops = {
714 .read = open_eth_desc_read,
715 .write = open_eth_desc_write,
716};
717
718static void sysbus_open_eth_realize(DeviceState *dev, Error **errp)
719{
720 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
721 OpenEthState *s = OPEN_ETH(dev);
722
723 memory_region_init_io(&s->reg_io, OBJECT(dev), &open_eth_reg_ops, s,
724 "open_eth.regs", 0x54);
725 sysbus_init_mmio(sbd, &s->reg_io);
726
727 memory_region_init_io(&s->desc_io, OBJECT(dev), &open_eth_desc_ops, s,
728 "open_eth.desc", 0x400);
729 sysbus_init_mmio(sbd, &s->desc_io);
730
731 sysbus_init_irq(sbd, &s->irq);
732
733 s->nic = qemu_new_nic(&net_open_eth_info, &s->conf,
734 object_get_typename(OBJECT(s)), dev->id, s);
735}
736
737static void qdev_open_eth_reset(DeviceState *dev)
738{
739 OpenEthState *d = OPEN_ETH(dev);
740
741 open_eth_reset(d);
742}
743
744static Property open_eth_properties[] = {
745 DEFINE_NIC_PROPERTIES(OpenEthState, conf),
746 DEFINE_PROP_END_OF_LIST(),
747};
748
749static void open_eth_class_init(ObjectClass *klass, void *data)
750{
751 DeviceClass *dc = DEVICE_CLASS(klass);
752
753 dc->realize = sysbus_open_eth_realize;
754 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
755 dc->desc = "Opencores 10/100 Mbit Ethernet";
756 dc->reset = qdev_open_eth_reset;
757 device_class_set_props(dc, open_eth_properties);
758}
759
760static const TypeInfo open_eth_info = {
761 .name = TYPE_OPEN_ETH,
762 .parent = TYPE_SYS_BUS_DEVICE,
763 .instance_size = sizeof(OpenEthState),
764 .class_init = open_eth_class_init,
765};
766
767static void open_eth_register_types(void)
768{
769 type_register_static(&open_eth_info);
770}
771
772type_init(open_eth_register_types)
773
