1/* 2 * bcm2708 aka bcm2835/2836 aka Raspberry Pi/Pi2 SoC platform defines 3 * 4 * These definitions are derived from those in Raspbian Linux at 5 * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h 6 * where they carry the following notice: 7 * 8 * Copyright (C) 2010 Broadcom 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 */ 24 25#ifndef HW_ARM_RASPI_PLATFORM_H 26#define HW_ARM_RASPI_PLATFORM_H 27 28#define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */ 29#define IC0_OFFSET 0x2000 30#define ST_OFFSET 0x3000 /* System Timer */ 31#define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */ 32#define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */ 33#define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */ 34#define ARMCTRL_OFFSET (ARM_OFFSET + 0x000) 35#define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */ 36#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */ 37#define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores 38 * Doorbells & Mailboxes */ 39#define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */ 40#define CM_OFFSET 0x101000 /* Clock Management */ 41#define A2W_OFFSET 0x102000 /* Reset controller */ 42#define AVS_OFFSET 0x103000 /* Audio Video Standard */ 43#define RNG_OFFSET 0x104000 44#define GPIO_OFFSET 0x200000 45#define UART0_OFFSET 0x201000 46#define MMCI0_OFFSET 0x202000 47#define I2S_OFFSET 0x203000 48#define SPI0_OFFSET 0x204000 49#define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ 50#define OTP_OFFSET 0x20f000 51#define THERMAL_OFFSET 0x212000 52#define BSC_SL_OFFSET 0x214000 /* SPI slave */ 53#define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */ 54#define EMMC1_OFFSET 0x300000 55#define SMI_OFFSET 0x600000 56#define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */ 57#define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */ 58#define DBUS_OFFSET 0x900000 59#define AVE0_OFFSET 0x910000 60#define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */ 61#define SDRAMC_OFFSET 0xe00000 62#define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */ 63 64/* GPU interrupts */ 65#define INTERRUPT_TIMER0 0 66#define INTERRUPT_TIMER1 1 67#define INTERRUPT_TIMER2 2 68#define INTERRUPT_TIMER3 3 69#define INTERRUPT_CODEC0 4 70#define INTERRUPT_CODEC1 5 71#define INTERRUPT_CODEC2 6 72#define INTERRUPT_JPEG 7 73#define INTERRUPT_ISP 8 74#define INTERRUPT_USB 9 75#define INTERRUPT_3D 10 76#define INTERRUPT_TRANSPOSER 11 77#define INTERRUPT_MULTICORESYNC0 12 78#define INTERRUPT_MULTICORESYNC1 13 79#define INTERRUPT_MULTICORESYNC2 14 80#define INTERRUPT_MULTICORESYNC3 15 81#define INTERRUPT_DMA0 16 82#define INTERRUPT_DMA1 17 83#define INTERRUPT_DMA2 18 84#define INTERRUPT_DMA3 19 85#define INTERRUPT_DMA4 20 86#define INTERRUPT_DMA5 21 87#define INTERRUPT_DMA6 22 88#define INTERRUPT_DMA7 23 89#define INTERRUPT_DMA8 24 90#define INTERRUPT_DMA9 25 91#define INTERRUPT_DMA10 26 92#define INTERRUPT_DMA11 27 93#define INTERRUPT_DMA12 28 94#define INTERRUPT_AUX 29 95#define INTERRUPT_ARM 30 96#define INTERRUPT_VPUDMA 31 97#define INTERRUPT_HOSTPORT 32 98#define INTERRUPT_VIDEOSCALER 33 99#define INTERRUPT_CCP2TX 34 100#define INTERRUPT_SDC 35 101#define INTERRUPT_DSI0 36 102#define INTERRUPT_AVE 37 103#define INTERRUPT_CAM0 38 104#define INTERRUPT_CAM1 39 105#define INTERRUPT_HDMI0 40 106#define INTERRUPT_HDMI1 41 107#define INTERRUPT_PIXELVALVE1 42 108#define INTERRUPT_I2CSPISLV 43 109#define INTERRUPT_DSI1 44 110#define INTERRUPT_PWA0 45 111#define INTERRUPT_PWA1 46 112#define INTERRUPT_CPR 47 113#define INTERRUPT_SMI 48 114#define INTERRUPT_GPIO0 49 115#define INTERRUPT_GPIO1 50 116#define INTERRUPT_GPIO2 51 117#define INTERRUPT_GPIO3 52 118#define INTERRUPT_I2C 53 119#define INTERRUPT_SPI 54 120#define INTERRUPT_I2SPCM 55 121#define INTERRUPT_SDIO 56 122#define INTERRUPT_UART0 57 123#define INTERRUPT_SLIMBUS 58 124#define INTERRUPT_VEC 59 125#define INTERRUPT_CPG 60 126#define INTERRUPT_RNG 61 127#define INTERRUPT_ARASANSDIO 62 128#define INTERRUPT_AVSPMON 63 129 130/* ARM CPU IRQs use a private number space */ 131#define INTERRUPT_ARM_TIMER 0 132#define INTERRUPT_ARM_MAILBOX 1 133#define INTERRUPT_ARM_DOORBELL_0 2 134#define INTERRUPT_ARM_DOORBELL_1 3 135#define INTERRUPT_VPU0_HALTED 4 136#define INTERRUPT_VPU1_HALTED 5 137#define INTERRUPT_ILLEGAL_TYPE0 6 138#define INTERRUPT_ILLEGAL_TYPE1 7 139 140#endif 141