LXR qemu/include/hw/pci-host/designware.h

   1/*
   2 * Copyright (c) 2017, Impinj, Inc.
   3 *
   4 * Designware PCIe IP block emulation
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see
  18 * <http://www.gnu.org/licenses/>.
  19 */
  20
  21#ifndef DESIGNWARE_H
  22#define DESIGNWARE_H
  23
  24#include "hw/sysbus.h"
  25#include "hw/pci/pci.h"
  26#include "hw/pci/pci_bus.h"
  27#include "hw/pci/pcie_host.h"
  28#include "hw/pci/pci_bridge.h"
  29
  30#define TYPE_DESIGNWARE_PCIE_HOST "designware-pcie-host"
  31#define DESIGNWARE_PCIE_HOST(obj) \
  32     OBJECT_CHECK(DesignwarePCIEHost, (obj), TYPE_DESIGNWARE_PCIE_HOST)
  33
  34#define TYPE_DESIGNWARE_PCIE_ROOT "designware-pcie-root"
  35#define DESIGNWARE_PCIE_ROOT(obj) \
  36     OBJECT_CHECK(DesignwarePCIERoot, (obj), TYPE_DESIGNWARE_PCIE_ROOT)
  37
  38struct DesignwarePCIERoot;
  39typedef struct DesignwarePCIERoot DesignwarePCIERoot;
  40
  41typedef struct DesignwarePCIEViewport {
  42    DesignwarePCIERoot *root;
  43
  44    MemoryRegion cfg;
  45    MemoryRegion mem;
  46
  47    uint64_t base;
  48    uint64_t target;
  49    uint32_t limit;
  50    uint32_t cr[2];
  51
  52    bool inbound;
  53} DesignwarePCIEViewport;
  54
  55typedef struct DesignwarePCIEMSIBank {
  56    uint32_t enable;
  57    uint32_t mask;
  58    uint32_t status;
  59} DesignwarePCIEMSIBank;
  60
  61typedef struct DesignwarePCIEMSI {
  62    uint64_t     base;
  63    MemoryRegion iomem;
  64
  65#define DESIGNWARE_PCIE_NUM_MSI_BANKS        1
  66
  67    DesignwarePCIEMSIBank intr[DESIGNWARE_PCIE_NUM_MSI_BANKS];
  68} DesignwarePCIEMSI;
  69
  70struct DesignwarePCIERoot {
  71    PCIBridge parent_obj;
  72
  73    uint32_t atu_viewport;
  74
  75#define DESIGNWARE_PCIE_VIEWPORT_OUTBOUND    0
  76#define DESIGNWARE_PCIE_VIEWPORT_INBOUND     1
  77#define DESIGNWARE_PCIE_NUM_VIEWPORTS        4
  78
  79    DesignwarePCIEViewport viewports[2][DESIGNWARE_PCIE_NUM_VIEWPORTS];
  80    DesignwarePCIEMSI msi;
  81};
  82
  83typedef struct DesignwarePCIEHost {
  84    PCIHostState parent_obj;
  85
  86    DesignwarePCIERoot root;
  87
  88    struct {
  89        AddressSpace address_space;
  90        MemoryRegion address_space_root;
  91
  92        MemoryRegion memory;
  93        MemoryRegion io;
  94
  95        qemu_irq     irqs[4];
  96    } pci;
  97
  98    MemoryRegion mmio;
  99} DesignwarePCIEHost;
 100
 101#endif /* DESIGNWARE_H */
 102