qemu/include/hw/pci/pci_bridge.h
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   1/*
   2 * QEMU PCI bridge
   3 *
   4 * Copyright (c) 2004 Fabrice Bellard
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  19 *
  20 * split out pci bus specific stuff from pci.[hc] to pci_bridge.[hc]
  21 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
  22 *                    VA Linux Systems Japan K.K.
  23 *
  24 */
  25
  26#ifndef QEMU_PCI_BRIDGE_H
  27#define QEMU_PCI_BRIDGE_H
  28
  29#include "hw/pci/pci.h"
  30#include "hw/pci/pci_bus.h"
  31
  32typedef struct PCIBridgeWindows PCIBridgeWindows;
  33
  34/*
  35 * Aliases for each of the address space windows that the bridge
  36 * can forward. Mapped into the bridge's parent's address space,
  37 * as subregions.
  38 */
  39struct PCIBridgeWindows {
  40    MemoryRegion alias_pref_mem;
  41    MemoryRegion alias_mem;
  42    MemoryRegion alias_io;
  43    /*
  44     * When bridge control VGA forwarding is enabled, bridges will
  45     * provide positive decode on the PCI VGA defined I/O port and
  46     * MMIO ranges.  When enabled forwarding is only qualified on the
  47     * I/O and memory enable bits in the bridge command register.
  48     */
  49    MemoryRegion alias_vga[QEMU_PCI_VGA_NUM_REGIONS];
  50};
  51
  52#define TYPE_PCI_BRIDGE "base-pci-bridge"
  53#define PCI_BRIDGE(obj) OBJECT_CHECK(PCIBridge, (obj), TYPE_PCI_BRIDGE)
  54
  55struct PCIBridge {
  56    /*< private >*/
  57    PCIDevice parent_obj;
  58    /*< public >*/
  59
  60    /* private member */
  61    PCIBus sec_bus;
  62    /*
  63     * Memory regions for the bridge's address spaces.  These regions are not
  64     * directly added to system_memory/system_io or its descendants.
  65     * Bridge's secondary bus points to these, so that devices
  66     * under the bridge see these regions as its address spaces.
  67     * The regions are as large as the entire address space -
  68     * they don't take into account any windows.
  69     */
  70    MemoryRegion address_space_mem;
  71    MemoryRegion address_space_io;
  72
  73    PCIBridgeWindows *windows;
  74
  75    pci_map_irq_fn map_irq;
  76    const char *bus_name;
  77};
  78
  79#define PCI_BRIDGE_DEV_PROP_CHASSIS_NR "chassis_nr"
  80#define PCI_BRIDGE_DEV_PROP_MSI        "msi"
  81#define PCI_BRIDGE_DEV_PROP_SHPC       "shpc"
  82
  83int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
  84                          uint16_t svid, uint16_t ssid,
  85                          Error **errp);
  86
  87PCIDevice *pci_bridge_get_device(PCIBus *bus);
  88PCIBus *pci_bridge_get_sec_bus(PCIBridge *br);
  89
  90pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type);
  91pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type);
  92
  93void pci_bridge_update_mappings(PCIBridge *br);
  94void pci_bridge_write_config(PCIDevice *d,
  95                             uint32_t address, uint32_t val, int len);
  96void pci_bridge_disable_base_limit(PCIDevice *dev);
  97void pci_bridge_reset(DeviceState *qdev);
  98
  99void pci_bridge_initfn(PCIDevice *pci_dev, const char *typename);
 100void pci_bridge_exitfn(PCIDevice *pci_dev);
 101
 102void pci_bridge_dev_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
 103                            Error **errp);
 104void pci_bridge_dev_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
 105                              Error **errp);
 106void pci_bridge_dev_unplug_request_cb(HotplugHandler *hotplug_dev,
 107                                      DeviceState *dev, Error **errp);
 108
 109/*
 110 * before qdev initialization(qdev_init()), this function sets bus_name and
 111 * map_irq callback which are necessary for pci_bridge_initfn() to
 112 * initialize bus.
 113 */
 114void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
 115                        pci_map_irq_fn map_irq);
 116
 117/* TODO: add this define to pci_regs.h in linux and then in qemu. */
 118#define  PCI_BRIDGE_CTL_VGA_16BIT       0x10    /* VGA 16-bit decode */
 119#define  PCI_BRIDGE_CTL_DISCARD         0x100   /* Primary discard timer */
 120#define  PCI_BRIDGE_CTL_SEC_DISCARD     0x200   /* Secondary discard timer */
 121#define  PCI_BRIDGE_CTL_DISCARD_STATUS  0x400   /* Discard timer status */
 122#define  PCI_BRIDGE_CTL_DISCARD_SERR    0x800   /* Discard timer SERR# enable */
 123
 124typedef struct PCIBridgeQemuCap {
 125    uint8_t id;     /* Standard PCI capability header field */
 126    uint8_t next;   /* Standard PCI capability header field */
 127    uint8_t len;    /* Standard PCI vendor-specific capability header field */
 128    uint8_t type;   /* Red Hat vendor-specific capability type.
 129                       Types are defined with REDHAT_PCI_CAP_ prefix */
 130
 131    uint32_t bus_res;   /* Minimum number of buses to reserve */
 132    uint64_t io;        /* IO space to reserve */
 133    uint32_t mem;       /* Non-prefetchable memory to reserve */
 134    /* At most one of the following two fields may be set to a value
 135     * different from -1 */
 136    uint32_t mem_pref_32; /* Prefetchable memory to reserve (32-bit MMIO) */
 137    uint64_t mem_pref_64; /* Prefetchable memory to reserve (64-bit MMIO) */
 138} PCIBridgeQemuCap;
 139
 140#define REDHAT_PCI_CAP_RESOURCE_RESERVE 1
 141
 142/*
 143 * PCI BUS/IO/MEM/PREFMEM additional resources recorded as a
 144 * capability in PCI configuration space to reserve on firmware init.
 145 */
 146typedef struct PCIResReserve {
 147    uint32_t bus;
 148    uint64_t io;
 149    uint64_t mem_non_pref;
 150    uint64_t mem_pref_32;
 151    uint64_t mem_pref_64;
 152} PCIResReserve;
 153
 154int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
 155                               PCIResReserve res_reserve, Error **errp);
 156
 157#endif /* QEMU_PCI_BRIDGE_H */
 158