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9
10#include "qemu/osdep.h"
11#include "qemu-common.h"
12#include "qemu/error-report.h"
13#include "qapi/error.h"
14#include <libfdt.h>
15#include "hw/arm/boot.h"
16#include "hw/arm/linux-boot-if.h"
17#include "sysemu/kvm.h"
18#include "sysemu/sysemu.h"
19#include "sysemu/numa.h"
20#include "hw/boards.h"
21#include "sysemu/reset.h"
22#include "hw/loader.h"
23#include "elf.h"
24#include "sysemu/device_tree.h"
25#include "qemu/config-file.h"
26#include "qemu/option.h"
27#include "exec/address-spaces.h"
28#include "qemu/units.h"
29
30
31
32
33
34#define KERNEL_ARGS_ADDR 0x100
35#define KERNEL_NOLOAD_ADDR 0x02000000
36#define KERNEL_LOAD_ADDR 0x00010000
37#define KERNEL64_LOAD_ADDR 0x00080000
38
39#define ARM64_TEXT_OFFSET_OFFSET 8
40#define ARM64_MAGIC_OFFSET 56
41
42#define BOOTLOADER_MAX_SIZE (4 * KiB)
43
44AddressSpace *arm_boot_address_space(ARMCPU *cpu,
45 const struct arm_boot_info *info)
46{
47
48
49
50
51 int asidx;
52 CPUState *cs = CPU(cpu);
53
54 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) {
55 asidx = ARMASIdx_S;
56 } else {
57 asidx = ARMASIdx_NS;
58 }
59
60 return cpu_get_address_space(cs, asidx);
61}
62
63typedef enum {
64 FIXUP_NONE = 0,
65 FIXUP_TERMINATOR,
66 FIXUP_BOARDID,
67 FIXUP_BOARD_SETUP,
68 FIXUP_ARGPTR_LO,
69 FIXUP_ARGPTR_HI,
70 FIXUP_ENTRYPOINT_LO,
71 FIXUP_ENTRYPOINT_HI,
72 FIXUP_GIC_CPU_IF,
73 FIXUP_BOOTREG,
74 FIXUP_DSB,
75 FIXUP_MAX,
76} FixupType;
77
78typedef struct ARMInsnFixup {
79 uint32_t insn;
80 FixupType fixup;
81} ARMInsnFixup;
82
83static const ARMInsnFixup bootloader_aarch64[] = {
84 { 0x580000c0 },
85 { 0xaa1f03e1 },
86 { 0xaa1f03e2 },
87 { 0xaa1f03e3 },
88 { 0x58000084 },
89 { 0xd61f0080 },
90 { 0, FIXUP_ARGPTR_LO },
91 { 0, FIXUP_ARGPTR_HI},
92 { 0, FIXUP_ENTRYPOINT_LO },
93 { 0, FIXUP_ENTRYPOINT_HI },
94 { 0, FIXUP_TERMINATOR }
95};
96
97
98
99
100
101
102
103static const ARMInsnFixup bootloader[] = {
104 { 0xe28fe004 },
105 { 0xe51ff004 },
106 { 0, FIXUP_BOARD_SETUP },
107#define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3
108 { 0xe3a00000 },
109 { 0xe59f1004 },
110 { 0xe59f2004 },
111 { 0xe59ff004 },
112 { 0, FIXUP_BOARDID },
113 { 0, FIXUP_ARGPTR_LO },
114 { 0, FIXUP_ENTRYPOINT_LO },
115 { 0, FIXUP_TERMINATOR }
116};
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132#define DSB_INSN 0xf57ff04f
133#define CP15_DSB_INSN 0xee070f9a
134
135static const ARMInsnFixup smpboot[] = {
136 { 0xe59f2028 },
137 { 0xe59f0028 },
138 { 0xe3a01001 },
139 { 0xe5821000 },
140 { 0xe3a010ff },
141 { 0xe5821004 },
142 { 0, FIXUP_DSB },
143 { 0xe320f003 },
144 { 0xe5901000 },
145 { 0xe1110001 },
146 { 0x0afffffb },
147 { 0xe12fff11 },
148 { 0, FIXUP_GIC_CPU_IF },
149 { 0, FIXUP_BOOTREG },
150 { 0, FIXUP_TERMINATOR }
151};
152
153static void write_bootloader(const char *name, hwaddr addr,
154 const ARMInsnFixup *insns, uint32_t *fixupcontext,
155 AddressSpace *as)
156{
157
158
159
160
161
162 int i, len;
163 uint32_t *code;
164
165 len = 0;
166 while (insns[len].fixup != FIXUP_TERMINATOR) {
167 len++;
168 }
169
170 code = g_new0(uint32_t, len);
171
172 for (i = 0; i < len; i++) {
173 uint32_t insn = insns[i].insn;
174 FixupType fixup = insns[i].fixup;
175
176 switch (fixup) {
177 case FIXUP_NONE:
178 break;
179 case FIXUP_BOARDID:
180 case FIXUP_BOARD_SETUP:
181 case FIXUP_ARGPTR_LO:
182 case FIXUP_ARGPTR_HI:
183 case FIXUP_ENTRYPOINT_LO:
184 case FIXUP_ENTRYPOINT_HI:
185 case FIXUP_GIC_CPU_IF:
186 case FIXUP_BOOTREG:
187 case FIXUP_DSB:
188 insn = fixupcontext[fixup];
189 break;
190 default:
191 abort();
192 }
193 code[i] = tswap32(insn);
194 }
195
196 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE);
197
198 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as);
199
200 g_free(code);
201}
202
203static void default_write_secondary(ARMCPU *cpu,
204 const struct arm_boot_info *info)
205{
206 uint32_t fixupcontext[FIXUP_MAX];
207 AddressSpace *as = arm_boot_address_space(cpu, info);
208
209 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr;
210 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr;
211 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
212 fixupcontext[FIXUP_DSB] = DSB_INSN;
213 } else {
214 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN;
215 }
216
217 write_bootloader("smpboot", info->smp_loader_start,
218 smpboot, fixupcontext, as);
219}
220
221void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
222 const struct arm_boot_info *info,
223 hwaddr mvbar_addr)
224{
225 AddressSpace *as = arm_boot_address_space(cpu, info);
226 int n;
227 uint32_t mvbar_blob[] = {
228
229
230
231
232 0xeafffffe,
233 0xeafffffe,
234 0xe1b0f00e,
235 0xeafffffe,
236 0xeafffffe,
237 0xeafffffe,
238 0xeafffffe,
239 0xeafffffe,
240 };
241 uint32_t board_setup_blob[] = {
242
243 0xee110f51,
244 0xe3800b03,
245 0xee010f51,
246 0xe3a00e00 + (mvbar_addr >> 4),
247 0xee0c0f30,
248 0xee110f11,
249 0xe3800031,
250 0xee010f11,
251 0xe1a0100e,
252 0xe1600070,
253 0xe1a0f001,
254 };
255
256
257 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100);
258
259
260 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr)
261 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr));
262
263 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) {
264 mvbar_blob[n] = tswap32(mvbar_blob[n]);
265 }
266 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob),
267 mvbar_addr, as);
268
269 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
270 board_setup_blob[n] = tswap32(board_setup_blob[n]);
271 }
272 rom_add_blob_fixed_as("board-setup", board_setup_blob,
273 sizeof(board_setup_blob), info->board_setup_addr, as);
274}
275
276static void default_reset_secondary(ARMCPU *cpu,
277 const struct arm_boot_info *info)
278{
279 AddressSpace *as = arm_boot_address_space(cpu, info);
280 CPUState *cs = CPU(cpu);
281
282 address_space_stl_notdirty(as, info->smp_bootreg_addr,
283 0, MEMTXATTRS_UNSPECIFIED, NULL);
284 cpu_set_pc(cs, info->smp_loader_start);
285}
286
287static inline bool have_dtb(const struct arm_boot_info *info)
288{
289 return info->dtb_filename || info->get_dtb;
290}
291
292#define WRITE_WORD(p, value) do { \
293 address_space_stl_notdirty(as, p, value, \
294 MEMTXATTRS_UNSPECIFIED, NULL); \
295 p += 4; \
296} while (0)
297
298static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as)
299{
300 int initrd_size = info->initrd_size;
301 hwaddr base = info->loader_start;
302 hwaddr p;
303
304 p = base + KERNEL_ARGS_ADDR;
305
306 WRITE_WORD(p, 5);
307 WRITE_WORD(p, 0x54410001);
308 WRITE_WORD(p, 1);
309 WRITE_WORD(p, 0x1000);
310 WRITE_WORD(p, 0);
311
312
313 WRITE_WORD(p, 4);
314 WRITE_WORD(p, 0x54410002);
315 WRITE_WORD(p, info->ram_size);
316 WRITE_WORD(p, info->loader_start);
317 if (initrd_size) {
318
319 WRITE_WORD(p, 4);
320 WRITE_WORD(p, 0x54420005);
321 WRITE_WORD(p, info->initrd_start);
322 WRITE_WORD(p, initrd_size);
323 }
324 if (info->kernel_cmdline && *info->kernel_cmdline) {
325
326 int cmdline_size;
327
328 cmdline_size = strlen(info->kernel_cmdline);
329 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED,
330 info->kernel_cmdline, cmdline_size + 1);
331 cmdline_size = (cmdline_size >> 2) + 1;
332 WRITE_WORD(p, cmdline_size + 2);
333 WRITE_WORD(p, 0x54410009);
334 p += cmdline_size * 4;
335 }
336 if (info->atag_board) {
337
338 int atag_board_len;
339 uint8_t atag_board_buf[0x1000];
340
341 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;
342 WRITE_WORD(p, (atag_board_len + 8) >> 2);
343 WRITE_WORD(p, 0x414f4d50);
344 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED,
345 atag_board_buf, atag_board_len);
346 p += atag_board_len;
347 }
348
349 WRITE_WORD(p, 0);
350 WRITE_WORD(p, 0);
351}
352
353static void set_kernel_args_old(const struct arm_boot_info *info,
354 AddressSpace *as)
355{
356 hwaddr p;
357 const char *s;
358 int initrd_size = info->initrd_size;
359 hwaddr base = info->loader_start;
360
361
362 p = base + KERNEL_ARGS_ADDR;
363
364 WRITE_WORD(p, 4096);
365
366 WRITE_WORD(p, info->ram_size / 4096);
367
368 WRITE_WORD(p, 0);
369#define FLAG_READONLY 1
370#define FLAG_RDLOAD 4
371#define FLAG_RDPROMPT 8
372
373 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT);
374
375 WRITE_WORD(p, (31 << 8) | 0);
376
377 WRITE_WORD(p, 0);
378
379 WRITE_WORD(p, 0);
380
381 WRITE_WORD(p, 0);
382
383 WRITE_WORD(p, 0);
384
385 WRITE_WORD(p, 0);
386
387
388
389
390 WRITE_WORD(p, 0);
391
392 WRITE_WORD(p, 0);
393 WRITE_WORD(p, 0);
394 WRITE_WORD(p, 0);
395 WRITE_WORD(p, 0);
396
397 WRITE_WORD(p, 0);
398
399 if (initrd_size) {
400 WRITE_WORD(p, info->initrd_start);
401 } else {
402 WRITE_WORD(p, 0);
403 }
404
405 WRITE_WORD(p, initrd_size);
406
407 WRITE_WORD(p, 0);
408
409 WRITE_WORD(p, 0);
410
411 WRITE_WORD(p, 0);
412
413 WRITE_WORD(p, 0);
414
415 WRITE_WORD(p, 0);
416
417 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) {
418 WRITE_WORD(p, 0);
419 }
420 s = info->kernel_cmdline;
421 if (s) {
422 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1);
423 } else {
424 WRITE_WORD(p, 0);
425 }
426}
427
428static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base,
429 uint32_t scells, hwaddr mem_len,
430 int numa_node_id)
431{
432 char *nodename;
433 int ret;
434
435 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base);
436 qemu_fdt_add_subnode(fdt, nodename);
437 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
438 ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base,
439 scells, mem_len);
440 if (ret < 0) {
441 goto out;
442 }
443
444
445 if (numa_node_id >= 0) {
446 ret = qemu_fdt_setprop_cell(fdt, nodename,
447 "numa-node-id", numa_node_id);
448 }
449out:
450 g_free(nodename);
451 return ret;
452}
453
454static void fdt_add_psci_node(void *fdt)
455{
456 uint32_t cpu_suspend_fn;
457 uint32_t cpu_off_fn;
458 uint32_t cpu_on_fn;
459 uint32_t migrate_fn;
460 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
461 const char *psci_method;
462 int64_t psci_conduit;
463 int rc;
464
465 psci_conduit = object_property_get_int(OBJECT(armcpu),
466 "psci-conduit",
467 &error_abort);
468 switch (psci_conduit) {
469 case QEMU_PSCI_CONDUIT_DISABLED:
470 return;
471 case QEMU_PSCI_CONDUIT_HVC:
472 psci_method = "hvc";
473 break;
474 case QEMU_PSCI_CONDUIT_SMC:
475 psci_method = "smc";
476 break;
477 default:
478 g_assert_not_reached();
479 }
480
481
482
483
484
485 rc = fdt_path_offset(fdt, "/psci");
486 if (rc >= 0) {
487 return;
488 }
489
490 qemu_fdt_add_subnode(fdt, "/psci");
491 if (armcpu->psci_version == 2) {
492 const char comp[] = "arm,psci-0.2\0arm,psci";
493 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
494
495 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF;
496 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) {
497 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND;
498 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON;
499 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE;
500 } else {
501 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND;
502 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON;
503 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE;
504 }
505 } else {
506 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci");
507
508 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND;
509 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF;
510 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON;
511 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE;
512 }
513
514
515
516
517
518
519 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method);
520
521 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn);
522 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn);
523 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn);
524 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn);
525}
526
527int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
528 hwaddr addr_limit, AddressSpace *as, MachineState *ms)
529{
530 void *fdt = NULL;
531 int size, rc, n = 0;
532 uint32_t acells, scells;
533 unsigned int i;
534 hwaddr mem_base, mem_len;
535 char **node_path;
536 Error *err = NULL;
537
538 if (binfo->dtb_filename) {
539 char *filename;
540 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename);
541 if (!filename) {
542 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
543 goto fail;
544 }
545
546 fdt = load_device_tree(filename, &size);
547 if (!fdt) {
548 fprintf(stderr, "Couldn't open dtb file %s\n", filename);
549 g_free(filename);
550 goto fail;
551 }
552 g_free(filename);
553 } else {
554 fdt = binfo->get_dtb(binfo, &size);
555 if (!fdt) {
556 fprintf(stderr, "Board was unable to create a dtb blob\n");
557 goto fail;
558 }
559 }
560
561 if (addr_limit > addr && size > (addr_limit - addr)) {
562
563
564
565
566 g_free(fdt);
567 return 0;
568 }
569
570 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
571 NULL, &error_fatal);
572 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
573 NULL, &error_fatal);
574 if (acells == 0 || scells == 0) {
575 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n");
576 goto fail;
577 }
578
579 if (scells < 2 && binfo->ram_size >= 4 * GiB) {
580
581
582
583 fprintf(stderr, "qemu: dtb file not compatible with "
584 "RAM size > 4GB\n");
585 goto fail;
586 }
587
588
589 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err);
590 if (err) {
591 error_report_err(err);
592 goto fail;
593 }
594 while (node_path[n]) {
595 if (g_str_has_prefix(node_path[n], "/memory")) {
596 qemu_fdt_nop_node(fdt, node_path[n]);
597 }
598 n++;
599 }
600 g_strfreev(node_path);
601
602 if (ms->numa_state != NULL && ms->numa_state->num_nodes > 0) {
603 mem_base = binfo->loader_start;
604 for (i = 0; i < ms->numa_state->num_nodes; i++) {
605 mem_len = ms->numa_state->nodes[i].node_mem;
606 rc = fdt_add_memory_node(fdt, acells, mem_base,
607 scells, mem_len, i);
608 if (rc < 0) {
609 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n",
610 mem_base);
611 goto fail;
612 }
613
614 mem_base += mem_len;
615 }
616 } else {
617 rc = fdt_add_memory_node(fdt, acells, binfo->loader_start,
618 scells, binfo->ram_size, -1);
619 if (rc < 0) {
620 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n",
621 binfo->loader_start);
622 goto fail;
623 }
624 }
625
626 rc = fdt_path_offset(fdt, "/chosen");
627 if (rc < 0) {
628 qemu_fdt_add_subnode(fdt, "/chosen");
629 }
630
631 if (ms->kernel_cmdline && *ms->kernel_cmdline) {
632 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
633 ms->kernel_cmdline);
634 if (rc < 0) {
635 fprintf(stderr, "couldn't set /chosen/bootargs\n");
636 goto fail;
637 }
638 }
639
640 if (binfo->initrd_size) {
641 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
642 binfo->initrd_start);
643 if (rc < 0) {
644 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
645 goto fail;
646 }
647
648 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
649 binfo->initrd_start + binfo->initrd_size);
650 if (rc < 0) {
651 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
652 goto fail;
653 }
654 }
655
656 fdt_add_psci_node(fdt);
657
658 if (binfo->modify_dtb) {
659 binfo->modify_dtb(binfo, fdt);
660 }
661
662 qemu_fdt_dumpdtb(fdt, size);
663
664
665
666
667 rom_add_blob_fixed_as("dtb", fdt, size, addr, as);
668
669 g_free(fdt);
670
671 return size;
672
673fail:
674 g_free(fdt);
675 return -1;
676}
677
678static void do_cpu_reset(void *opaque)
679{
680 ARMCPU *cpu = opaque;
681 CPUState *cs = CPU(cpu);
682 CPUARMState *env = &cpu->env;
683 const struct arm_boot_info *info = env->boot_info;
684
685 cpu_reset(cs);
686 if (info) {
687 if (!info->is_linux) {
688 int i;
689
690 uint64_t entry = info->entry;
691
692 switch (info->endianness) {
693 case ARM_ENDIANNESS_LE:
694 env->cp15.sctlr_el[1] &= ~SCTLR_E0E;
695 for (i = 1; i < 4; ++i) {
696 env->cp15.sctlr_el[i] &= ~SCTLR_EE;
697 }
698 env->uncached_cpsr &= ~CPSR_E;
699 break;
700 case ARM_ENDIANNESS_BE8:
701 env->cp15.sctlr_el[1] |= SCTLR_E0E;
702 for (i = 1; i < 4; ++i) {
703 env->cp15.sctlr_el[i] |= SCTLR_EE;
704 }
705 env->uncached_cpsr |= CPSR_E;
706 break;
707 case ARM_ENDIANNESS_BE32:
708 env->cp15.sctlr_el[1] |= SCTLR_B;
709 break;
710 case ARM_ENDIANNESS_UNKNOWN:
711 break;
712 default:
713 g_assert_not_reached();
714 }
715
716 cpu_set_pc(cs, entry);
717 } else {
718
719
720
721
722
723
724 if (arm_feature(env, ARM_FEATURE_EL3)) {
725
726
727
728
729
730
731 if (env->aarch64) {
732 env->cp15.scr_el3 |= SCR_RW;
733 if (arm_feature(env, ARM_FEATURE_EL2)) {
734 env->cp15.hcr_el2 |= HCR_RW;
735 env->pstate = PSTATE_MODE_EL2h;
736 } else {
737 env->pstate = PSTATE_MODE_EL1h;
738 }
739 if (cpu_isar_feature(aa64_pauth, cpu)) {
740 env->cp15.scr_el3 |= SCR_API | SCR_APK;
741 }
742 if (cpu_isar_feature(aa64_mte, cpu)) {
743 env->cp15.scr_el3 |= SCR_ATA;
744 }
745 if (cpu_isar_feature(aa64_sve, cpu)) {
746 env->cp15.cptr_el[3] |= CPTR_EZ;
747 }
748
749 assert(!info->secure_boot);
750
751
752
753
754 assert(!info->secure_board_setup);
755 }
756
757 if (arm_feature(env, ARM_FEATURE_EL2)) {
758
759 env->cp15.scr_el3 |= SCR_HCE;
760 }
761
762
763 if (!info->secure_boot &&
764 (cs != first_cpu || !info->secure_board_setup)) {
765
766 env->cp15.scr_el3 |= SCR_NS;
767
768 env->cp15.nsacr |= 3 << 10;
769 }
770 }
771
772 if (!env->aarch64 && !info->secure_boot &&
773 arm_feature(env, ARM_FEATURE_EL2)) {
774
775
776
777
778
779
780 cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw);
781 }
782
783 if (cs == first_cpu) {
784 AddressSpace *as = arm_boot_address_space(cpu, info);
785
786 cpu_set_pc(cs, info->loader_start);
787
788 if (!have_dtb(info)) {
789 if (old_param) {
790 set_kernel_args_old(info, as);
791 } else {
792 set_kernel_args(info, as);
793 }
794 }
795 } else {
796 info->secondary_cpu_reset_hook(cpu, info);
797 }
798 }
799 arm_rebuild_hflags(env);
800 }
801}
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
821 uint16_t data_key, const char *image_name,
822 bool try_decompress)
823{
824 size_t size = -1;
825 uint8_t *data;
826
827 if (image_name == NULL) {
828 return;
829 }
830
831 if (try_decompress) {
832 size = load_image_gzipped_buffer(image_name,
833 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data);
834 }
835
836 if (size == (size_t)-1) {
837 gchar *contents;
838 gsize length;
839
840 if (!g_file_get_contents(image_name, &contents, &length, NULL)) {
841 error_report("failed to load \"%s\"", image_name);
842 exit(1);
843 }
844 size = length;
845 data = (uint8_t *)contents;
846 }
847
848 fw_cfg_add_i32(fw_cfg, size_key, size);
849 fw_cfg_add_bytes(fw_cfg, data_key, data, size);
850}
851
852static int do_arm_linux_init(Object *obj, void *opaque)
853{
854 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) {
855 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj);
856 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj);
857 struct arm_boot_info *info = opaque;
858
859 if (albifc->arm_linux_init) {
860 albifc->arm_linux_init(albif, info->secure_boot);
861 }
862 }
863 return 0;
864}
865
866static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
867 uint64_t *lowaddr, uint64_t *highaddr,
868 int elf_machine, AddressSpace *as)
869{
870 bool elf_is64;
871 union {
872 Elf32_Ehdr h32;
873 Elf64_Ehdr h64;
874 } elf_header;
875 int data_swab = 0;
876 bool big_endian;
877 int64_t ret = -1;
878 Error *err = NULL;
879
880
881 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err);
882 if (err) {
883 error_free(err);
884 return ret;
885 }
886
887 if (elf_is64) {
888 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB;
889 info->endianness = big_endian ? ARM_ENDIANNESS_BE8
890 : ARM_ENDIANNESS_LE;
891 } else {
892 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB;
893 if (big_endian) {
894 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) {
895 info->endianness = ARM_ENDIANNESS_BE8;
896 } else {
897 info->endianness = ARM_ENDIANNESS_BE32;
898
899
900
901
902
903
904
905 data_swab = 2;
906 }
907 } else {
908 info->endianness = ARM_ENDIANNESS_LE;
909 }
910 }
911
912 ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL,
913 pentry, lowaddr, highaddr, NULL, big_endian, elf_machine,
914 1, data_swab, as);
915 if (ret <= 0) {
916
917 exit(1);
918 }
919
920 return ret;
921}
922
923static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
924 hwaddr *entry, AddressSpace *as)
925{
926 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR;
927 uint64_t kernel_size = 0;
928 uint8_t *buffer;
929 int size;
930
931
932 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES,
933 &buffer);
934
935 if (size < 0) {
936 gsize len;
937
938
939 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) {
940 return -1;
941 }
942 size = len;
943 }
944
945
946 if (size > ARM64_MAGIC_OFFSET + 4 &&
947 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) {
948 uint64_t hdrvals[2];
949
950
951
952
953
954 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals));
955
956 kernel_size = le64_to_cpu(hdrvals[1]);
957
958 if (kernel_size != 0) {
959 kernel_load_offset = le64_to_cpu(hdrvals[0]);
960
961
962
963
964
965
966
967
968
969
970 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) {
971 kernel_load_offset += 2 * MiB;
972 }
973 }
974 }
975
976
977
978
979
980
981 if (kernel_size == 0) {
982 kernel_size = size;
983 }
984
985 *entry = mem_base + kernel_load_offset;
986 rom_add_blob_fixed_as(filename, buffer, size, *entry, as);
987
988 g_free(buffer);
989
990 return kernel_size;
991}
992
993static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
994 struct arm_boot_info *info)
995{
996
997 CPUState *cs;
998 AddressSpace *as = arm_boot_address_space(cpu, info);
999 int kernel_size;
1000 int initrd_size;
1001 int is_linux = 0;
1002 uint64_t elf_entry;
1003
1004 uint64_t image_low_addr = 0, image_high_addr = 0;
1005 int elf_machine;
1006 hwaddr entry;
1007 static const ARMInsnFixup *primary_loader;
1008 uint64_t ram_end = info->loader_start + info->ram_size;
1009
1010 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1011 primary_loader = bootloader_aarch64;
1012 elf_machine = EM_AARCH64;
1013 } else {
1014 primary_loader = bootloader;
1015 if (!info->write_board_setup) {
1016 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET;
1017 }
1018 elf_machine = EM_ARM;
1019 }
1020
1021 if (!info->secondary_cpu_reset_hook) {
1022 info->secondary_cpu_reset_hook = default_reset_secondary;
1023 }
1024 if (!info->write_secondary_boot) {
1025 info->write_secondary_boot = default_write_secondary;
1026 }
1027
1028 if (info->nb_cpus == 0)
1029 info->nb_cpus = 1;
1030
1031
1032 kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr,
1033 &image_high_addr, elf_machine, as);
1034 if (kernel_size > 0 && have_dtb(info)) {
1035
1036
1037
1038
1039 if (image_low_addr > info->loader_start
1040 || image_high_addr < info->loader_start) {
1041
1042
1043
1044
1045 if (image_low_addr < info->loader_start) {
1046 image_low_addr = 0;
1047 }
1048 info->dtb_start = info->loader_start;
1049 info->dtb_limit = image_low_addr;
1050 }
1051 }
1052 entry = elf_entry;
1053 if (kernel_size < 0) {
1054 uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR;
1055 kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr,
1056 &is_linux, NULL, NULL, as);
1057 if (kernel_size >= 0) {
1058 image_low_addr = loadaddr;
1059 image_high_addr = image_low_addr + kernel_size;
1060 }
1061 }
1062 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {
1063 kernel_size = load_aarch64_image(info->kernel_filename,
1064 info->loader_start, &entry, as);
1065 is_linux = 1;
1066 if (kernel_size >= 0) {
1067 image_low_addr = entry;
1068 image_high_addr = image_low_addr + kernel_size;
1069 }
1070 } else if (kernel_size < 0) {
1071
1072 entry = info->loader_start + KERNEL_LOAD_ADDR;
1073 kernel_size = load_image_targphys_as(info->kernel_filename, entry,
1074 ram_end - KERNEL_LOAD_ADDR, as);
1075 is_linux = 1;
1076 if (kernel_size >= 0) {
1077 image_low_addr = entry;
1078 image_high_addr = image_low_addr + kernel_size;
1079 }
1080 }
1081 if (kernel_size < 0) {
1082 error_report("could not load kernel '%s'", info->kernel_filename);
1083 exit(1);
1084 }
1085
1086 if (kernel_size > info->ram_size) {
1087 error_report("kernel '%s' is too large to fit in RAM "
1088 "(kernel size %d, RAM size %" PRId64 ")",
1089 info->kernel_filename, kernel_size, info->ram_size);
1090 exit(1);
1091 }
1092
1093 info->entry = entry;
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110 info->initrd_start = info->loader_start +
1111 MIN(info->ram_size / 2, 128 * MiB);
1112 if (image_high_addr) {
1113 info->initrd_start = MAX(info->initrd_start, image_high_addr);
1114 }
1115 info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start);
1116
1117 if (is_linux) {
1118 uint32_t fixupcontext[FIXUP_MAX];
1119
1120 if (info->initrd_filename) {
1121
1122 if (info->initrd_start >= ram_end) {
1123 error_report("not enough space after kernel to load initrd");
1124 exit(1);
1125 }
1126
1127 initrd_size = load_ramdisk_as(info->initrd_filename,
1128 info->initrd_start,
1129 ram_end - info->initrd_start, as);
1130 if (initrd_size < 0) {
1131 initrd_size = load_image_targphys_as(info->initrd_filename,
1132 info->initrd_start,
1133 ram_end -
1134 info->initrd_start,
1135 as);
1136 }
1137 if (initrd_size < 0) {
1138 error_report("could not load initrd '%s'",
1139 info->initrd_filename);
1140 exit(1);
1141 }
1142 if (info->initrd_start + initrd_size > ram_end) {
1143 error_report("could not load initrd '%s': "
1144 "too big to fit into RAM after the kernel",
1145 info->initrd_filename);
1146 exit(1);
1147 }
1148 } else {
1149 initrd_size = 0;
1150 }
1151 info->initrd_size = initrd_size;
1152
1153 fixupcontext[FIXUP_BOARDID] = info->board_id;
1154 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr;
1155
1156
1157
1158
1159
1160 if (have_dtb(info)) {
1161 hwaddr align;
1162
1163 if (elf_machine == EM_AARCH64) {
1164
1165
1166
1167
1168
1169
1170
1171 align = 2 * MiB;
1172 } else {
1173
1174
1175
1176
1177 align = 4 * KiB;
1178 }
1179
1180
1181 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size,
1182 align);
1183 if (info->dtb_start >= ram_end) {
1184 error_report("Not enough space for DTB after kernel/initrd");
1185 exit(1);
1186 }
1187 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start;
1188 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32;
1189 } else {
1190 fixupcontext[FIXUP_ARGPTR_LO] =
1191 info->loader_start + KERNEL_ARGS_ADDR;
1192 fixupcontext[FIXUP_ARGPTR_HI] =
1193 (info->loader_start + KERNEL_ARGS_ADDR) >> 32;
1194 if (info->ram_size >= 4 * GiB) {
1195 error_report("RAM size must be less than 4GB to boot"
1196 " Linux kernel using ATAGS (try passing a device tree"
1197 " using -dtb)");
1198 exit(1);
1199 }
1200 }
1201 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry;
1202 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32;
1203
1204 write_bootloader("bootloader", info->loader_start,
1205 primary_loader, fixupcontext, as);
1206
1207 if (info->nb_cpus > 1) {
1208 info->write_secondary_boot(cpu, info);
1209 }
1210 if (info->write_board_setup) {
1211 info->write_board_setup(cpu, info);
1212 }
1213
1214
1215
1216
1217
1218 object_child_foreach_recursive(object_get_root(),
1219 do_arm_linux_init, info);
1220 }
1221 info->is_linux = is_linux;
1222
1223 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
1224 ARM_CPU(cs)->env.boot_info = info;
1225 }
1226}
1227
1228static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info)
1229{
1230
1231
1232 if (have_dtb(info)) {
1233
1234
1235
1236
1237
1238 info->dtb_start = info->loader_start;
1239 }
1240
1241 if (info->kernel_filename) {
1242 FWCfgState *fw_cfg;
1243 bool try_decompressing_kernel;
1244
1245 fw_cfg = fw_cfg_find();
1246 try_decompressing_kernel = arm_feature(&cpu->env,
1247 ARM_FEATURE_AARCH64);
1248
1249
1250
1251
1252
1253
1254 load_image_to_fw_cfg(fw_cfg,
1255 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
1256 info->kernel_filename,
1257 try_decompressing_kernel);
1258 load_image_to_fw_cfg(fw_cfg,
1259 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
1260 info->initrd_filename, false);
1261
1262 if (info->kernel_cmdline) {
1263 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1264 strlen(info->kernel_cmdline) + 1);
1265 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
1266 info->kernel_cmdline);
1267 }
1268 }
1269
1270
1271
1272
1273
1274
1275}
1276
1277void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
1278{
1279 CPUState *cs;
1280 AddressSpace *as = arm_boot_address_space(cpu, info);
1281
1282
1283
1284
1285
1286
1287
1288 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
1289 qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
1290 }
1291
1292
1293
1294
1295
1296
1297 assert(!(info->secure_board_setup && kvm_enabled()));
1298 info->kernel_filename = ms->kernel_filename;
1299 info->kernel_cmdline = ms->kernel_cmdline;
1300 info->initrd_filename = ms->initrd_filename;
1301 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
1302 info->dtb_limit = 0;
1303
1304
1305 if (!info->kernel_filename || info->firmware_loaded) {
1306 arm_setup_firmware_boot(cpu, info);
1307 } else {
1308 arm_setup_direct_kernel_boot(cpu, info);
1309 }
1310
1311 if (!info->skip_dtb_autoload && have_dtb(info)) {
1312 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1313 exit(1);
1314 }
1315 }
1316}
1317
1318static const TypeInfo arm_linux_boot_if_info = {
1319 .name = TYPE_ARM_LINUX_BOOT_IF,
1320 .parent = TYPE_INTERFACE,
1321 .class_size = sizeof(ARMLinuxBootIfClass),
1322};
1323
1324static void arm_linux_boot_register_types(void)
1325{
1326 type_register_static(&arm_linux_boot_if_info);
1327}
1328
1329type_init(arm_linux_boot_register_types)
1330