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20#include "qemu/osdep.h"
21#include "qemu/units.h"
22#include "qapi/error.h"
23#include "hw/sysbus.h"
24#include "migration/vmstate.h"
25#include "net/net.h"
26#include "hw/irq.h"
27#include "hw/qdev-properties.h"
28#include "qemu/log.h"
29#include "trace.h"
30#include "net/checksum.h"
31#include "qemu/module.h"
32#include "exec/cpu-common.h"
33#include "sysemu/dma.h"
34#include "hw/net/allwinner-sun8i-emac.h"
35
36
37enum {
38 REG_BASIC_CTL_0 = 0x0000,
39 REG_BASIC_CTL_1 = 0x0004,
40 REG_INT_STA = 0x0008,
41 REG_INT_EN = 0x000C,
42 REG_TX_CTL_0 = 0x0010,
43 REG_TX_CTL_1 = 0x0014,
44 REG_TX_FLOW_CTL = 0x001C,
45 REG_TX_DMA_DESC_LIST = 0x0020,
46 REG_RX_CTL_0 = 0x0024,
47 REG_RX_CTL_1 = 0x0028,
48 REG_RX_DMA_DESC_LIST = 0x0034,
49 REG_FRM_FLT = 0x0038,
50 REG_RX_HASH_0 = 0x0040,
51 REG_RX_HASH_1 = 0x0044,
52 REG_MII_CMD = 0x0048,
53 REG_MII_DATA = 0x004C,
54 REG_ADDR_HIGH = 0x0050,
55 REG_ADDR_LOW = 0x0054,
56 REG_TX_DMA_STA = 0x00B0,
57 REG_TX_CUR_DESC = 0x00B4,
58 REG_TX_CUR_BUF = 0x00B8,
59 REG_RX_DMA_STA = 0x00C0,
60 REG_RX_CUR_DESC = 0x00C4,
61 REG_RX_CUR_BUF = 0x00C8,
62 REG_RGMII_STA = 0x00D0,
63};
64
65
66enum {
67 BASIC_CTL0_100Mbps = (0b11 << 2),
68 BASIC_CTL0_FD = (1 << 0),
69 BASIC_CTL1_SOFTRST = (1 << 0),
70};
71
72enum {
73 INT_STA_RGMII_LINK = (1 << 16),
74 INT_STA_RX_EARLY = (1 << 13),
75 INT_STA_RX_OVERFLOW = (1 << 12),
76 INT_STA_RX_TIMEOUT = (1 << 11),
77 INT_STA_RX_DMA_STOP = (1 << 10),
78 INT_STA_RX_BUF_UA = (1 << 9),
79 INT_STA_RX = (1 << 8),
80 INT_STA_TX_EARLY = (1 << 5),
81 INT_STA_TX_UNDERFLOW = (1 << 4),
82 INT_STA_TX_TIMEOUT = (1 << 3),
83 INT_STA_TX_BUF_UA = (1 << 2),
84 INT_STA_TX_DMA_STOP = (1 << 1),
85 INT_STA_TX = (1 << 0),
86};
87
88enum {
89 INT_EN_RX_EARLY = (1 << 13),
90 INT_EN_RX_OVERFLOW = (1 << 12),
91 INT_EN_RX_TIMEOUT = (1 << 11),
92 INT_EN_RX_DMA_STOP = (1 << 10),
93 INT_EN_RX_BUF_UA = (1 << 9),
94 INT_EN_RX = (1 << 8),
95 INT_EN_TX_EARLY = (1 << 5),
96 INT_EN_TX_UNDERFLOW = (1 << 4),
97 INT_EN_TX_TIMEOUT = (1 << 3),
98 INT_EN_TX_BUF_UA = (1 << 2),
99 INT_EN_TX_DMA_STOP = (1 << 1),
100 INT_EN_TX = (1 << 0),
101};
102
103enum {
104 TX_CTL0_TX_EN = (1 << 31),
105 TX_CTL1_TX_DMA_START = (1 << 31),
106 TX_CTL1_TX_DMA_EN = (1 << 30),
107 TX_CTL1_TX_FLUSH = (1 << 0),
108};
109
110enum {
111 RX_CTL0_RX_EN = (1 << 31),
112 RX_CTL0_STRIP_FCS = (1 << 28),
113 RX_CTL0_CRC_IPV4 = (1 << 27),
114};
115
116enum {
117 RX_CTL1_RX_DMA_START = (1 << 31),
118 RX_CTL1_RX_DMA_EN = (1 << 30),
119 RX_CTL1_RX_MD = (1 << 1),
120};
121
122enum {
123 RX_FRM_FLT_DIS_ADDR = (1 << 31),
124};
125
126enum {
127 MII_CMD_PHY_ADDR_SHIFT = (12),
128 MII_CMD_PHY_ADDR_MASK = (0xf000),
129 MII_CMD_PHY_REG_SHIFT = (4),
130 MII_CMD_PHY_REG_MASK = (0xf0),
131 MII_CMD_PHY_RW = (1 << 1),
132 MII_CMD_PHY_BUSY = (1 << 0),
133};
134
135enum {
136 TX_DMA_STA_STOP = (0b000),
137 TX_DMA_STA_RUN_FETCH = (0b001),
138 TX_DMA_STA_WAIT_STA = (0b010),
139};
140
141enum {
142 RX_DMA_STA_STOP = (0b000),
143 RX_DMA_STA_RUN_FETCH = (0b001),
144 RX_DMA_STA_WAIT_FRM = (0b011),
145};
146
147
148enum {
149 REG_BASIC_CTL_1_RST = 0x08000000,
150};
151
152
153enum {
154 AW_SUN8I_EMAC_MIN_PKT_SZ = 64
155};
156
157
158typedef struct FrameDescriptor {
159 uint32_t status;
160 uint32_t status2;
161 uint32_t addr;
162 uint32_t next;
163} FrameDescriptor;
164
165
166enum {
167 DESC_STATUS_CTL = (1 << 31),
168 DESC_STATUS2_BUF_SIZE_MASK = (0x7ff),
169};
170
171
172enum {
173 TX_DESC_STATUS_LENGTH_ERR = (1 << 14),
174 TX_DESC_STATUS2_FIRST_DESC = (1 << 29),
175 TX_DESC_STATUS2_LAST_DESC = (1 << 30),
176 TX_DESC_STATUS2_CHECKSUM_MASK = (0x3 << 27),
177};
178
179
180enum {
181 RX_DESC_STATUS_FIRST_DESC = (1 << 9),
182 RX_DESC_STATUS_LAST_DESC = (1 << 8),
183 RX_DESC_STATUS_FRM_LEN_MASK = (0x3fff0000),
184 RX_DESC_STATUS_FRM_LEN_SHIFT = (16),
185 RX_DESC_STATUS_NO_BUF = (1 << 14),
186 RX_DESC_STATUS_HEADER_ERR = (1 << 7),
187 RX_DESC_STATUS_LENGTH_ERR = (1 << 4),
188 RX_DESC_STATUS_CRC_ERR = (1 << 1),
189 RX_DESC_STATUS_PAYLOAD_ERR = (1 << 0),
190 RX_DESC_STATUS2_RX_INT_CTL = (1 << 31),
191};
192
193
194enum {
195 MII_REG_CR = (0x0),
196 MII_REG_ST = (0x1),
197 MII_REG_ID_HIGH = (0x2),
198 MII_REG_ID_LOW = (0x3),
199 MII_REG_ADV = (0x4),
200 MII_REG_LPA = (0x5),
201};
202
203
204enum {
205 MII_REG_CR_RESET = (1 << 15),
206 MII_REG_CR_POWERDOWN = (1 << 11),
207 MII_REG_CR_10Mbit = (0),
208 MII_REG_CR_100Mbit = (1 << 13),
209 MII_REG_CR_1000Mbit = (1 << 6),
210 MII_REG_CR_AUTO_NEG = (1 << 12),
211 MII_REG_CR_AUTO_NEG_RESTART = (1 << 9),
212 MII_REG_CR_FULLDUPLEX = (1 << 8),
213};
214
215enum {
216 MII_REG_ST_100BASE_T4 = (1 << 15),
217 MII_REG_ST_100BASE_X_FD = (1 << 14),
218 MII_REG_ST_100BASE_X_HD = (1 << 13),
219 MII_REG_ST_10_FD = (1 << 12),
220 MII_REG_ST_10_HD = (1 << 11),
221 MII_REG_ST_100BASE_T2_FD = (1 << 10),
222 MII_REG_ST_100BASE_T2_HD = (1 << 9),
223 MII_REG_ST_AUTONEG_COMPLETE = (1 << 5),
224 MII_REG_ST_AUTONEG_AVAIL = (1 << 3),
225 MII_REG_ST_LINK_UP = (1 << 2),
226};
227
228enum {
229 MII_REG_LPA_10_HD = (1 << 5),
230 MII_REG_LPA_10_FD = (1 << 6),
231 MII_REG_LPA_100_HD = (1 << 7),
232 MII_REG_LPA_100_FD = (1 << 8),
233 MII_REG_LPA_PAUSE = (1 << 10),
234 MII_REG_LPA_ASYMPAUSE = (1 << 11),
235};
236
237
238enum {
239 MII_PHY_ID_HIGH = 0x0044,
240 MII_PHY_ID_LOW = 0x1400,
241};
242
243static void allwinner_sun8i_emac_mii_set_link(AwSun8iEmacState *s,
244 bool link_active)
245{
246 if (link_active) {
247 s->mii_st |= MII_REG_ST_LINK_UP;
248 } else {
249 s->mii_st &= ~MII_REG_ST_LINK_UP;
250 }
251}
252
253static void allwinner_sun8i_emac_mii_reset(AwSun8iEmacState *s,
254 bool link_active)
255{
256 s->mii_cr = MII_REG_CR_100Mbit | MII_REG_CR_AUTO_NEG |
257 MII_REG_CR_FULLDUPLEX;
258 s->mii_st = MII_REG_ST_100BASE_T4 | MII_REG_ST_100BASE_X_FD |
259 MII_REG_ST_100BASE_X_HD | MII_REG_ST_10_FD | MII_REG_ST_10_HD |
260 MII_REG_ST_100BASE_T2_FD | MII_REG_ST_100BASE_T2_HD |
261 MII_REG_ST_AUTONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL;
262 s->mii_adv = 0;
263
264 allwinner_sun8i_emac_mii_set_link(s, link_active);
265}
266
267static void allwinner_sun8i_emac_mii_cmd(AwSun8iEmacState *s)
268{
269 uint8_t addr, reg;
270
271 addr = (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) >> MII_CMD_PHY_ADDR_SHIFT;
272 reg = (s->mii_cmd & MII_CMD_PHY_REG_MASK) >> MII_CMD_PHY_REG_SHIFT;
273
274 if (addr != s->mii_phy_addr) {
275 return;
276 }
277
278
279 if (s->mii_cmd & MII_CMD_PHY_RW) {
280 trace_allwinner_sun8i_emac_mii_write_reg(reg, s->mii_data);
281
282 switch (reg) {
283 case MII_REG_CR:
284 if (s->mii_data & MII_REG_CR_RESET) {
285 allwinner_sun8i_emac_mii_reset(s, s->mii_st &
286 MII_REG_ST_LINK_UP);
287 } else {
288 s->mii_cr = s->mii_data & ~(MII_REG_CR_RESET |
289 MII_REG_CR_AUTO_NEG_RESTART);
290 }
291 break;
292 case MII_REG_ADV:
293 s->mii_adv = s->mii_data;
294 break;
295 case MII_REG_ID_HIGH:
296 case MII_REG_ID_LOW:
297 case MII_REG_LPA:
298 break;
299 default:
300 qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to "
301 "unknown MII register 0x%x\n", reg);
302 break;
303 }
304 } else {
305 switch (reg) {
306 case MII_REG_CR:
307 s->mii_data = s->mii_cr;
308 break;
309 case MII_REG_ST:
310 s->mii_data = s->mii_st;
311 break;
312 case MII_REG_ID_HIGH:
313 s->mii_data = MII_PHY_ID_HIGH;
314 break;
315 case MII_REG_ID_LOW:
316 s->mii_data = MII_PHY_ID_LOW;
317 break;
318 case MII_REG_ADV:
319 s->mii_data = s->mii_adv;
320 break;
321 case MII_REG_LPA:
322 s->mii_data = MII_REG_LPA_10_HD | MII_REG_LPA_10_FD |
323 MII_REG_LPA_100_HD | MII_REG_LPA_100_FD |
324 MII_REG_LPA_PAUSE | MII_REG_LPA_ASYMPAUSE;
325 break;
326 default:
327 qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to "
328 "unknown MII register 0x%x\n", reg);
329 s->mii_data = 0;
330 break;
331 }
332
333 trace_allwinner_sun8i_emac_mii_read_reg(reg, s->mii_data);
334 }
335}
336
337static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s)
338{
339 qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0);
340}
341
342static uint32_t allwinner_sun8i_emac_next_desc(AwSun8iEmacState *s,
343 FrameDescriptor *desc,
344 size_t min_size)
345{
346 uint32_t paddr = desc->next;
347
348 dma_memory_read(&s->dma_as, paddr, desc, sizeof(*desc));
349
350 if ((desc->status & DESC_STATUS_CTL) &&
351 (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
352 return paddr;
353 } else {
354 return 0;
355 }
356}
357
358static uint32_t allwinner_sun8i_emac_get_desc(AwSun8iEmacState *s,
359 FrameDescriptor *desc,
360 uint32_t start_addr,
361 size_t min_size)
362{
363 uint32_t desc_addr = start_addr;
364
365
366 while (desc_addr != 0) {
367 dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc));
368
369 if ((desc->status & DESC_STATUS_CTL) &&
370 (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
371 return desc_addr;
372 } else if (desc->next == start_addr) {
373 break;
374 } else {
375 desc_addr = desc->next;
376 }
377 }
378
379 return 0;
380}
381
382static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s,
383 FrameDescriptor *desc,
384 size_t min_size)
385{
386 return allwinner_sun8i_emac_get_desc(s, desc, s->rx_desc_curr, min_size);
387}
388
389static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s,
390 FrameDescriptor *desc,
391 size_t min_size)
392{
393 return allwinner_sun8i_emac_get_desc(s, desc, s->tx_desc_head, min_size);
394}
395
396static void allwinner_sun8i_emac_flush_desc(AwSun8iEmacState *s,
397 FrameDescriptor *desc,
398 uint32_t phys_addr)
399{
400 dma_memory_write(&s->dma_as, phys_addr, desc, sizeof(*desc));
401}
402
403static bool allwinner_sun8i_emac_can_receive(NetClientState *nc)
404{
405 AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
406 FrameDescriptor desc;
407
408 return (s->rx_ctl0 & RX_CTL0_RX_EN) &&
409 (allwinner_sun8i_emac_rx_desc(s, &desc, 0) != 0);
410}
411
412static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
413 const uint8_t *buf,
414 size_t size)
415{
416 AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
417 FrameDescriptor desc;
418 size_t bytes_left = size;
419 size_t desc_bytes = 0;
420 size_t pad_fcs_size = 4;
421 size_t padding = 0;
422
423 if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) {
424 return -1;
425 }
426
427 s->rx_desc_curr = allwinner_sun8i_emac_rx_desc(s, &desc,
428 AW_SUN8I_EMAC_MIN_PKT_SZ);
429 if (!s->rx_desc_curr) {
430 s->int_sta |= INT_STA_RX_BUF_UA;
431 }
432
433
434 while (s->rx_desc_curr && bytes_left > 0) {
435 desc.status &= ~DESC_STATUS_CTL;
436 desc.status &= ~RX_DESC_STATUS_FRM_LEN_MASK;
437
438 if (bytes_left == size) {
439 desc.status |= RX_DESC_STATUS_FIRST_DESC;
440 }
441
442 if ((desc.status2 & DESC_STATUS2_BUF_SIZE_MASK) <
443 (bytes_left + pad_fcs_size)) {
444 desc_bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
445 desc.status |= desc_bytes << RX_DESC_STATUS_FRM_LEN_SHIFT;
446 } else {
447 padding = pad_fcs_size;
448 if (bytes_left < AW_SUN8I_EMAC_MIN_PKT_SZ) {
449 padding += (AW_SUN8I_EMAC_MIN_PKT_SZ - bytes_left);
450 }
451
452 desc_bytes = (bytes_left);
453 desc.status |= RX_DESC_STATUS_LAST_DESC;
454 desc.status |= (bytes_left + padding)
455 << RX_DESC_STATUS_FRM_LEN_SHIFT;
456 }
457
458 dma_memory_write(&s->dma_as, desc.addr, buf, desc_bytes);
459 allwinner_sun8i_emac_flush_desc(s, &desc, s->rx_desc_curr);
460 trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr,
461 desc_bytes);
462
463
464 if (!(desc.status2 & RX_DESC_STATUS2_RX_INT_CTL)) {
465 s->int_sta |= INT_STA_RX;
466 }
467
468
469 buf += desc_bytes;
470 bytes_left -= desc_bytes;
471
472
473 s->rx_desc_curr = allwinner_sun8i_emac_next_desc(s, &desc, 64);
474 if (!s->rx_desc_curr) {
475
476 s->int_sta |= INT_STA_RX_BUF_UA;
477 s->rx_desc_curr = s->rx_desc_head;
478 break;
479 }
480 }
481
482
483 s->rx_ctl1 &= ~RX_CTL1_RX_DMA_START;
484 allwinner_sun8i_emac_update_irq(s);
485
486 return size;
487}
488
489static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
490{
491 NetClientState *nc = qemu_get_queue(s->nic);
492 FrameDescriptor desc;
493 size_t bytes = 0;
494 size_t packet_bytes = 0;
495 size_t transmitted = 0;
496 static uint8_t packet_buf[2048];
497
498 s->tx_desc_curr = allwinner_sun8i_emac_tx_desc(s, &desc, 0);
499
500
501 while (s->tx_desc_curr != 0) {
502
503
504 bytes = desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
505 if (bytes + packet_bytes > sizeof(packet_buf)) {
506 desc.status |= TX_DESC_STATUS_LENGTH_ERR;
507 break;
508 }
509 dma_memory_read(&s->dma_as, desc.addr, packet_buf + packet_bytes, bytes);
510 packet_bytes += bytes;
511 desc.status &= ~DESC_STATUS_CTL;
512 allwinner_sun8i_emac_flush_desc(s, &desc, s->tx_desc_curr);
513
514
515 if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) {
516 if (desc.status2 & TX_DESC_STATUS2_CHECKSUM_MASK) {
517 net_checksum_calculate(packet_buf, packet_bytes);
518 }
519
520 qemu_send_packet(nc, packet_buf, packet_bytes);
521 trace_allwinner_sun8i_emac_transmit(s->tx_desc_curr, desc.addr,
522 bytes);
523
524 packet_bytes = 0;
525 transmitted++;
526 }
527 s->tx_desc_curr = allwinner_sun8i_emac_next_desc(s, &desc, 0);
528 }
529
530
531 if (transmitted > 0) {
532 s->int_sta |= INT_STA_TX;
533 s->tx_ctl1 &= ~TX_CTL1_TX_DMA_START;
534 allwinner_sun8i_emac_update_irq(s);
535 }
536}
537
538static void allwinner_sun8i_emac_reset(DeviceState *dev)
539{
540 AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
541 NetClientState *nc = qemu_get_queue(s->nic);
542
543 trace_allwinner_sun8i_emac_reset();
544
545 s->mii_cmd = 0;
546 s->mii_data = 0;
547 s->basic_ctl0 = 0;
548 s->basic_ctl1 = REG_BASIC_CTL_1_RST;
549 s->int_en = 0;
550 s->int_sta = 0;
551 s->frm_flt = 0;
552 s->rx_ctl0 = 0;
553 s->rx_ctl1 = RX_CTL1_RX_MD;
554 s->rx_desc_head = 0;
555 s->rx_desc_curr = 0;
556 s->tx_ctl0 = 0;
557 s->tx_ctl1 = 0;
558 s->tx_desc_head = 0;
559 s->tx_desc_curr = 0;
560 s->tx_flowctl = 0;
561
562 allwinner_sun8i_emac_mii_reset(s, !nc->link_down);
563}
564
565static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
566 unsigned size)
567{
568 AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque);
569 uint64_t value = 0;
570 FrameDescriptor desc;
571
572 switch (offset) {
573 case REG_BASIC_CTL_0:
574 value = s->basic_ctl0;
575 break;
576 case REG_BASIC_CTL_1:
577 value = s->basic_ctl1;
578 break;
579 case REG_INT_STA:
580 value = s->int_sta;
581 break;
582 case REG_INT_EN:
583 value = s->int_en;
584 break;
585 case REG_TX_CTL_0:
586 value = s->tx_ctl0;
587 break;
588 case REG_TX_CTL_1:
589 value = s->tx_ctl1;
590 break;
591 case REG_TX_FLOW_CTL:
592 value = s->tx_flowctl;
593 break;
594 case REG_TX_DMA_DESC_LIST:
595 value = s->tx_desc_head;
596 break;
597 case REG_RX_CTL_0:
598 value = s->rx_ctl0;
599 break;
600 case REG_RX_CTL_1:
601 value = s->rx_ctl1;
602 break;
603 case REG_RX_DMA_DESC_LIST:
604 value = s->rx_desc_head;
605 break;
606 case REG_FRM_FLT:
607 value = s->frm_flt;
608 break;
609 case REG_RX_HASH_0:
610 case REG_RX_HASH_1:
611 break;
612 case REG_MII_CMD:
613 value = s->mii_cmd;
614 break;
615 case REG_MII_DATA:
616 value = s->mii_data;
617 break;
618 case REG_ADDR_HIGH:
619 value = lduw_le_p(s->conf.macaddr.a + 4);
620 break;
621 case REG_ADDR_LOW:
622 value = ldl_le_p(s->conf.macaddr.a);
623 break;
624 case REG_TX_DMA_STA:
625 break;
626 case REG_TX_CUR_DESC:
627 value = s->tx_desc_curr;
628 break;
629 case REG_TX_CUR_BUF:
630 if (s->tx_desc_curr != 0) {
631 dma_memory_read(&s->dma_as, s->tx_desc_curr, &desc, sizeof(desc));
632 value = desc.addr;
633 } else {
634 value = 0;
635 }
636 break;
637 case REG_RX_DMA_STA:
638 break;
639 case REG_RX_CUR_DESC:
640 value = s->rx_desc_curr;
641 break;
642 case REG_RX_CUR_BUF:
643 if (s->rx_desc_curr != 0) {
644 dma_memory_read(&s->dma_as, s->rx_desc_curr, &desc, sizeof(desc));
645 value = desc.addr;
646 } else {
647 value = 0;
648 }
649 break;
650 case REG_RGMII_STA:
651 break;
652 default:
653 qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown "
654 "EMAC register 0x" TARGET_FMT_plx "\n",
655 offset);
656 }
657
658 trace_allwinner_sun8i_emac_read(offset, value);
659 return value;
660}
661
662static void allwinner_sun8i_emac_write(void *opaque, hwaddr offset,
663 uint64_t value, unsigned size)
664{
665 AwSun8iEmacState *s = AW_SUN8I_EMAC(opaque);
666 NetClientState *nc = qemu_get_queue(s->nic);
667
668 trace_allwinner_sun8i_emac_write(offset, value);
669
670 switch (offset) {
671 case REG_BASIC_CTL_0:
672 s->basic_ctl0 = value;
673 break;
674 case REG_BASIC_CTL_1:
675 if (value & BASIC_CTL1_SOFTRST) {
676 allwinner_sun8i_emac_reset(DEVICE(s));
677 value &= ~BASIC_CTL1_SOFTRST;
678 }
679 s->basic_ctl1 = value;
680 if (allwinner_sun8i_emac_can_receive(nc)) {
681 qemu_flush_queued_packets(nc);
682 }
683 break;
684 case REG_INT_STA:
685 s->int_sta &= ~value;
686 allwinner_sun8i_emac_update_irq(s);
687 break;
688 case REG_INT_EN:
689 s->int_en = value;
690 allwinner_sun8i_emac_update_irq(s);
691 break;
692 case REG_TX_CTL_0:
693 s->tx_ctl0 = value;
694 break;
695 case REG_TX_CTL_1:
696 s->tx_ctl1 = value;
697 if (value & TX_CTL1_TX_DMA_EN) {
698 allwinner_sun8i_emac_transmit(s);
699 }
700 break;
701 case REG_TX_FLOW_CTL:
702 s->tx_flowctl = value;
703 break;
704 case REG_TX_DMA_DESC_LIST:
705 s->tx_desc_head = value;
706 s->tx_desc_curr = value;
707 break;
708 case REG_RX_CTL_0:
709 s->rx_ctl0 = value;
710 break;
711 case REG_RX_CTL_1:
712 s->rx_ctl1 = value | RX_CTL1_RX_MD;
713 if ((value & RX_CTL1_RX_DMA_EN) &&
714 allwinner_sun8i_emac_can_receive(nc)) {
715 qemu_flush_queued_packets(nc);
716 }
717 break;
718 case REG_RX_DMA_DESC_LIST:
719 s->rx_desc_head = value;
720 s->rx_desc_curr = value;
721 break;
722 case REG_FRM_FLT:
723 s->frm_flt = value;
724 break;
725 case REG_RX_HASH_0:
726 case REG_RX_HASH_1:
727 break;
728 case REG_MII_CMD:
729 s->mii_cmd = value & ~MII_CMD_PHY_BUSY;
730 allwinner_sun8i_emac_mii_cmd(s);
731 break;
732 case REG_MII_DATA:
733 s->mii_data = value;
734 break;
735 case REG_ADDR_HIGH:
736 stw_le_p(s->conf.macaddr.a + 4, value);
737 break;
738 case REG_ADDR_LOW:
739 stl_le_p(s->conf.macaddr.a, value);
740 break;
741 case REG_TX_DMA_STA:
742 case REG_TX_CUR_DESC:
743 case REG_TX_CUR_BUF:
744 case REG_RX_DMA_STA:
745 case REG_RX_CUR_DESC:
746 case REG_RX_CUR_BUF:
747 case REG_RGMII_STA:
748 break;
749 default:
750 qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown "
751 "EMAC register 0x" TARGET_FMT_plx "\n",
752 offset);
753 }
754}
755
756static void allwinner_sun8i_emac_set_link(NetClientState *nc)
757{
758 AwSun8iEmacState *s = qemu_get_nic_opaque(nc);
759
760 trace_allwinner_sun8i_emac_set_link(!nc->link_down);
761 allwinner_sun8i_emac_mii_set_link(s, !nc->link_down);
762}
763
764static const MemoryRegionOps allwinner_sun8i_emac_mem_ops = {
765 .read = allwinner_sun8i_emac_read,
766 .write = allwinner_sun8i_emac_write,
767 .endianness = DEVICE_NATIVE_ENDIAN,
768 .valid = {
769 .min_access_size = 4,
770 .max_access_size = 4,
771 },
772 .impl.min_access_size = 4,
773};
774
775static NetClientInfo net_allwinner_sun8i_emac_info = {
776 .type = NET_CLIENT_DRIVER_NIC,
777 .size = sizeof(NICState),
778 .can_receive = allwinner_sun8i_emac_can_receive,
779 .receive = allwinner_sun8i_emac_receive,
780 .link_status_changed = allwinner_sun8i_emac_set_link,
781};
782
783static void allwinner_sun8i_emac_init(Object *obj)
784{
785 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
786 AwSun8iEmacState *s = AW_SUN8I_EMAC(obj);
787
788 memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sun8i_emac_mem_ops,
789 s, TYPE_AW_SUN8I_EMAC, 64 * KiB);
790 sysbus_init_mmio(sbd, &s->iomem);
791 sysbus_init_irq(sbd, &s->irq);
792}
793
794static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
795{
796 AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
797
798 if (!s->dma_mr) {
799 error_setg(errp, TYPE_AW_SUN8I_EMAC " 'dma-memory' link not set");
800 return;
801 }
802
803 address_space_init(&s->dma_as, s->dma_mr, "emac-dma");
804
805 qemu_macaddr_default_if_unset(&s->conf.macaddr);
806 s->nic = qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf,
807 object_get_typename(OBJECT(dev)), dev->id, s);
808 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
809}
810
811static Property allwinner_sun8i_emac_properties[] = {
812 DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf),
813 DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0),
814 DEFINE_PROP_LINK("dma-memory", AwSun8iEmacState, dma_mr,
815 TYPE_MEMORY_REGION, MemoryRegion *),
816 DEFINE_PROP_END_OF_LIST(),
817};
818
819static int allwinner_sun8i_emac_post_load(void *opaque, int version_id)
820{
821 AwSun8iEmacState *s = opaque;
822
823 allwinner_sun8i_emac_set_link(qemu_get_queue(s->nic));
824
825 return 0;
826}
827
828static const VMStateDescription vmstate_aw_emac = {
829 .name = "allwinner-sun8i-emac",
830 .version_id = 1,
831 .minimum_version_id = 1,
832 .post_load = allwinner_sun8i_emac_post_load,
833 .fields = (VMStateField[]) {
834 VMSTATE_UINT8(mii_phy_addr, AwSun8iEmacState),
835 VMSTATE_UINT32(mii_cmd, AwSun8iEmacState),
836 VMSTATE_UINT32(mii_data, AwSun8iEmacState),
837 VMSTATE_UINT32(mii_cr, AwSun8iEmacState),
838 VMSTATE_UINT32(mii_st, AwSun8iEmacState),
839 VMSTATE_UINT32(mii_adv, AwSun8iEmacState),
840 VMSTATE_UINT32(basic_ctl0, AwSun8iEmacState),
841 VMSTATE_UINT32(basic_ctl1, AwSun8iEmacState),
842 VMSTATE_UINT32(int_en, AwSun8iEmacState),
843 VMSTATE_UINT32(int_sta, AwSun8iEmacState),
844 VMSTATE_UINT32(frm_flt, AwSun8iEmacState),
845 VMSTATE_UINT32(rx_ctl0, AwSun8iEmacState),
846 VMSTATE_UINT32(rx_ctl1, AwSun8iEmacState),
847 VMSTATE_UINT32(rx_desc_head, AwSun8iEmacState),
848 VMSTATE_UINT32(rx_desc_curr, AwSun8iEmacState),
849 VMSTATE_UINT32(tx_ctl0, AwSun8iEmacState),
850 VMSTATE_UINT32(tx_ctl1, AwSun8iEmacState),
851 VMSTATE_UINT32(tx_desc_head, AwSun8iEmacState),
852 VMSTATE_UINT32(tx_desc_curr, AwSun8iEmacState),
853 VMSTATE_UINT32(tx_flowctl, AwSun8iEmacState),
854 VMSTATE_END_OF_LIST()
855 }
856};
857
858static void allwinner_sun8i_emac_class_init(ObjectClass *klass, void *data)
859{
860 DeviceClass *dc = DEVICE_CLASS(klass);
861
862 dc->realize = allwinner_sun8i_emac_realize;
863 dc->reset = allwinner_sun8i_emac_reset;
864 dc->vmsd = &vmstate_aw_emac;
865 device_class_set_props(dc, allwinner_sun8i_emac_properties);
866}
867
868static const TypeInfo allwinner_sun8i_emac_info = {
869 .name = TYPE_AW_SUN8I_EMAC,
870 .parent = TYPE_SYS_BUS_DEVICE,
871 .instance_size = sizeof(AwSun8iEmacState),
872 .instance_init = allwinner_sun8i_emac_init,
873 .class_init = allwinner_sun8i_emac_class_init,
874};
875
876static void allwinner_sun8i_emac_register_types(void)
877{
878 type_register_static(&allwinner_sun8i_emac_info);
879}
880
881type_init(allwinner_sun8i_emac_register_types)
882
