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25#include "qemu/osdep.h"
26#include "hw/pci/pci.h"
27#include "hw/qdev-properties.h"
28#include "sysemu/dma.h"
29#include "hw/pci/msi.h"
30#include "qemu/iov.h"
31#include "qemu/main-loop.h"
32#include "qemu/module.h"
33#include "hw/scsi/scsi.h"
34#include "scsi/constants.h"
35#include "trace.h"
36#include "qapi/error.h"
37#include "mptsas.h"
38#include "migration/qemu-file-types.h"
39#include "migration/vmstate.h"
40#include "mpi.h"
41
42#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
43#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
44
45#define MPTSAS1068_PRODUCT_ID \
46 (MPI_FW_HEADER_PID_FAMILY_1068_SAS | \
47 MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI | \
48 MPI_FW_HEADER_PID_TYPE_SAS)
49
50struct MPTSASRequest {
51 MPIMsgSCSIIORequest scsi_io;
52 SCSIRequest *sreq;
53 QEMUSGList qsg;
54 MPTSASState *dev;
55
56 QTAILQ_ENTRY(MPTSASRequest) next;
57};
58
59static void mptsas_update_interrupt(MPTSASState *s)
60{
61 PCIDevice *pci = (PCIDevice *) s;
62 uint32_t state = s->intr_status & ~(s->intr_mask | MPI_HIS_IOP_DOORBELL_STATUS);
63
64 if (msi_enabled(pci)) {
65 if (state) {
66 trace_mptsas_irq_msi(s);
67 msi_notify(pci, 0);
68 }
69 }
70
71 trace_mptsas_irq_intx(s, !!state);
72 pci_set_irq(pci, !!state);
73}
74
75static void mptsas_set_fault(MPTSASState *s, uint32_t code)
76{
77 if ((s->state & MPI_IOC_STATE_FAULT) == 0) {
78 s->state = MPI_IOC_STATE_FAULT | code;
79 }
80}
81
82#define MPTSAS_FIFO_INVALID(s, name) \
83 ((s)->name##_head > ARRAY_SIZE((s)->name) || \
84 (s)->name##_tail > ARRAY_SIZE((s)->name))
85
86#define MPTSAS_FIFO_EMPTY(s, name) \
87 ((s)->name##_head == (s)->name##_tail)
88
89#define MPTSAS_FIFO_FULL(s, name) \
90 ((s)->name##_head == ((s)->name##_tail + 1) % ARRAY_SIZE((s)->name))
91
92#define MPTSAS_FIFO_GET(s, name) ({ \
93 uint32_t _val = (s)->name[(s)->name##_head++]; \
94 (s)->name##_head %= ARRAY_SIZE((s)->name); \
95 _val; \
96})
97
98#define MPTSAS_FIFO_PUT(s, name, val) do { \
99 (s)->name[(s)->name##_tail++] = (val); \
100 (s)->name##_tail %= ARRAY_SIZE((s)->name); \
101} while(0)
102
103static void mptsas_post_reply(MPTSASState *s, MPIDefaultReply *reply)
104{
105 PCIDevice *pci = (PCIDevice *) s;
106 uint32_t addr_lo;
107
108 if (MPTSAS_FIFO_EMPTY(s, reply_free) || MPTSAS_FIFO_FULL(s, reply_post)) {
109 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES);
110 return;
111 }
112
113 addr_lo = MPTSAS_FIFO_GET(s, reply_free);
114
115 pci_dma_write(pci, addr_lo | s->host_mfa_high_addr, reply,
116 MIN(s->reply_frame_size, 4 * reply->MsgLength));
117
118 MPTSAS_FIFO_PUT(s, reply_post, MPI_ADDRESS_REPLY_A_BIT | (addr_lo >> 1));
119
120 s->intr_status |= MPI_HIS_REPLY_MESSAGE_INTERRUPT;
121 if (s->doorbell_state == DOORBELL_WRITE) {
122 s->doorbell_state = DOORBELL_NONE;
123 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT;
124 }
125 mptsas_update_interrupt(s);
126}
127
128void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply)
129{
130 if (s->doorbell_state == DOORBELL_WRITE) {
131
132
133
134 s->doorbell_state = DOORBELL_READ;
135 s->doorbell_reply_idx = 0;
136 s->doorbell_reply_size = reply->MsgLength * 2;
137 memcpy(s->doorbell_reply, reply, s->doorbell_reply_size * 2);
138 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT;
139 mptsas_update_interrupt(s);
140 } else {
141 mptsas_post_reply(s, reply);
142 }
143}
144
145static void mptsas_turbo_reply(MPTSASState *s, uint32_t msgctx)
146{
147 if (MPTSAS_FIFO_FULL(s, reply_post)) {
148 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES);
149 return;
150 }
151
152
153 MPTSAS_FIFO_PUT(s, reply_post, msgctx);
154
155 s->intr_status |= MPI_HIS_REPLY_MESSAGE_INTERRUPT;
156 mptsas_update_interrupt(s);
157}
158
159#define MPTSAS_MAX_REQUEST_SIZE 52
160
161static const int mpi_request_sizes[] = {
162 [MPI_FUNCTION_SCSI_IO_REQUEST] = sizeof(MPIMsgSCSIIORequest),
163 [MPI_FUNCTION_SCSI_TASK_MGMT] = sizeof(MPIMsgSCSITaskMgmt),
164 [MPI_FUNCTION_IOC_INIT] = sizeof(MPIMsgIOCInit),
165 [MPI_FUNCTION_IOC_FACTS] = sizeof(MPIMsgIOCFacts),
166 [MPI_FUNCTION_CONFIG] = sizeof(MPIMsgConfig),
167 [MPI_FUNCTION_PORT_FACTS] = sizeof(MPIMsgPortFacts),
168 [MPI_FUNCTION_PORT_ENABLE] = sizeof(MPIMsgPortEnable),
169 [MPI_FUNCTION_EVENT_NOTIFICATION] = sizeof(MPIMsgEventNotify),
170};
171
172static dma_addr_t mptsas_ld_sg_base(MPTSASState *s, uint32_t flags_and_length,
173 dma_addr_t *sgaddr)
174{
175 PCIDevice *pci = (PCIDevice *) s;
176 dma_addr_t addr;
177
178 if (flags_and_length & MPI_SGE_FLAGS_64_BIT_ADDRESSING) {
179 addr = ldq_le_pci_dma(pci, *sgaddr + 4);
180 *sgaddr += 12;
181 } else {
182 addr = ldl_le_pci_dma(pci, *sgaddr + 4);
183 *sgaddr += 8;
184 }
185 return addr;
186}
187
188static int mptsas_build_sgl(MPTSASState *s, MPTSASRequest *req, hwaddr addr)
189{
190 PCIDevice *pci = (PCIDevice *) s;
191 hwaddr next_chain_addr;
192 uint32_t left;
193 hwaddr sgaddr;
194 uint32_t chain_offset;
195
196 chain_offset = req->scsi_io.ChainOffset;
197 next_chain_addr = addr + chain_offset * sizeof(uint32_t);
198 sgaddr = addr + sizeof(MPIMsgSCSIIORequest);
199 pci_dma_sglist_init(&req->qsg, pci, 4);
200 left = req->scsi_io.DataLength;
201
202 for(;;) {
203 dma_addr_t addr, len;
204 uint32_t flags_and_length;
205
206 flags_and_length = ldl_le_pci_dma(pci, sgaddr);
207 len = flags_and_length & MPI_SGE_LENGTH_MASK;
208 if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK)
209 != MPI_SGE_FLAGS_SIMPLE_ELEMENT ||
210 (!len &&
211 !(flags_and_length & MPI_SGE_FLAGS_END_OF_LIST) &&
212 !(flags_and_length & MPI_SGE_FLAGS_END_OF_BUFFER))) {
213 return MPI_IOCSTATUS_INVALID_SGL;
214 }
215
216 len = MIN(len, left);
217 if (!len) {
218
219
220
221 break;
222 }
223
224 addr = mptsas_ld_sg_base(s, flags_and_length, &sgaddr);
225 qemu_sglist_add(&req->qsg, addr, len);
226 left -= len;
227
228 if (flags_and_length & MPI_SGE_FLAGS_END_OF_LIST) {
229 break;
230 }
231
232 if (flags_and_length & MPI_SGE_FLAGS_LAST_ELEMENT) {
233 if (!chain_offset) {
234 break;
235 }
236
237 flags_and_length = ldl_le_pci_dma(pci, next_chain_addr);
238 if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK)
239 != MPI_SGE_FLAGS_CHAIN_ELEMENT) {
240 return MPI_IOCSTATUS_INVALID_SGL;
241 }
242
243 sgaddr = mptsas_ld_sg_base(s, flags_and_length, &next_chain_addr);
244 chain_offset =
245 (flags_and_length & MPI_SGE_CHAIN_OFFSET_MASK) >> MPI_SGE_CHAIN_OFFSET_SHIFT;
246 next_chain_addr = sgaddr + chain_offset * sizeof(uint32_t);
247 }
248 }
249 return 0;
250}
251
252static void mptsas_free_request(MPTSASRequest *req)
253{
254 MPTSASState *s = req->dev;
255
256 if (req->sreq != NULL) {
257 req->sreq->hba_private = NULL;
258 scsi_req_unref(req->sreq);
259 req->sreq = NULL;
260 QTAILQ_REMOVE(&s->pending, req, next);
261 }
262 qemu_sglist_destroy(&req->qsg);
263 g_free(req);
264}
265
266static int mptsas_scsi_device_find(MPTSASState *s, int bus, int target,
267 uint8_t *lun, SCSIDevice **sdev)
268{
269 if (bus != 0) {
270 return MPI_IOCSTATUS_SCSI_INVALID_BUS;
271 }
272
273 if (target >= s->max_devices) {
274 return MPI_IOCSTATUS_SCSI_INVALID_TARGETID;
275 }
276
277 *sdev = scsi_device_find(&s->bus, bus, target, lun[1]);
278 if (!*sdev) {
279 return MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE;
280 }
281
282 return 0;
283}
284
285static int mptsas_process_scsi_io_request(MPTSASState *s,
286 MPIMsgSCSIIORequest *scsi_io,
287 hwaddr addr)
288{
289 MPTSASRequest *req;
290 MPIMsgSCSIIOReply reply;
291 SCSIDevice *sdev;
292 int status;
293
294 mptsas_fix_scsi_io_endianness(scsi_io);
295
296 trace_mptsas_process_scsi_io_request(s, scsi_io->Bus, scsi_io->TargetID,
297 scsi_io->LUN[1], scsi_io->DataLength);
298
299 status = mptsas_scsi_device_find(s, scsi_io->Bus, scsi_io->TargetID,
300 scsi_io->LUN, &sdev);
301 if (status) {
302 goto bad;
303 }
304
305 req = g_new0(MPTSASRequest, 1);
306 QTAILQ_INSERT_TAIL(&s->pending, req, next);
307 req->scsi_io = *scsi_io;
308 req->dev = s;
309
310 status = mptsas_build_sgl(s, req, addr);
311 if (status) {
312 goto free_bad;
313 }
314
315 if (req->qsg.size < scsi_io->DataLength) {
316 trace_mptsas_sgl_overflow(s, scsi_io->MsgContext, scsi_io->DataLength,
317 req->qsg.size);
318 status = MPI_IOCSTATUS_INVALID_SGL;
319 goto free_bad;
320 }
321
322 req->sreq = scsi_req_new(sdev, scsi_io->MsgContext,
323 scsi_io->LUN[1], scsi_io->CDB, req);
324
325 if (req->sreq->cmd.xfer > scsi_io->DataLength) {
326 goto overrun;
327 }
328 switch (scsi_io->Control & MPI_SCSIIO_CONTROL_DATADIRECTION_MASK) {
329 case MPI_SCSIIO_CONTROL_NODATATRANSFER:
330 if (req->sreq->cmd.mode != SCSI_XFER_NONE) {
331 goto overrun;
332 }
333 break;
334
335 case MPI_SCSIIO_CONTROL_WRITE:
336 if (req->sreq->cmd.mode != SCSI_XFER_TO_DEV) {
337 goto overrun;
338 }
339 break;
340
341 case MPI_SCSIIO_CONTROL_READ:
342 if (req->sreq->cmd.mode != SCSI_XFER_FROM_DEV) {
343 goto overrun;
344 }
345 break;
346 }
347
348 if (scsi_req_enqueue(req->sreq)) {
349 scsi_req_continue(req->sreq);
350 }
351 return 0;
352
353overrun:
354 trace_mptsas_scsi_overflow(s, scsi_io->MsgContext, req->sreq->cmd.xfer,
355 scsi_io->DataLength);
356 status = MPI_IOCSTATUS_SCSI_DATA_OVERRUN;
357free_bad:
358 mptsas_free_request(req);
359bad:
360 memset(&reply, 0, sizeof(reply));
361 reply.TargetID = scsi_io->TargetID;
362 reply.Bus = scsi_io->Bus;
363 reply.MsgLength = sizeof(reply) / 4;
364 reply.Function = scsi_io->Function;
365 reply.CDBLength = scsi_io->CDBLength;
366 reply.SenseBufferLength = scsi_io->SenseBufferLength;
367 reply.MsgContext = scsi_io->MsgContext;
368 reply.SCSIState = MPI_SCSI_STATE_NO_SCSI_STATUS;
369 reply.IOCStatus = status;
370
371 mptsas_fix_scsi_io_reply_endianness(&reply);
372 mptsas_reply(s, (MPIDefaultReply *)&reply);
373
374 return 0;
375}
376
377typedef struct {
378 Notifier notifier;
379 MPTSASState *s;
380 MPIMsgSCSITaskMgmtReply *reply;
381} MPTSASCancelNotifier;
382
383static void mptsas_cancel_notify(Notifier *notifier, void *data)
384{
385 MPTSASCancelNotifier *n = container_of(notifier,
386 MPTSASCancelNotifier,
387 notifier);
388
389
390 if (++n->reply->TerminationCount == n->reply->IOCLogInfo) {
391 n->reply->IOCLogInfo = 0;
392 mptsas_fix_scsi_task_mgmt_reply_endianness(n->reply);
393 mptsas_post_reply(n->s, (MPIDefaultReply *)n->reply);
394 g_free(n->reply);
395 }
396 g_free(n);
397}
398
399static void mptsas_process_scsi_task_mgmt(MPTSASState *s, MPIMsgSCSITaskMgmt *req)
400{
401 MPIMsgSCSITaskMgmtReply reply;
402 MPIMsgSCSITaskMgmtReply *reply_async;
403 int status, count;
404 SCSIDevice *sdev;
405 SCSIRequest *r, *next;
406 BusChild *kid;
407
408 mptsas_fix_scsi_task_mgmt_endianness(req);
409
410 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
411 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
412 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
413
414 memset(&reply, 0, sizeof(reply));
415 reply.TargetID = req->TargetID;
416 reply.Bus = req->Bus;
417 reply.MsgLength = sizeof(reply) / 4;
418 reply.Function = req->Function;
419 reply.TaskType = req->TaskType;
420 reply.MsgContext = req->MsgContext;
421
422 switch (req->TaskType) {
423 case MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK:
424 case MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK:
425 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID,
426 req->LUN, &sdev);
427 if (status) {
428 reply.IOCStatus = status;
429 goto out;
430 }
431 if (sdev->lun != req->LUN[1]) {
432 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN;
433 goto out;
434 }
435
436 QTAILQ_FOREACH_SAFE(r, &sdev->requests, next, next) {
437 MPTSASRequest *cmd_req = r->hba_private;
438 if (cmd_req && cmd_req->scsi_io.MsgContext == req->TaskMsgContext) {
439 break;
440 }
441 }
442 if (r) {
443
444
445
446
447 assert(r->hba_private);
448 if (req->TaskType == MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK) {
449
450
451
452 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_SUCCEEDED;
453 } else {
454 MPTSASCancelNotifier *notifier;
455
456 reply_async = g_memdup(&reply, sizeof(MPIMsgSCSITaskMgmtReply));
457 reply_async->IOCLogInfo = INT_MAX;
458
459 count = 1;
460 notifier = g_new(MPTSASCancelNotifier, 1);
461 notifier->s = s;
462 notifier->reply = reply_async;
463 notifier->notifier.notify = mptsas_cancel_notify;
464 scsi_req_cancel_async(r, ¬ifier->notifier);
465 goto reply_maybe_async;
466 }
467 }
468 break;
469
470 case MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
471 case MPI_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET:
472 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID,
473 req->LUN, &sdev);
474 if (status) {
475 reply.IOCStatus = status;
476 goto out;
477 }
478 if (sdev->lun != req->LUN[1]) {
479 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN;
480 goto out;
481 }
482
483 reply_async = g_memdup(&reply, sizeof(MPIMsgSCSITaskMgmtReply));
484 reply_async->IOCLogInfo = INT_MAX;
485
486 count = 0;
487 QTAILQ_FOREACH_SAFE(r, &sdev->requests, next, next) {
488 if (r->hba_private) {
489 MPTSASCancelNotifier *notifier;
490
491 count++;
492 notifier = g_new(MPTSASCancelNotifier, 1);
493 notifier->s = s;
494 notifier->reply = reply_async;
495 notifier->notifier.notify = mptsas_cancel_notify;
496 scsi_req_cancel_async(r, ¬ifier->notifier);
497 }
498 }
499
500reply_maybe_async:
501 if (reply_async->TerminationCount < count) {
502 reply_async->IOCLogInfo = count;
503 return;
504 }
505 g_free(reply_async);
506 reply.TerminationCount = count;
507 break;
508
509 case MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
510 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID,
511 req->LUN, &sdev);
512 if (status) {
513 reply.IOCStatus = status;
514 goto out;
515 }
516 if (sdev->lun != req->LUN[1]) {
517 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN;
518 goto out;
519 }
520 qdev_reset_all(&sdev->qdev);
521 break;
522
523 case MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
524 if (req->Bus != 0) {
525 reply.IOCStatus = MPI_IOCSTATUS_SCSI_INVALID_BUS;
526 goto out;
527 }
528 if (req->TargetID > s->max_devices) {
529 reply.IOCStatus = MPI_IOCSTATUS_SCSI_INVALID_TARGETID;
530 goto out;
531 }
532
533 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
534 sdev = SCSI_DEVICE(kid->child);
535 if (sdev->channel == 0 && sdev->id == req->TargetID) {
536 qdev_reset_all(kid->child);
537 }
538 }
539 break;
540
541 case MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS:
542 qbus_reset_all(BUS(&s->bus));
543 break;
544
545 default:
546 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED;
547 break;
548 }
549
550out:
551 mptsas_fix_scsi_task_mgmt_reply_endianness(&reply);
552 mptsas_post_reply(s, (MPIDefaultReply *)&reply);
553}
554
555static void mptsas_process_ioc_init(MPTSASState *s, MPIMsgIOCInit *req)
556{
557 MPIMsgIOCInitReply reply;
558
559 mptsas_fix_ioc_init_endianness(req);
560
561 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
562 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
563 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
564
565 s->who_init = req->WhoInit;
566 s->reply_frame_size = req->ReplyFrameSize;
567 s->max_buses = req->MaxBuses;
568 s->max_devices = req->MaxDevices ? req->MaxDevices : 256;
569 s->host_mfa_high_addr = (hwaddr)req->HostMfaHighAddr << 32;
570 s->sense_buffer_high_addr = (hwaddr)req->SenseBufferHighAddr << 32;
571
572 if (s->state == MPI_IOC_STATE_READY) {
573 s->state = MPI_IOC_STATE_OPERATIONAL;
574 }
575
576 memset(&reply, 0, sizeof(reply));
577 reply.WhoInit = s->who_init;
578 reply.MsgLength = sizeof(reply) / 4;
579 reply.Function = req->Function;
580 reply.MaxDevices = s->max_devices;
581 reply.MaxBuses = s->max_buses;
582 reply.MsgContext = req->MsgContext;
583
584 mptsas_fix_ioc_init_reply_endianness(&reply);
585 mptsas_reply(s, (MPIDefaultReply *)&reply);
586}
587
588static void mptsas_process_ioc_facts(MPTSASState *s,
589 MPIMsgIOCFacts *req)
590{
591 MPIMsgIOCFactsReply reply;
592
593 mptsas_fix_ioc_facts_endianness(req);
594
595 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
596 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
597 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
598
599 memset(&reply, 0, sizeof(reply));
600 reply.MsgVersion = 0x0105;
601 reply.MsgLength = sizeof(reply) / 4;
602 reply.Function = req->Function;
603 reply.MsgContext = req->MsgContext;
604 reply.MaxChainDepth = MPTSAS_MAXIMUM_CHAIN_DEPTH;
605 reply.WhoInit = s->who_init;
606 reply.BlockSize = MPTSAS_MAX_REQUEST_SIZE / sizeof(uint32_t);
607 reply.ReplyQueueDepth = ARRAY_SIZE(s->reply_post) - 1;
608 QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->reply_post) != ARRAY_SIZE(s->reply_free));
609
610 reply.RequestFrameSize = 128;
611 reply.ProductID = MPTSAS1068_PRODUCT_ID;
612 reply.CurrentHostMfaHighAddr = s->host_mfa_high_addr >> 32;
613 reply.GlobalCredits = ARRAY_SIZE(s->request_post) - 1;
614 reply.NumberOfPorts = MPTSAS_NUM_PORTS;
615 reply.CurrentSenseBufferHighAddr = s->sense_buffer_high_addr >> 32;
616 reply.CurReplyFrameSize = s->reply_frame_size;
617 reply.MaxDevices = s->max_devices;
618 reply.MaxBuses = s->max_buses;
619 reply.FWVersionDev = 0;
620 reply.FWVersionUnit = 0x92;
621 reply.FWVersionMinor = 0x32;
622 reply.FWVersionMajor = 0x1;
623
624 mptsas_fix_ioc_facts_reply_endianness(&reply);
625 mptsas_reply(s, (MPIDefaultReply *)&reply);
626}
627
628static void mptsas_process_port_facts(MPTSASState *s,
629 MPIMsgPortFacts *req)
630{
631 MPIMsgPortFactsReply reply;
632
633 mptsas_fix_port_facts_endianness(req);
634
635 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
636 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
637 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
638
639 memset(&reply, 0, sizeof(reply));
640 reply.MsgLength = sizeof(reply) / 4;
641 reply.Function = req->Function;
642 reply.PortNumber = req->PortNumber;
643 reply.MsgContext = req->MsgContext;
644
645 if (req->PortNumber < MPTSAS_NUM_PORTS) {
646 reply.PortType = MPI_PORTFACTS_PORTTYPE_SAS;
647 reply.MaxDevices = MPTSAS_NUM_PORTS;
648 reply.PortSCSIID = MPTSAS_NUM_PORTS;
649 reply.ProtocolFlags = MPI_PORTFACTS_PROTOCOL_LOGBUSADDR | MPI_PORTFACTS_PROTOCOL_INITIATOR;
650 }
651
652 mptsas_fix_port_facts_reply_endianness(&reply);
653 mptsas_reply(s, (MPIDefaultReply *)&reply);
654}
655
656static void mptsas_process_port_enable(MPTSASState *s,
657 MPIMsgPortEnable *req)
658{
659 MPIMsgPortEnableReply reply;
660
661 mptsas_fix_port_enable_endianness(req);
662
663 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
664 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
665 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
666
667 memset(&reply, 0, sizeof(reply));
668 reply.MsgLength = sizeof(reply) / 4;
669 reply.PortNumber = req->PortNumber;
670 reply.Function = req->Function;
671 reply.MsgContext = req->MsgContext;
672
673 mptsas_fix_port_enable_reply_endianness(&reply);
674 mptsas_reply(s, (MPIDefaultReply *)&reply);
675}
676
677static void mptsas_process_event_notification(MPTSASState *s,
678 MPIMsgEventNotify *req)
679{
680 MPIMsgEventNotifyReply reply;
681
682 mptsas_fix_event_notification_endianness(req);
683
684 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
685 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
686 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
687
688
689
690
691
692 memset(&reply, 0, sizeof(reply));
693 reply.EventDataLength = sizeof(reply.Data) / 4;
694 reply.MsgLength = sizeof(reply) / 4;
695 reply.Function = req->Function;
696
697
698 reply.MsgFlags = MPI_MSGFLAGS_CONTINUATION_REPLY;
699
700 reply.MsgContext = req->MsgContext;
701 reply.Event = MPI_EVENT_EVENT_CHANGE;
702 reply.Data[0] = !!req->Switch;
703
704 mptsas_fix_event_notification_reply_endianness(&reply);
705 mptsas_reply(s, (MPIDefaultReply *)&reply);
706}
707
708static void mptsas_process_message(MPTSASState *s, MPIRequestHeader *req)
709{
710 trace_mptsas_process_message(s, req->Function, req->MsgContext);
711 switch (req->Function) {
712 case MPI_FUNCTION_SCSI_TASK_MGMT:
713 mptsas_process_scsi_task_mgmt(s, (MPIMsgSCSITaskMgmt *)req);
714 break;
715
716 case MPI_FUNCTION_IOC_INIT:
717 mptsas_process_ioc_init(s, (MPIMsgIOCInit *)req);
718 break;
719
720 case MPI_FUNCTION_IOC_FACTS:
721 mptsas_process_ioc_facts(s, (MPIMsgIOCFacts *)req);
722 break;
723
724 case MPI_FUNCTION_PORT_FACTS:
725 mptsas_process_port_facts(s, (MPIMsgPortFacts *)req);
726 break;
727
728 case MPI_FUNCTION_PORT_ENABLE:
729 mptsas_process_port_enable(s, (MPIMsgPortEnable *)req);
730 break;
731
732 case MPI_FUNCTION_EVENT_NOTIFICATION:
733 mptsas_process_event_notification(s, (MPIMsgEventNotify *)req);
734 break;
735
736 case MPI_FUNCTION_CONFIG:
737 mptsas_process_config(s, (MPIMsgConfig *)req);
738 break;
739
740 default:
741 trace_mptsas_unhandled_cmd(s, req->Function, 0);
742 mptsas_set_fault(s, MPI_IOCSTATUS_INVALID_FUNCTION);
743 break;
744 }
745}
746
747static void mptsas_fetch_request(MPTSASState *s)
748{
749 PCIDevice *pci = (PCIDevice *) s;
750 char req[MPTSAS_MAX_REQUEST_SIZE];
751 MPIRequestHeader *hdr = (MPIRequestHeader *)req;
752 hwaddr addr;
753 int size;
754
755
756 addr = s->host_mfa_high_addr | MPTSAS_FIFO_GET(s, request_post);
757 pci_dma_read(pci, addr, req, sizeof(*hdr));
758
759 if (hdr->Function < ARRAY_SIZE(mpi_request_sizes) &&
760 mpi_request_sizes[hdr->Function]) {
761
762
763
764
765 size = mpi_request_sizes[hdr->Function];
766 assert(size <= MPTSAS_MAX_REQUEST_SIZE);
767 pci_dma_read(pci, addr + sizeof(*hdr), &req[sizeof(*hdr)],
768 size - sizeof(*hdr));
769 }
770
771 if (hdr->Function == MPI_FUNCTION_SCSI_IO_REQUEST) {
772
773
774
775 mptsas_process_scsi_io_request(s, (MPIMsgSCSIIORequest *)req, addr);
776 } else {
777 mptsas_process_message(s, (MPIRequestHeader *)req);
778 }
779}
780
781static void mptsas_fetch_requests(void *opaque)
782{
783 MPTSASState *s = opaque;
784
785 if (s->state != MPI_IOC_STATE_OPERATIONAL) {
786 mptsas_set_fault(s, MPI_IOCSTATUS_INVALID_STATE);
787 return;
788 }
789 while (!MPTSAS_FIFO_EMPTY(s, request_post)) {
790 mptsas_fetch_request(s);
791 }
792}
793
794static void mptsas_soft_reset(MPTSASState *s)
795{
796 uint32_t save_mask;
797
798 trace_mptsas_reset(s);
799
800
801 save_mask = s->intr_mask;
802 s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM;
803 mptsas_update_interrupt(s);
804
805 qbus_reset_all(BUS(&s->bus));
806 s->intr_status = 0;
807 s->intr_mask = save_mask;
808
809 s->reply_free_tail = 0;
810 s->reply_free_head = 0;
811 s->reply_post_tail = 0;
812 s->reply_post_head = 0;
813 s->request_post_tail = 0;
814 s->request_post_head = 0;
815 qemu_bh_cancel(s->request_bh);
816
817 s->state = MPI_IOC_STATE_READY;
818}
819
820static uint32_t mptsas_doorbell_read(MPTSASState *s)
821{
822 uint32_t ret;
823
824 ret = (s->who_init << MPI_DOORBELL_WHO_INIT_SHIFT) & MPI_DOORBELL_WHO_INIT_MASK;
825 ret |= s->state;
826 switch (s->doorbell_state) {
827 case DOORBELL_NONE:
828 break;
829
830 case DOORBELL_WRITE:
831 ret |= MPI_DOORBELL_ACTIVE;
832 break;
833
834 case DOORBELL_READ:
835
836 ret &= ~MPI_DOORBELL_DATA_MASK;
837
838 assert(s->intr_status & MPI_HIS_DOORBELL_INTERRUPT);
839 assert(s->doorbell_reply_idx <= s->doorbell_reply_size);
840
841 ret |= MPI_DOORBELL_ACTIVE;
842 if (s->doorbell_reply_idx < s->doorbell_reply_size) {
843
844
845
846
847 ret |= le16_to_cpu(s->doorbell_reply[s->doorbell_reply_idx++]);
848 }
849 break;
850
851 default:
852 abort();
853 }
854
855 return ret;
856}
857
858static void mptsas_doorbell_write(MPTSASState *s, uint32_t val)
859{
860 if (s->doorbell_state == DOORBELL_WRITE) {
861 if (s->doorbell_idx < s->doorbell_cnt) {
862
863
864
865
866 s->doorbell_msg[s->doorbell_idx++] = cpu_to_le32(val);
867 if (s->doorbell_idx == s->doorbell_cnt) {
868 mptsas_process_message(s, (MPIRequestHeader *)s->doorbell_msg);
869 }
870 }
871 return;
872 }
873
874 switch ((val & MPI_DOORBELL_FUNCTION_MASK) >> MPI_DOORBELL_FUNCTION_SHIFT) {
875 case MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET:
876 mptsas_soft_reset(s);
877 break;
878 case MPI_FUNCTION_IO_UNIT_RESET:
879 break;
880 case MPI_FUNCTION_HANDSHAKE:
881 s->doorbell_state = DOORBELL_WRITE;
882 s->doorbell_idx = 0;
883 s->doorbell_cnt = (val & MPI_DOORBELL_ADD_DWORDS_MASK)
884 >> MPI_DOORBELL_ADD_DWORDS_SHIFT;
885 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT;
886 mptsas_update_interrupt(s);
887 break;
888 default:
889 trace_mptsas_unhandled_doorbell_cmd(s, val);
890 break;
891 }
892}
893
894static void mptsas_write_sequence_write(MPTSASState *s, uint32_t val)
895{
896
897
898
899
900 if (s->diagnostic & MPI_DIAG_DRWE) {
901 goto disable;
902 }
903
904 switch (s->diagnostic_idx) {
905 case 0:
906 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_1ST_KEY_VALUE) {
907 goto disable;
908 }
909 break;
910 case 1:
911 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_2ND_KEY_VALUE) {
912 goto disable;
913 }
914 break;
915 case 2:
916 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_3RD_KEY_VALUE) {
917 goto disable;
918 }
919 break;
920 case 3:
921 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_4TH_KEY_VALUE) {
922 goto disable;
923 }
924 break;
925 case 4:
926 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_5TH_KEY_VALUE) {
927 goto disable;
928 }
929
930
931
932 s->diagnostic |= MPI_DIAG_DRWE;
933 break;
934 }
935 s->diagnostic_idx++;
936 return;
937
938disable:
939 s->diagnostic &= ~MPI_DIAG_DRWE;
940 s->diagnostic_idx = 0;
941}
942
943static int mptsas_hard_reset(MPTSASState *s)
944{
945 mptsas_soft_reset(s);
946
947 s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM;
948
949 s->host_mfa_high_addr = 0;
950 s->sense_buffer_high_addr = 0;
951 s->reply_frame_size = 0;
952 s->max_devices = MPTSAS_NUM_PORTS;
953 s->max_buses = 1;
954
955 return 0;
956}
957
958static void mptsas_interrupt_status_write(MPTSASState *s)
959{
960 switch (s->doorbell_state) {
961 case DOORBELL_NONE:
962 case DOORBELL_WRITE:
963 s->intr_status &= ~MPI_HIS_DOORBELL_INTERRUPT;
964 break;
965
966 case DOORBELL_READ:
967
968 assert(s->intr_status & MPI_HIS_DOORBELL_INTERRUPT);
969 if (s->doorbell_reply_idx == s->doorbell_reply_size) {
970 s->doorbell_state = DOORBELL_NONE;
971 }
972 break;
973
974 default:
975 abort();
976 }
977 mptsas_update_interrupt(s);
978}
979
980static uint32_t mptsas_reply_post_read(MPTSASState *s)
981{
982 uint32_t ret;
983
984 if (!MPTSAS_FIFO_EMPTY(s, reply_post)) {
985 ret = MPTSAS_FIFO_GET(s, reply_post);
986 } else {
987 ret = -1;
988 s->intr_status &= ~MPI_HIS_REPLY_MESSAGE_INTERRUPT;
989 mptsas_update_interrupt(s);
990 }
991
992 return ret;
993}
994
995static uint64_t mptsas_mmio_read(void *opaque, hwaddr addr,
996 unsigned size)
997{
998 MPTSASState *s = opaque;
999 uint32_t ret = 0;
1000
1001 switch (addr & ~3) {
1002 case MPI_DOORBELL_OFFSET:
1003 ret = mptsas_doorbell_read(s);
1004 break;
1005
1006 case MPI_DIAGNOSTIC_OFFSET:
1007 ret = s->diagnostic;
1008 break;
1009
1010 case MPI_HOST_INTERRUPT_STATUS_OFFSET:
1011 ret = s->intr_status;
1012 break;
1013
1014 case MPI_HOST_INTERRUPT_MASK_OFFSET:
1015 ret = s->intr_mask;
1016 break;
1017
1018 case MPI_REPLY_POST_FIFO_OFFSET:
1019 ret = mptsas_reply_post_read(s);
1020 break;
1021
1022 default:
1023 trace_mptsas_mmio_unhandled_read(s, addr);
1024 break;
1025 }
1026 trace_mptsas_mmio_read(s, addr, ret);
1027 return ret;
1028}
1029
1030static void mptsas_mmio_write(void *opaque, hwaddr addr,
1031 uint64_t val, unsigned size)
1032{
1033 MPTSASState *s = opaque;
1034
1035 trace_mptsas_mmio_write(s, addr, val);
1036 switch (addr) {
1037 case MPI_DOORBELL_OFFSET:
1038 mptsas_doorbell_write(s, val);
1039 break;
1040
1041 case MPI_WRITE_SEQUENCE_OFFSET:
1042 mptsas_write_sequence_write(s, val);
1043 break;
1044
1045 case MPI_DIAGNOSTIC_OFFSET:
1046 if (val & MPI_DIAG_RESET_ADAPTER) {
1047 mptsas_hard_reset(s);
1048 }
1049 break;
1050
1051 case MPI_HOST_INTERRUPT_STATUS_OFFSET:
1052 mptsas_interrupt_status_write(s);
1053 break;
1054
1055 case MPI_HOST_INTERRUPT_MASK_OFFSET:
1056 s->intr_mask = val & (MPI_HIM_RIM | MPI_HIM_DIM);
1057 mptsas_update_interrupt(s);
1058 break;
1059
1060 case MPI_REQUEST_POST_FIFO_OFFSET:
1061 if (MPTSAS_FIFO_FULL(s, request_post)) {
1062 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES);
1063 } else {
1064 MPTSAS_FIFO_PUT(s, request_post, val & ~0x03);
1065 qemu_bh_schedule(s->request_bh);
1066 }
1067 break;
1068
1069 case MPI_REPLY_FREE_FIFO_OFFSET:
1070 if (MPTSAS_FIFO_FULL(s, reply_free)) {
1071 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES);
1072 } else {
1073 MPTSAS_FIFO_PUT(s, reply_free, val);
1074 }
1075 break;
1076
1077 default:
1078 trace_mptsas_mmio_unhandled_write(s, addr, val);
1079 break;
1080 }
1081}
1082
1083static const MemoryRegionOps mptsas_mmio_ops = {
1084 .read = mptsas_mmio_read,
1085 .write = mptsas_mmio_write,
1086 .endianness = DEVICE_LITTLE_ENDIAN,
1087 .impl = {
1088 .min_access_size = 4,
1089 .max_access_size = 4,
1090 }
1091};
1092
1093static const MemoryRegionOps mptsas_port_ops = {
1094 .read = mptsas_mmio_read,
1095 .write = mptsas_mmio_write,
1096 .endianness = DEVICE_LITTLE_ENDIAN,
1097 .impl = {
1098 .min_access_size = 4,
1099 .max_access_size = 4,
1100 }
1101};
1102
1103static uint64_t mptsas_diag_read(void *opaque, hwaddr addr,
1104 unsigned size)
1105{
1106 MPTSASState *s = opaque;
1107 trace_mptsas_diag_read(s, addr, 0);
1108 return 0;
1109}
1110
1111static void mptsas_diag_write(void *opaque, hwaddr addr,
1112 uint64_t val, unsigned size)
1113{
1114 MPTSASState *s = opaque;
1115 trace_mptsas_diag_write(s, addr, val);
1116}
1117
1118static const MemoryRegionOps mptsas_diag_ops = {
1119 .read = mptsas_diag_read,
1120 .write = mptsas_diag_write,
1121 .endianness = DEVICE_LITTLE_ENDIAN,
1122 .impl = {
1123 .min_access_size = 4,
1124 .max_access_size = 4,
1125 }
1126};
1127
1128static QEMUSGList *mptsas_get_sg_list(SCSIRequest *sreq)
1129{
1130 MPTSASRequest *req = sreq->hba_private;
1131
1132 return &req->qsg;
1133}
1134
1135static void mptsas_command_complete(SCSIRequest *sreq,
1136 uint32_t status, size_t resid)
1137{
1138 MPTSASRequest *req = sreq->hba_private;
1139 MPTSASState *s = req->dev;
1140 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
1141 uint8_t sense_len;
1142
1143 hwaddr sense_buffer_addr = req->dev->sense_buffer_high_addr |
1144 req->scsi_io.SenseBufferLowAddr;
1145
1146 trace_mptsas_command_complete(s, req->scsi_io.MsgContext, status, resid);
1147
1148 sense_len = scsi_req_get_sense(sreq, sense_buf, SCSI_SENSE_BUF_SIZE);
1149 if (sense_len > 0) {
1150 pci_dma_write(PCI_DEVICE(s), sense_buffer_addr, sense_buf,
1151 MIN(req->scsi_io.SenseBufferLength, sense_len));
1152 }
1153
1154 if (sreq->status != GOOD || resid ||
1155 req->dev->doorbell_state == DOORBELL_WRITE) {
1156 MPIMsgSCSIIOReply reply;
1157
1158 memset(&reply, 0, sizeof(reply));
1159 reply.TargetID = req->scsi_io.TargetID;
1160 reply.Bus = req->scsi_io.Bus;
1161 reply.MsgLength = sizeof(reply) / 4;
1162 reply.Function = req->scsi_io.Function;
1163 reply.CDBLength = req->scsi_io.CDBLength;
1164 reply.SenseBufferLength = req->scsi_io.SenseBufferLength;
1165 reply.MsgFlags = req->scsi_io.MsgFlags;
1166 reply.MsgContext = req->scsi_io.MsgContext;
1167 reply.SCSIStatus = sreq->status;
1168 if (sreq->status == GOOD) {
1169 reply.TransferCount = req->scsi_io.DataLength - resid;
1170 if (resid) {
1171 reply.IOCStatus = MPI_IOCSTATUS_SCSI_DATA_UNDERRUN;
1172 }
1173 } else {
1174 reply.SCSIState = MPI_SCSI_STATE_AUTOSENSE_VALID;
1175 reply.SenseCount = sense_len;
1176 reply.IOCStatus = MPI_IOCSTATUS_SCSI_DATA_UNDERRUN;
1177 }
1178
1179 mptsas_fix_scsi_io_reply_endianness(&reply);
1180 mptsas_post_reply(req->dev, (MPIDefaultReply *)&reply);
1181 } else {
1182 mptsas_turbo_reply(req->dev, req->scsi_io.MsgContext);
1183 }
1184
1185 mptsas_free_request(req);
1186}
1187
1188static void mptsas_request_cancelled(SCSIRequest *sreq)
1189{
1190 MPTSASRequest *req = sreq->hba_private;
1191 MPIMsgSCSIIOReply reply;
1192
1193 memset(&reply, 0, sizeof(reply));
1194 reply.TargetID = req->scsi_io.TargetID;
1195 reply.Bus = req->scsi_io.Bus;
1196 reply.MsgLength = sizeof(reply) / 4;
1197 reply.Function = req->scsi_io.Function;
1198 reply.CDBLength = req->scsi_io.CDBLength;
1199 reply.SenseBufferLength = req->scsi_io.SenseBufferLength;
1200 reply.MsgFlags = req->scsi_io.MsgFlags;
1201 reply.MsgContext = req->scsi_io.MsgContext;
1202 reply.SCSIState = MPI_SCSI_STATE_NO_SCSI_STATUS;
1203 reply.IOCStatus = MPI_IOCSTATUS_SCSI_TASK_TERMINATED;
1204
1205 mptsas_fix_scsi_io_reply_endianness(&reply);
1206 mptsas_post_reply(req->dev, (MPIDefaultReply *)&reply);
1207 mptsas_free_request(req);
1208}
1209
1210static void mptsas_save_request(QEMUFile *f, SCSIRequest *sreq)
1211{
1212 MPTSASRequest *req = sreq->hba_private;
1213 int i;
1214
1215 qemu_put_buffer(f, (unsigned char *)&req->scsi_io, sizeof(req->scsi_io));
1216 qemu_put_be32(f, req->qsg.nsg);
1217 for (i = 0; i < req->qsg.nsg; i++) {
1218 qemu_put_be64(f, req->qsg.sg[i].base);
1219 qemu_put_be64(f, req->qsg.sg[i].len);
1220 }
1221}
1222
1223static void *mptsas_load_request(QEMUFile *f, SCSIRequest *sreq)
1224{
1225 SCSIBus *bus = sreq->bus;
1226 MPTSASState *s = container_of(bus, MPTSASState, bus);
1227 PCIDevice *pci = PCI_DEVICE(s);
1228 MPTSASRequest *req;
1229 int i, n;
1230
1231 req = g_new(MPTSASRequest, 1);
1232 qemu_get_buffer(f, (unsigned char *)&req->scsi_io, sizeof(req->scsi_io));
1233
1234 n = qemu_get_be32(f);
1235
1236
1237
1238
1239
1240 assert(n >= 0);
1241
1242 pci_dma_sglist_init(&req->qsg, pci, n);
1243 for (i = 0; i < n; i++) {
1244 uint64_t base = qemu_get_be64(f);
1245 uint64_t len = qemu_get_be64(f);
1246 qemu_sglist_add(&req->qsg, base, len);
1247 }
1248
1249 scsi_req_ref(sreq);
1250 req->sreq = sreq;
1251 req->dev = s;
1252
1253 return req;
1254}
1255
1256static const struct SCSIBusInfo mptsas_scsi_info = {
1257 .tcq = true,
1258 .max_target = MPTSAS_NUM_PORTS,
1259 .max_lun = 1,
1260
1261 .get_sg_list = mptsas_get_sg_list,
1262 .complete = mptsas_command_complete,
1263 .cancel = mptsas_request_cancelled,
1264 .save_request = mptsas_save_request,
1265 .load_request = mptsas_load_request,
1266};
1267
1268static void mptsas_scsi_realize(PCIDevice *dev, Error **errp)
1269{
1270 MPTSASState *s = MPT_SAS(dev);
1271 Error *err = NULL;
1272 int ret;
1273
1274 dev->config[PCI_LATENCY_TIMER] = 0;
1275 dev->config[PCI_INTERRUPT_PIN] = 0x01;
1276
1277 if (s->msi != ON_OFF_AUTO_OFF) {
1278 ret = msi_init(dev, 0, 1, true, false, &err);
1279
1280
1281 assert(!ret || ret == -ENOTSUP);
1282 if (ret && s->msi == ON_OFF_AUTO_ON) {
1283
1284 error_append_hint(&err, "You have to use msi=auto (default) or "
1285 "msi=off with this machine type.\n");
1286 error_propagate(errp, err);
1287 return;
1288 }
1289 assert(!err || s->msi == ON_OFF_AUTO_AUTO);
1290
1291 error_free(err);
1292
1293
1294 s->msi_in_use = (ret == 0);
1295 }
1296
1297 memory_region_init_io(&s->mmio_io, OBJECT(s), &mptsas_mmio_ops, s,
1298 "mptsas-mmio", 0x4000);
1299 memory_region_init_io(&s->port_io, OBJECT(s), &mptsas_port_ops, s,
1300 "mptsas-io", 256);
1301 memory_region_init_io(&s->diag_io, OBJECT(s), &mptsas_diag_ops, s,
1302 "mptsas-diag", 0x10000);
1303
1304 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
1305 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY |
1306 PCI_BASE_ADDRESS_MEM_TYPE_32, &s->mmio_io);
1307 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY |
1308 PCI_BASE_ADDRESS_MEM_TYPE_32, &s->diag_io);
1309
1310 if (!s->sas_addr) {
1311 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
1312 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
1313 s->sas_addr |= (pci_dev_bus_num(dev) << 16);
1314 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
1315 s->sas_addr |= PCI_FUNC(dev->devfn);
1316 }
1317 s->max_devices = MPTSAS_NUM_PORTS;
1318
1319 s->request_bh = qemu_bh_new(mptsas_fetch_requests, s);
1320
1321 QTAILQ_INIT(&s->pending);
1322
1323 scsi_bus_new(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info, NULL);
1324}
1325
1326static void mptsas_scsi_uninit(PCIDevice *dev)
1327{
1328 MPTSASState *s = MPT_SAS(dev);
1329
1330 qemu_bh_delete(s->request_bh);
1331 msi_uninit(dev);
1332}
1333
1334static void mptsas_reset(DeviceState *dev)
1335{
1336 MPTSASState *s = MPT_SAS(dev);
1337
1338 mptsas_hard_reset(s);
1339}
1340
1341static int mptsas_post_load(void *opaque, int version_id)
1342{
1343 MPTSASState *s = opaque;
1344
1345 if (s->doorbell_idx > s->doorbell_cnt ||
1346 s->doorbell_cnt > ARRAY_SIZE(s->doorbell_msg) ||
1347 s->doorbell_reply_idx > s->doorbell_reply_size ||
1348 s->doorbell_reply_size > ARRAY_SIZE(s->doorbell_reply) ||
1349 MPTSAS_FIFO_INVALID(s, request_post) ||
1350 MPTSAS_FIFO_INVALID(s, reply_post) ||
1351 MPTSAS_FIFO_INVALID(s, reply_free) ||
1352 s->diagnostic_idx > 4) {
1353 return -EINVAL;
1354 }
1355
1356 return 0;
1357}
1358
1359static const VMStateDescription vmstate_mptsas = {
1360 .name = "mptsas",
1361 .version_id = 0,
1362 .minimum_version_id = 0,
1363 .minimum_version_id_old = 0,
1364 .post_load = mptsas_post_load,
1365 .fields = (VMStateField[]) {
1366 VMSTATE_PCI_DEVICE(dev, MPTSASState),
1367 VMSTATE_BOOL(msi_in_use, MPTSASState),
1368 VMSTATE_UINT32(state, MPTSASState),
1369 VMSTATE_UINT8(who_init, MPTSASState),
1370 VMSTATE_UINT8(doorbell_state, MPTSASState),
1371 VMSTATE_UINT32_ARRAY(doorbell_msg, MPTSASState, 256),
1372 VMSTATE_INT32(doorbell_idx, MPTSASState),
1373 VMSTATE_INT32(doorbell_cnt, MPTSASState),
1374
1375 VMSTATE_UINT16_ARRAY(doorbell_reply, MPTSASState, 256),
1376 VMSTATE_INT32(doorbell_reply_idx, MPTSASState),
1377 VMSTATE_INT32(doorbell_reply_size, MPTSASState),
1378
1379 VMSTATE_UINT32(diagnostic, MPTSASState),
1380 VMSTATE_UINT8(diagnostic_idx, MPTSASState),
1381
1382 VMSTATE_UINT32(intr_status, MPTSASState),
1383 VMSTATE_UINT32(intr_mask, MPTSASState),
1384
1385 VMSTATE_UINT32_ARRAY(request_post, MPTSASState,
1386 MPTSAS_REQUEST_QUEUE_DEPTH + 1),
1387 VMSTATE_UINT16(request_post_head, MPTSASState),
1388 VMSTATE_UINT16(request_post_tail, MPTSASState),
1389
1390 VMSTATE_UINT32_ARRAY(reply_post, MPTSASState,
1391 MPTSAS_REPLY_QUEUE_DEPTH + 1),
1392 VMSTATE_UINT16(reply_post_head, MPTSASState),
1393 VMSTATE_UINT16(reply_post_tail, MPTSASState),
1394
1395 VMSTATE_UINT32_ARRAY(reply_free, MPTSASState,
1396 MPTSAS_REPLY_QUEUE_DEPTH + 1),
1397 VMSTATE_UINT16(reply_free_head, MPTSASState),
1398 VMSTATE_UINT16(reply_free_tail, MPTSASState),
1399
1400 VMSTATE_UINT16(max_buses, MPTSASState),
1401 VMSTATE_UINT16(max_devices, MPTSASState),
1402 VMSTATE_UINT16(reply_frame_size, MPTSASState),
1403 VMSTATE_UINT64(host_mfa_high_addr, MPTSASState),
1404 VMSTATE_UINT64(sense_buffer_high_addr, MPTSASState),
1405 VMSTATE_END_OF_LIST()
1406 }
1407};
1408
1409static Property mptsas_properties[] = {
1410 DEFINE_PROP_UINT64("sas_address", MPTSASState, sas_addr, 0),
1411
1412 DEFINE_PROP_ON_OFF_AUTO("msi", MPTSASState, msi, ON_OFF_AUTO_AUTO),
1413 DEFINE_PROP_END_OF_LIST(),
1414};
1415
1416static void mptsas1068_class_init(ObjectClass *oc, void *data)
1417{
1418 DeviceClass *dc = DEVICE_CLASS(oc);
1419 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
1420
1421 pc->realize = mptsas_scsi_realize;
1422 pc->exit = mptsas_scsi_uninit;
1423 pc->romfile = 0;
1424 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
1425 pc->device_id = PCI_DEVICE_ID_LSI_SAS1068;
1426 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
1427 pc->subsystem_id = 0x8000;
1428 pc->class_id = PCI_CLASS_STORAGE_SCSI;
1429 device_class_set_props(dc, mptsas_properties);
1430 dc->reset = mptsas_reset;
1431 dc->vmsd = &vmstate_mptsas;
1432 dc->desc = "LSI SAS 1068";
1433 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1434}
1435
1436static const TypeInfo mptsas_info = {
1437 .name = TYPE_MPTSAS1068,
1438 .parent = TYPE_PCI_DEVICE,
1439 .instance_size = sizeof(MPTSASState),
1440 .class_init = mptsas1068_class_init,
1441 .interfaces = (InterfaceInfo[]) {
1442 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1443 { },
1444 },
1445};
1446
1447static void mptsas_register_types(void)
1448{
1449 type_register(&mptsas_info);
1450}
1451
1452type_init(mptsas_register_types)
1453
