1/* 2 * bcm2708 aka bcm2835/2836 aka Raspberry Pi/Pi2 SoC platform defines 3 * 4 * These definitions are derived from those in Raspbian Linux at 5 * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h 6 * where they carry the following notice: 7 * 8 * Copyright (C) 2010 Broadcom 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 * Various undocumented addresses and names come from Herman Hermitage's VC4 25 * documentation: 26 * https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map 27 */ 28 29#ifndef HW_ARM_RASPI_PLATFORM_H 30#define HW_ARM_RASPI_PLATFORM_H 31 32#define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */ 33#define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */ 34#define INTE_OFFSET 0x2000 /* VC Interrupt controller */ 35#define ST_OFFSET 0x3000 /* System Timer */ 36#define TXP_OFFSET 0x4000 /* Transposer */ 37#define JPEG_OFFSET 0x5000 38#define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */ 39#define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */ 40#define ARBA_OFFSET 0x9000 41#define BRDG_OFFSET 0xa000 42#define ARM_OFFSET 0xB000 /* ARM control block */ 43#define ARMCTRL_OFFSET (ARM_OFFSET + 0x000) 44#define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */ 45#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */ 46#define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores 47 * Doorbells & Mailboxes */ 48#define PM_OFFSET 0x100000 /* Power Management */ 49#define CPRMAN_OFFSET 0x101000 /* Clock Management */ 50#define AVS_OFFSET 0x103000 /* Audio Video Standard */ 51#define RNG_OFFSET 0x104000 52#define GPIO_OFFSET 0x200000 53#define UART0_OFFSET 0x201000 /* PL011 */ 54#define MMCI0_OFFSET 0x202000 /* Legacy MMC */ 55#define I2S_OFFSET 0x203000 /* PCM */ 56#define SPI0_OFFSET 0x204000 /* SPI master */ 57#define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ 58#define PIXV0_OFFSET 0x206000 59#define PIXV1_OFFSET 0x207000 60#define DPI_OFFSET 0x208000 61#define DSI0_OFFSET 0x209000 /* Display Serial Interface */ 62#define PWM_OFFSET 0x20c000 63#define PERM_OFFSET 0x20d000 64#define TEC_OFFSET 0x20e000 65#define OTP_OFFSET 0x20f000 66#define SLIM_OFFSET 0x210000 /* SLIMbus */ 67#define CPG_OFFSET 0x211000 68#define THERMAL_OFFSET 0x212000 69#define AVSP_OFFSET 0x213000 70#define BSC_SL_OFFSET 0x214000 /* SPI slave (bootrom) */ 71#define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */ 72#define EMMC1_OFFSET 0x300000 73#define EMMC2_OFFSET 0x340000 74#define HVS_OFFSET 0x400000 75#define SMI_OFFSET 0x600000 76#define DSI1_OFFSET 0x700000 77#define UCAM_OFFSET 0x800000 78#define CMI_OFFSET 0x802000 79#define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */ 80#define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */ 81#define VECA_OFFSET 0x806000 82#define PIXV2_OFFSET 0x807000 83#define HDMI_OFFSET 0x808000 84#define HDCP_OFFSET 0x809000 85#define ARBR0_OFFSET 0x80a000 86#define DBUS_OFFSET 0x900000 87#define AVE0_OFFSET 0x910000 88#define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */ 89#define V3D_OFFSET 0xc00000 90#define SDRAMC_OFFSET 0xe00000 91#define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */ 92#define L1CC_OFFSET 0xe02000 /* Level 1 Cache controller */ 93#define ARBR1_OFFSET 0xe04000 94#define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */ 95#define DCRC_OFFSET 0xe07000 96#define AXIP_OFFSET 0xe08000 97 98/* GPU interrupts */ 99#define INTERRUPT_TIMER0 0 100#define INTERRUPT_TIMER1 1 101#define INTERRUPT_TIMER2 2 102#define INTERRUPT_TIMER3 3 103#define INTERRUPT_CODEC0 4 104#define INTERRUPT_CODEC1 5 105#define INTERRUPT_CODEC2 6 106#define INTERRUPT_JPEG 7 107#define INTERRUPT_ISP 8 108#define INTERRUPT_USB 9 109#define INTERRUPT_3D 10 110#define INTERRUPT_TRANSPOSER 11 111#define INTERRUPT_MULTICORESYNC0 12 112#define INTERRUPT_MULTICORESYNC1 13 113#define INTERRUPT_MULTICORESYNC2 14 114#define INTERRUPT_MULTICORESYNC3 15 115#define INTERRUPT_DMA0 16 116#define INTERRUPT_DMA1 17 117#define INTERRUPT_DMA2 18 118#define INTERRUPT_DMA3 19 119#define INTERRUPT_DMA4 20 120#define INTERRUPT_DMA5 21 121#define INTERRUPT_DMA6 22 122#define INTERRUPT_DMA7 23 123#define INTERRUPT_DMA8 24 124#define INTERRUPT_DMA9 25 125#define INTERRUPT_DMA10 26 126#define INTERRUPT_DMA11 27 127#define INTERRUPT_DMA12 28 128#define INTERRUPT_AUX 29 129#define INTERRUPT_ARM 30 130#define INTERRUPT_VPUDMA 31 131#define INTERRUPT_HOSTPORT 32 132#define INTERRUPT_VIDEOSCALER 33 133#define INTERRUPT_CCP2TX 34 134#define INTERRUPT_SDC 35 135#define INTERRUPT_DSI0 36 136#define INTERRUPT_AVE 37 137#define INTERRUPT_CAM0 38 138#define INTERRUPT_CAM1 39 139#define INTERRUPT_HDMI0 40 140#define INTERRUPT_HDMI1 41 141#define INTERRUPT_PIXELVALVE1 42 142#define INTERRUPT_I2CSPISLV 43 143#define INTERRUPT_DSI1 44 144#define INTERRUPT_PWA0 45 145#define INTERRUPT_PWA1 46 146#define INTERRUPT_CPR 47 147#define INTERRUPT_SMI 48 148#define INTERRUPT_GPIO0 49 149#define INTERRUPT_GPIO1 50 150#define INTERRUPT_GPIO2 51 151#define INTERRUPT_GPIO3 52 152#define INTERRUPT_I2C 53 153#define INTERRUPT_SPI 54 154#define INTERRUPT_I2SPCM 55 155#define INTERRUPT_SDIO 56 156#define INTERRUPT_UART0 57 157#define INTERRUPT_SLIMBUS 58 158#define INTERRUPT_VEC 59 159#define INTERRUPT_CPG 60 160#define INTERRUPT_RNG 61 161#define INTERRUPT_ARASANSDIO 62 162#define INTERRUPT_AVSPMON 63 163 164/* ARM CPU IRQs use a private number space */ 165#define INTERRUPT_ARM_TIMER 0 166#define INTERRUPT_ARM_MAILBOX 1 167#define INTERRUPT_ARM_DOORBELL_0 2 168#define INTERRUPT_ARM_DOORBELL_1 3 169#define INTERRUPT_VPU0_HALTED 4 170#define INTERRUPT_VPU1_HALTED 5 171#define INTERRUPT_ILLEGAL_TYPE0 6 172#define INTERRUPT_ILLEGAL_TYPE1 7 173 174#endif 175