LXR qemu/include/hw/riscv/microchip

   1/*
   2 * Microchip PolarFire SoC machine interface
   3 *
   4 * Copyright (c) 2020 Wind River Systems, Inc.
   5 *
   6 * Author:
   7 *   Bin Meng <bin.meng@windriver.com>
   8 *
   9 * This program is free software; you can redistribute it and/or modify it
  10 * under the terms and conditions of the GNU General Public License,
  11 * version 2 or later, as published by the Free Software Foundation.
  12 *
  13 * This program is distributed in the hope it will be useful, but WITHOUT
  14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16 * more details.
  17 *
  18 * You should have received a copy of the GNU General Public License along with
  19 * this program.  If not, see <http://www.gnu.org/licenses/>.
  20 */
  21
  22#ifndef HW_MICROCHIP_PFSOC_H
  23#define HW_MICROCHIP_PFSOC_H
  24
  25#include "hw/char/mchp_pfsoc_mmuart.h"
  26#include "hw/dma/sifive_pdma.h"
  27#include "hw/misc/mchp_pfsoc_dmc.h"
  28#include "hw/misc/mchp_pfsoc_ioscb.h"
  29#include "hw/misc/mchp_pfsoc_sysreg.h"
  30#include "hw/net/cadence_gem.h"
  31#include "hw/sd/cadence_sdhci.h"
  32
  33typedef struct MicrochipPFSoCState {
  34    /*< private >*/
  35    DeviceState parent_obj;
  36
  37    /*< public >*/
  38    CPUClusterState e_cluster;
  39    CPUClusterState u_cluster;
  40    RISCVHartArrayState e_cpus;
  41    RISCVHartArrayState u_cpus;
  42    DeviceState *plic;
  43    MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
  44    MchpPfSoCDdrCfgState ddr_cfg;
  45    MchpPfSoCIoscbState ioscb;
  46    MchpPfSoCMMUartState *serial0;
  47    MchpPfSoCMMUartState *serial1;
  48    MchpPfSoCMMUartState *serial2;
  49    MchpPfSoCMMUartState *serial3;
  50    MchpPfSoCMMUartState *serial4;
  51    MchpPfSoCSysregState sysreg;
  52    SiFivePDMAState dma;
  53    CadenceGEMState gem0;
  54    CadenceGEMState gem1;
  55    CadenceSDHCIState sdhci;
  56} MicrochipPFSoCState;
  57
  58#define TYPE_MICROCHIP_PFSOC    "microchip.pfsoc"
  59#define MICROCHIP_PFSOC(obj) \
  60    OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)
  61
  62typedef struct MicrochipIcicleKitState {
  63    /*< private >*/
  64    MachineState parent_obj;
  65
  66    /*< public >*/
  67    MicrochipPFSoCState soc;
  68} MicrochipIcicleKitState;
  69
  70#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
  71    MACHINE_TYPE_NAME("microchip-icicle-kit")
  72#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
  73    OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
  74                 TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
  75
  76enum {
  77    MICROCHIP_PFSOC_RSVD0,
  78    MICROCHIP_PFSOC_DEBUG,
  79    MICROCHIP_PFSOC_E51_DTIM,
  80    MICROCHIP_PFSOC_BUSERR_UNIT0,
  81    MICROCHIP_PFSOC_BUSERR_UNIT1,
  82    MICROCHIP_PFSOC_BUSERR_UNIT2,
  83    MICROCHIP_PFSOC_BUSERR_UNIT3,
  84    MICROCHIP_PFSOC_BUSERR_UNIT4,
  85    MICROCHIP_PFSOC_CLINT,
  86    MICROCHIP_PFSOC_L2CC,
  87    MICROCHIP_PFSOC_DMA,
  88    MICROCHIP_PFSOC_L2LIM,
  89    MICROCHIP_PFSOC_PLIC,
  90    MICROCHIP_PFSOC_MMUART0,
  91    MICROCHIP_PFSOC_SYSREG,
  92    MICROCHIP_PFSOC_MPUCFG,
  93    MICROCHIP_PFSOC_DDR_SGMII_PHY,
  94    MICROCHIP_PFSOC_EMMC_SD,
  95    MICROCHIP_PFSOC_DDR_CFG,
  96    MICROCHIP_PFSOC_MMUART1,
  97    MICROCHIP_PFSOC_MMUART2,
  98    MICROCHIP_PFSOC_MMUART3,
  99    MICROCHIP_PFSOC_MMUART4,
 100    MICROCHIP_PFSOC_I2C1,
 101    MICROCHIP_PFSOC_GEM0,
 102    MICROCHIP_PFSOC_GEM1,
 103    MICROCHIP_PFSOC_GPIO0,
 104    MICROCHIP_PFSOC_GPIO1,
 105    MICROCHIP_PFSOC_GPIO2,
 106    MICROCHIP_PFSOC_ENVM_CFG,
 107    MICROCHIP_PFSOC_ENVM_DATA,
 108    MICROCHIP_PFSOC_IOSCB,
 109    MICROCHIP_PFSOC_DRAM_LO,
 110    MICROCHIP_PFSOC_DRAM_LO_ALIAS,
 111    MICROCHIP_PFSOC_DRAM_HI,
 112    MICROCHIP_PFSOC_DRAM_HI_ALIAS
 113};
 114
 115enum {
 116    MICROCHIP_PFSOC_DMA_IRQ0 = 5,
 117    MICROCHIP_PFSOC_DMA_IRQ1 = 6,
 118    MICROCHIP_PFSOC_DMA_IRQ2 = 7,
 119    MICROCHIP_PFSOC_DMA_IRQ3 = 8,
 120    MICROCHIP_PFSOC_DMA_IRQ4 = 9,
 121    MICROCHIP_PFSOC_DMA_IRQ5 = 10,
 122    MICROCHIP_PFSOC_DMA_IRQ6 = 11,
 123    MICROCHIP_PFSOC_DMA_IRQ7 = 12,
 124    MICROCHIP_PFSOC_GEM0_IRQ = 64,
 125    MICROCHIP_PFSOC_GEM1_IRQ = 70,
 126    MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
 127    MICROCHIP_PFSOC_MMUART0_IRQ = 90,
 128    MICROCHIP_PFSOC_MMUART1_IRQ = 91,
 129    MICROCHIP_PFSOC_MMUART2_IRQ = 92,
 130    MICROCHIP_PFSOC_MMUART3_IRQ = 93,
 131    MICROCHIP_PFSOC_MMUART4_IRQ = 94,
 132};
 133
 134#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT    1
 135#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT       4
 136
 137#define MICROCHIP_PFSOC_PLIC_HART_CONFIG        "MS"
 138#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES        185
 139#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES     7
 140#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE      0x04
 141#define MICROCHIP_PFSOC_PLIC_PENDING_BASE       0x1000
 142#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE        0x2000
 143#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE      0x80
 144#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE       0x200000
 145#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE     0x1000
 146
 147#endif /* HW_MICROCHIP_PFSOC_H */
 148