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23#include "qemu/osdep.h"
24#include "qemu/main-loop.h"
25#include "cpu.h"
26#include "internal.h"
27#include "qemu/host-utils.h"
28#include "exec/helper-proto.h"
29#include "exec/exec-all.h"
30#include "exec/cpu_ldst.h"
31#include "exec/memop.h"
32#include "sysemu/kvm.h"
33
34
35#ifndef CONFIG_USER_ONLY
36
37static bool mips_vpe_is_wfi(MIPSCPU *c)
38{
39 CPUState *cpu = CPU(c);
40 CPUMIPSState *env = &c->env;
41
42
43
44
45
46 return cpu->halted && mips_vpe_active(env);
47}
48
49static bool mips_vp_is_wfi(MIPSCPU *c)
50{
51 CPUState *cpu = CPU(c);
52 CPUMIPSState *env = &c->env;
53
54 return cpu->halted && mips_vp_active(env);
55}
56
57static inline void mips_vpe_wake(MIPSCPU *c)
58{
59
60
61
62
63
64 qemu_mutex_lock_iothread();
65 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
66 qemu_mutex_unlock_iothread();
67}
68
69static inline void mips_vpe_sleep(MIPSCPU *cpu)
70{
71 CPUState *cs = CPU(cpu);
72
73
74
75
76
77 cs->halted = 1;
78 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
79}
80
81static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
82{
83 CPUMIPSState *c = &cpu->env;
84
85
86 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
87 mips_vpe_wake(cpu);
88 }
89}
90
91static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
92{
93 CPUMIPSState *c = &cpu->env;
94
95
96 if (!mips_vpe_active(c)) {
97 mips_vpe_sleep(cpu);
98 }
99}
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
116{
117 MIPSCPU *cpu;
118 CPUState *cs;
119 CPUState *other_cs;
120 int vpe_idx;
121 int tc_idx = *tc;
122
123 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
124
125 *tc = env->current_tc;
126 return env;
127 }
128
129 cs = env_cpu(env);
130 vpe_idx = tc_idx / cs->nr_threads;
131 *tc = tc_idx % cs->nr_threads;
132 other_cs = qemu_get_cpu(vpe_idx);
133 if (other_cs == NULL) {
134 return env;
135 }
136 cpu = MIPS_CPU(other_cs);
137 return &cpu->env;
138}
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
158 target_ulong v)
159{
160 uint32_t status;
161 uint32_t tcu, tmx, tasid, tksu;
162 uint32_t mask = ((1U << CP0St_CU3)
163 | (1 << CP0St_CU2)
164 | (1 << CP0St_CU1)
165 | (1 << CP0St_CU0)
166 | (1 << CP0St_MX)
167 | (3 << CP0St_KSU));
168
169 tcu = (v >> CP0TCSt_TCU0) & 0xf;
170 tmx = (v >> CP0TCSt_TMX) & 0x1;
171 tasid = v & cpu->CP0_EntryHi_ASID_mask;
172 tksu = (v >> CP0TCSt_TKSU) & 0x3;
173
174 status = tcu << CP0St_CU0;
175 status |= tmx << CP0St_MX;
176 status |= tksu << CP0St_KSU;
177
178 cpu->CP0_Status &= ~mask;
179 cpu->CP0_Status |= status;
180
181
182 cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask;
183 cpu->CP0_EntryHi |= tasid;
184
185 compute_hflags(cpu);
186}
187
188
189static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
190{
191 int32_t *tcst;
192 uint32_t asid, v = cpu->CP0_EntryHi;
193
194 asid = v & cpu->CP0_EntryHi_ASID_mask;
195
196 if (tc == cpu->current_tc) {
197 tcst = &cpu->active_tc.CP0_TCStatus;
198 } else {
199 tcst = &cpu->tcs[tc].CP0_TCStatus;
200 }
201
202 *tcst &= ~cpu->CP0_EntryHi_ASID_mask;
203 *tcst |= asid;
204}
205
206
207uint32_t cpu_mips_get_random(CPUMIPSState *env)
208{
209 static uint32_t seed = 1;
210 static uint32_t prev_idx;
211 uint32_t idx;
212 uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired;
213
214 if (nb_rand_tlb == 1) {
215 return env->tlb->nb_tlb - 1;
216 }
217
218
219 do {
220
221
222
223
224 seed = 1103515245 * seed + 12345;
225 idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired;
226 } while (idx == prev_idx);
227 prev_idx = idx;
228 return idx;
229}
230
231
232target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
233{
234 return env->mvp->CP0_MVPControl;
235}
236
237target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
238{
239 return env->mvp->CP0_MVPConf0;
240}
241
242target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
243{
244 return env->mvp->CP0_MVPConf1;
245}
246
247target_ulong helper_mfc0_random(CPUMIPSState *env)
248{
249 return (int32_t)cpu_mips_get_random(env);
250}
251
252target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
253{
254 return env->active_tc.CP0_TCStatus;
255}
256
257target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
258{
259 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
260 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
261
262 if (other_tc == other->current_tc) {
263 return other->active_tc.CP0_TCStatus;
264 } else {
265 return other->tcs[other_tc].CP0_TCStatus;
266 }
267}
268
269target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
270{
271 return env->active_tc.CP0_TCBind;
272}
273
274target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
275{
276 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
277 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
278
279 if (other_tc == other->current_tc) {
280 return other->active_tc.CP0_TCBind;
281 } else {
282 return other->tcs[other_tc].CP0_TCBind;
283 }
284}
285
286target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
287{
288 return env->active_tc.PC;
289}
290
291target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
292{
293 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
294 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
295
296 if (other_tc == other->current_tc) {
297 return other->active_tc.PC;
298 } else {
299 return other->tcs[other_tc].PC;
300 }
301}
302
303target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
304{
305 return env->active_tc.CP0_TCHalt;
306}
307
308target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
309{
310 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
311 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
312
313 if (other_tc == other->current_tc) {
314 return other->active_tc.CP0_TCHalt;
315 } else {
316 return other->tcs[other_tc].CP0_TCHalt;
317 }
318}
319
320target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
321{
322 return env->active_tc.CP0_TCContext;
323}
324
325target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
326{
327 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
328 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
329
330 if (other_tc == other->current_tc) {
331 return other->active_tc.CP0_TCContext;
332 } else {
333 return other->tcs[other_tc].CP0_TCContext;
334 }
335}
336
337target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
338{
339 return env->active_tc.CP0_TCSchedule;
340}
341
342target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
343{
344 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
345 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
346
347 if (other_tc == other->current_tc) {
348 return other->active_tc.CP0_TCSchedule;
349 } else {
350 return other->tcs[other_tc].CP0_TCSchedule;
351 }
352}
353
354target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
355{
356 return env->active_tc.CP0_TCScheFBack;
357}
358
359target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
360{
361 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
362 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
363
364 if (other_tc == other->current_tc) {
365 return other->active_tc.CP0_TCScheFBack;
366 } else {
367 return other->tcs[other_tc].CP0_TCScheFBack;
368 }
369}
370
371target_ulong helper_mfc0_count(CPUMIPSState *env)
372{
373 return (int32_t)cpu_mips_get_count(env);
374}
375
376target_ulong helper_mfc0_saar(CPUMIPSState *env)
377{
378 if ((env->CP0_SAARI & 0x3f) < 2) {
379 return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f];
380 }
381 return 0;
382}
383
384target_ulong helper_mfhc0_saar(CPUMIPSState *env)
385{
386 if ((env->CP0_SAARI & 0x3f) < 2) {
387 return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32;
388 }
389 return 0;
390}
391
392target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
393{
394 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
395 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
396
397 return other->CP0_EntryHi;
398}
399
400target_ulong helper_mftc0_cause(CPUMIPSState *env)
401{
402 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
403 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
404
405 return other->CP0_Cause;
406}
407
408target_ulong helper_mftc0_status(CPUMIPSState *env)
409{
410 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
411 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
412
413 return other->CP0_Status;
414}
415
416target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
417{
418 return (int32_t)(env->CP0_LLAddr >> env->CP0_LLAddr_shift);
419}
420
421target_ulong helper_mfc0_maar(CPUMIPSState *env)
422{
423 return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
424}
425
426target_ulong helper_mfhc0_maar(CPUMIPSState *env)
427{
428 return env->CP0_MAAR[env->CP0_MAARI] >> 32;
429}
430
431target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
432{
433 return (int32_t)env->CP0_WatchLo[sel];
434}
435
436target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
437{
438 return (int32_t) env->CP0_WatchHi[sel];
439}
440
441target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel)
442{
443 return env->CP0_WatchHi[sel] >> 32;
444}
445
446target_ulong helper_mfc0_debug(CPUMIPSState *env)
447{
448 target_ulong t0 = env->CP0_Debug;
449 if (env->hflags & MIPS_HFLAG_DM) {
450 t0 |= 1 << CP0DB_DM;
451 }
452
453 return t0;
454}
455
456target_ulong helper_mftc0_debug(CPUMIPSState *env)
457{
458 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
459 int32_t tcstatus;
460 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
461
462 if (other_tc == other->current_tc) {
463 tcstatus = other->active_tc.CP0_Debug_tcstatus;
464 } else {
465 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
466 }
467
468
469 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
470 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
471}
472
473#if defined(TARGET_MIPS64)
474target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
475{
476 return env->active_tc.PC;
477}
478
479target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
480{
481 return env->active_tc.CP0_TCHalt;
482}
483
484target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
485{
486 return env->active_tc.CP0_TCContext;
487}
488
489target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
490{
491 return env->active_tc.CP0_TCSchedule;
492}
493
494target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
495{
496 return env->active_tc.CP0_TCScheFBack;
497}
498
499target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
500{
501 return env->CP0_LLAddr >> env->CP0_LLAddr_shift;
502}
503
504target_ulong helper_dmfc0_maar(CPUMIPSState *env)
505{
506 return env->CP0_MAAR[env->CP0_MAARI];
507}
508
509target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
510{
511 return env->CP0_WatchLo[sel];
512}
513
514target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel)
515{
516 return env->CP0_WatchHi[sel];
517}
518
519target_ulong helper_dmfc0_saar(CPUMIPSState *env)
520{
521 if ((env->CP0_SAARI & 0x3f) < 2) {
522 return env->CP0_SAAR[env->CP0_SAARI & 0x3f];
523 }
524 return 0;
525}
526#endif
527
528void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
529{
530 uint32_t index_p = env->CP0_Index & 0x80000000;
531 uint32_t tlb_index = arg1 & 0x7fffffff;
532 if (tlb_index < env->tlb->nb_tlb) {
533 if (env->insn_flags & ISA_MIPS32R6) {
534 index_p |= arg1 & 0x80000000;
535 }
536 env->CP0_Index = index_p | tlb_index;
537 }
538}
539
540void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
541{
542 uint32_t mask = 0;
543 uint32_t newval;
544
545 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
546 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
547 (1 << CP0MVPCo_EVP);
548 }
549 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
550 mask |= (1 << CP0MVPCo_STLB);
551 }
552 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
553
554
555
556 env->mvp->CP0_MVPControl = newval;
557}
558
559void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
560{
561 uint32_t mask;
562 uint32_t newval;
563
564 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
565 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
566 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
567
568
569
570
571
572
573
574
575 env->CP0_VPEControl = newval;
576}
577
578void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
579{
580 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
581 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
582 uint32_t mask;
583 uint32_t newval;
584
585 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
586 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
587 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
588
589
590
591 other->CP0_VPEControl = newval;
592}
593
594target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
595{
596 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
597 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
598
599 return other->CP0_VPEControl;
600}
601
602target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
603{
604 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
605 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
606
607 return other->CP0_VPEConf0;
608}
609
610void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
611{
612 uint32_t mask = 0;
613 uint32_t newval;
614
615 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
616 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) {
617 mask |= (0xff << CP0VPEC0_XTC);
618 }
619 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
620 }
621 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
622
623
624
625 env->CP0_VPEConf0 = newval;
626}
627
628void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
629{
630 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
631 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
632 uint32_t mask = 0;
633 uint32_t newval;
634
635 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
636 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
637
638
639 other->CP0_VPEConf0 = newval;
640}
641
642void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
643{
644 uint32_t mask = 0;
645 uint32_t newval;
646
647 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
648 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
649 (0xff << CP0VPEC1_NCP1);
650 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
651
652
653
654
655
656
657 env->CP0_VPEConf1 = newval;
658}
659
660void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
661{
662
663 env->CP0_YQMask = 0x00000000;
664}
665
666void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
667{
668 env->CP0_VPEOpt = arg1 & 0x0000ffff;
669}
670
671#define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
672
673void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
674{
675
676 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
677 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
678 | (rxi << (CP0EnLo_XI - 30));
679}
680
681#if defined(TARGET_MIPS64)
682#define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
683
684void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
685{
686 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
687 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
688}
689#endif
690
691void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
692{
693 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
694 uint32_t newval;
695
696 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
697
698 env->active_tc.CP0_TCStatus = newval;
699 sync_c0_tcstatus(env, env->current_tc, newval);
700}
701
702void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
703{
704 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
705 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
706
707 if (other_tc == other->current_tc) {
708 other->active_tc.CP0_TCStatus = arg1;
709 } else {
710 other->tcs[other_tc].CP0_TCStatus = arg1;
711 }
712 sync_c0_tcstatus(other, other_tc, arg1);
713}
714
715void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
716{
717 uint32_t mask = (1 << CP0TCBd_TBE);
718 uint32_t newval;
719
720 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
721 mask |= (1 << CP0TCBd_CurVPE);
722 }
723 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
724 env->active_tc.CP0_TCBind = newval;
725}
726
727void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
728{
729 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
730 uint32_t mask = (1 << CP0TCBd_TBE);
731 uint32_t newval;
732 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
733
734 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
735 mask |= (1 << CP0TCBd_CurVPE);
736 }
737 if (other_tc == other->current_tc) {
738 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
739 other->active_tc.CP0_TCBind = newval;
740 } else {
741 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
742 other->tcs[other_tc].CP0_TCBind = newval;
743 }
744}
745
746void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
747{
748 env->active_tc.PC = arg1;
749 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
750 env->CP0_LLAddr = 0;
751 env->lladdr = 0;
752
753}
754
755void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
756{
757 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
758 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
759
760 if (other_tc == other->current_tc) {
761 other->active_tc.PC = arg1;
762 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
763 other->CP0_LLAddr = 0;
764 other->lladdr = 0;
765
766 } else {
767 other->tcs[other_tc].PC = arg1;
768 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
769 other->CP0_LLAddr = 0;
770 other->lladdr = 0;
771
772 }
773}
774
775void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
776{
777 MIPSCPU *cpu = env_archcpu(env);
778
779 env->active_tc.CP0_TCHalt = arg1 & 0x1;
780
781
782 if (env->active_tc.CP0_TCHalt & 1) {
783 mips_tc_sleep(cpu, env->current_tc);
784 } else {
785 mips_tc_wake(cpu, env->current_tc);
786 }
787}
788
789void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
790{
791 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
792 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
793 MIPSCPU *other_cpu = env_archcpu(other);
794
795
796
797 if (other_tc == other->current_tc) {
798 other->active_tc.CP0_TCHalt = arg1;
799 } else {
800 other->tcs[other_tc].CP0_TCHalt = arg1;
801 }
802
803 if (arg1 & 1) {
804 mips_tc_sleep(other_cpu, other_tc);
805 } else {
806 mips_tc_wake(other_cpu, other_tc);
807 }
808}
809
810void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
811{
812 env->active_tc.CP0_TCContext = arg1;
813}
814
815void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
816{
817 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
818 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
819
820 if (other_tc == other->current_tc) {
821 other->active_tc.CP0_TCContext = arg1;
822 } else {
823 other->tcs[other_tc].CP0_TCContext = arg1;
824 }
825}
826
827void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
828{
829 env->active_tc.CP0_TCSchedule = arg1;
830}
831
832void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
833{
834 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
835 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
836
837 if (other_tc == other->current_tc) {
838 other->active_tc.CP0_TCSchedule = arg1;
839 } else {
840 other->tcs[other_tc].CP0_TCSchedule = arg1;
841 }
842}
843
844void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
845{
846 env->active_tc.CP0_TCScheFBack = arg1;
847}
848
849void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
850{
851 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
852 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
853
854 if (other_tc == other->current_tc) {
855 other->active_tc.CP0_TCScheFBack = arg1;
856 } else {
857 other->tcs[other_tc].CP0_TCScheFBack = arg1;
858 }
859}
860
861void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
862{
863
864 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
865 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
866 | (rxi << (CP0EnLo_XI - 30));
867}
868
869#if defined(TARGET_MIPS64)
870void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
871{
872 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
873 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
874}
875#endif
876
877void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
878{
879 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
880}
881
882void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1)
883{
884 int32_t old;
885 old = env->CP0_MemoryMapID;
886 env->CP0_MemoryMapID = (int32_t) arg1;
887
888 if (old != env->CP0_MemoryMapID) {
889 cpu_mips_tlb_flush(env);
890 }
891}
892
893void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
894{
895 uint32_t mask;
896 int maskbits;
897
898
899 mask = extract32((uint32_t)arg1, CP0PM_MASK, 16);
900 maskbits = cto32(mask);
901
902
903 if ((mask >> maskbits) != 0) {
904 goto invalid;
905 }
906
907 if ((maskbits + 12) < TARGET_PAGE_BITS) {
908 goto invalid;
909 }
910 env->CP0_PageMask = mask << CP0PM_MASK;
911
912 return;
913
914invalid:
915
916 env->CP0_PageMask = (~TARGET_PAGE_MASK >> 12) << CP0PM_MASK;
917}
918
919void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
920{
921 update_pagemask(env, arg1, &env->CP0_PageMask);
922}
923
924void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
925{
926
927
928 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
929 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
930 compute_hflags(env);
931 restore_pamask(env);
932}
933
934void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1)
935{
936 CPUState *cs = env_cpu(env);
937
938 env->CP0_SegCtl0 = arg1 & CP0SC0_MASK;
939 tlb_flush(cs);
940}
941
942void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1)
943{
944 CPUState *cs = env_cpu(env);
945
946 env->CP0_SegCtl1 = arg1 & CP0SC1_MASK;
947 tlb_flush(cs);
948}
949
950void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1)
951{
952 CPUState *cs = env_cpu(env);
953
954 env->CP0_SegCtl2 = arg1 & CP0SC2_MASK;
955 tlb_flush(cs);
956}
957
958void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
959{
960#if defined(TARGET_MIPS64)
961 uint64_t mask = 0x3F3FFFFFFFULL;
962 uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL;
963 uint32_t new_ptei = (arg1 >> CP0PF_PTEI) & 0x3FULL;
964
965 if ((env->insn_flags & ISA_MIPS32R6)) {
966 if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) {
967 mask &= ~(0x3FULL << CP0PF_BDI);
968 }
969 if (((arg1 >> CP0PF_GDI) & 0x3FULL) < 12) {
970 mask &= ~(0x3FULL << CP0PF_GDI);
971 }
972 if (((arg1 >> CP0PF_UDI) & 0x3FULL) < 12) {
973 mask &= ~(0x3FULL << CP0PF_UDI);
974 }
975 if (((arg1 >> CP0PF_MDI) & 0x3FULL) < 12) {
976 mask &= ~(0x3FULL << CP0PF_MDI);
977 }
978 if (((arg1 >> CP0PF_PTI) & 0x3FULL) < 12) {
979 mask &= ~(0x3FULL << CP0PF_PTI);
980 }
981 }
982 env->CP0_PWField = arg1 & mask;
983
984 if ((new_ptei >= 32) ||
985 ((env->insn_flags & ISA_MIPS32R6) &&
986 (new_ptei == 0 || new_ptei == 1))) {
987 env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) |
988 (old_ptei << CP0PF_PTEI);
989 }
990#else
991 uint32_t mask = 0x3FFFFFFF;
992 uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
993 uint32_t new_ptew = (arg1 >> CP0PF_PTEW) & 0x3F;
994
995 if ((env->insn_flags & ISA_MIPS32R6)) {
996 if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) {
997 mask &= ~(0x3F << CP0PF_GDW);
998 }
999 if (((arg1 >> CP0PF_UDW) & 0x3F) < 12) {
1000 mask &= ~(0x3F << CP0PF_UDW);
1001 }
1002 if (((arg1 >> CP0PF_MDW) & 0x3F) < 12) {
1003 mask &= ~(0x3F << CP0PF_MDW);
1004 }
1005 if (((arg1 >> CP0PF_PTW) & 0x3F) < 12) {
1006 mask &= ~(0x3F << CP0PF_PTW);
1007 }
1008 }
1009 env->CP0_PWField = arg1 & mask;
1010
1011 if ((new_ptew >= 32) ||
1012 ((env->insn_flags & ISA_MIPS32R6) &&
1013 (new_ptew == 0 || new_ptew == 1))) {
1014 env->CP0_PWField = (env->CP0_PWField & ~0x3F) |
1015 (old_ptew << CP0PF_PTEW);
1016 }
1017#endif
1018}
1019
1020void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)
1021{
1022#if defined(TARGET_MIPS64)
1023 env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL;
1024#else
1025 env->CP0_PWSize = arg1 & 0x3FFFFFFF;
1026#endif
1027}
1028
1029void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1030{
1031 if (env->insn_flags & ISA_MIPS32R6) {
1032 if (arg1 < env->tlb->nb_tlb) {
1033 env->CP0_Wired = arg1;
1034 }
1035 } else {
1036 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1037 }
1038}
1039
1040void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1)
1041{
1042#if defined(TARGET_MIPS64)
1043
1044 env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F);
1045#else
1046 env->CP0_PWCtl = (arg1 & 0x800000FF);
1047#endif
1048}
1049
1050void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1051{
1052 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1053}
1054
1055void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1056{
1057 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1058}
1059
1060void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1061{
1062 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1063}
1064
1065void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1066{
1067 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1068}
1069
1070void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1071{
1072 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1073}
1074
1075void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1076{
1077 uint32_t mask = 0x0000000F;
1078
1079 if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1080 (env->insn_flags & ISA_MIPS32R6)) {
1081 mask |= (1 << 4);
1082 }
1083 if (env->insn_flags & ISA_MIPS32R6) {
1084 mask |= (1 << 5);
1085 }
1086 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1087 mask |= (1 << 29);
1088
1089 if (arg1 & (1 << 29)) {
1090 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1091 } else {
1092 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1093 }
1094 }
1095
1096 env->CP0_HWREna = arg1 & mask;
1097}
1098
1099void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1100{
1101 cpu_mips_store_count(env, arg1);
1102}
1103
1104void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1)
1105{
1106 uint32_t target = arg1 & 0x3f;
1107 if (target <= 1) {
1108 env->CP0_SAARI = target;
1109 }
1110}
1111
1112void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
1113{
1114 uint32_t target = env->CP0_SAARI & 0x3f;
1115 if (target < 2) {
1116 env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL;
1117 switch (target) {
1118 case 0:
1119 if (env->itu) {
1120 itc_reconfigure(env->itu);
1121 }
1122 break;
1123 }
1124 }
1125}
1126
1127void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
1128{
1129 uint32_t target = env->CP0_SAARI & 0x3f;
1130 if (target < 2) {
1131 env->CP0_SAAR[target] =
1132 (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) |
1133 (env->CP0_SAAR[target] & 0x00000000ffffffffULL);
1134 switch (target) {
1135 case 0:
1136 if (env->itu) {
1137 itc_reconfigure(env->itu);
1138 }
1139 break;
1140 }
1141 }
1142}
1143
1144void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1145{
1146 target_ulong old, val, mask;
1147 mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
1148 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1149 mask |= 1 << CP0EnHi_EHINV;
1150 }
1151
1152
1153#if defined(TARGET_MIPS64)
1154 if (env->insn_flags & ISA_MIPS32R6) {
1155 int entryhi_r = extract64(arg1, 62, 2);
1156 int config0_at = extract32(env->CP0_Config0, 13, 2);
1157 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1158 if ((entryhi_r == 2) ||
1159 (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1160
1161 mask &= ~(0x3ull << 62);
1162 }
1163 }
1164 mask &= env->SEGMask;
1165#endif
1166 old = env->CP0_EntryHi;
1167 val = (arg1 & mask) | (old & ~mask);
1168 env->CP0_EntryHi = val;
1169 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1170 sync_c0_entryhi(env, env->current_tc);
1171 }
1172
1173 if ((old & env->CP0_EntryHi_ASID_mask) !=
1174 (val & env->CP0_EntryHi_ASID_mask)) {
1175 tlb_flush(env_cpu(env));
1176 }
1177}
1178
1179void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1180{
1181 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1182 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1183
1184 other->CP0_EntryHi = arg1;
1185 sync_c0_entryhi(other, other_tc);
1186}
1187
1188void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1189{
1190 cpu_mips_store_compare(env, arg1);
1191}
1192
1193void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1194{
1195 uint32_t val, old;
1196
1197 old = env->CP0_Status;
1198 cpu_mips_store_status(env, arg1);
1199 val = env->CP0_Status;
1200
1201 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1202 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1203 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1204 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1205 env->CP0_Cause);
1206 switch (cpu_mmu_index(env, false)) {
1207 case 3:
1208 qemu_log(", ERL\n");
1209 break;
1210 case MIPS_HFLAG_UM:
1211 qemu_log(", UM\n");
1212 break;
1213 case MIPS_HFLAG_SM:
1214 qemu_log(", SM\n");
1215 break;
1216 case MIPS_HFLAG_KM:
1217 qemu_log("\n");
1218 break;
1219 default:
1220 cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
1221 break;
1222 }
1223 }
1224}
1225
1226void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1227{
1228 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1229 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1230 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1231
1232 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1233 sync_c0_status(env, other, other_tc);
1234}
1235
1236void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1237{
1238 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1239}
1240
1241void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1242{
1243 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1244 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1245}
1246
1247void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1248{
1249 cpu_mips_store_cause(env, arg1);
1250}
1251
1252void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1253{
1254 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1255 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1256
1257 cpu_mips_store_cause(other, arg1);
1258}
1259
1260target_ulong helper_mftc0_epc(CPUMIPSState *env)
1261{
1262 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1263 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1264
1265 return other->CP0_EPC;
1266}
1267
1268target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1269{
1270 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1271 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1272
1273 return other->CP0_EBase;
1274}
1275
1276void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1277{
1278 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1279 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1280 mask |= ~0x3FFFFFFF;
1281 }
1282 env->CP0_EBase = (env->CP0_EBase & ~mask) | (arg1 & mask);
1283}
1284
1285void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1286{
1287 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1288 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1289 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1290 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1291 mask |= ~0x3FFFFFFF;
1292 }
1293 other->CP0_EBase = (other->CP0_EBase & ~mask) | (arg1 & mask);
1294}
1295
1296target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1297{
1298 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1299 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1300
1301 switch (idx) {
1302 case 0: return other->CP0_Config0;
1303 case 1: return other->CP0_Config1;
1304 case 2: return other->CP0_Config2;
1305 case 3: return other->CP0_Config3;
1306
1307 case 6: return other->CP0_Config6;
1308 case 7: return other->CP0_Config7;
1309 default:
1310 break;
1311 }
1312 return 0;
1313}
1314
1315void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1316{
1317 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1318}
1319
1320void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1321{
1322
1323 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1324}
1325
1326void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1327{
1328 if (env->insn_flags & ASE_MICROMIPS) {
1329 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1330 (arg1 & (1 << CP0C3_ISA_ON_EXC));
1331 }
1332}
1333
1334void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1335{
1336 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1337 (arg1 & env->CP0_Config4_rw_bitmask);
1338}
1339
1340void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1341{
1342 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1343 (arg1 & env->CP0_Config5_rw_bitmask);
1344 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
1345 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
1346 compute_hflags(env);
1347}
1348
1349void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1350{
1351 target_long mask = env->CP0_LLAddr_rw_bitmask;
1352 arg1 = arg1 << env->CP0_LLAddr_shift;
1353 env->CP0_LLAddr = (env->CP0_LLAddr & ~mask) | (arg1 & mask);
1354}
1355
1356#define MTC0_MAAR_MASK(env) \
1357 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1358
1359void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1360{
1361 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1362}
1363
1364void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1365{
1366 env->CP0_MAAR[env->CP0_MAARI] =
1367 (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1368 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1369}
1370
1371void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1372{
1373 int index = arg1 & 0x3f;
1374 if (index == 0x3f) {
1375
1376
1377
1378
1379 env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1380 } else if (index < MIPS_MAAR_MAX) {
1381 env->CP0_MAARI = index;
1382 }
1383
1384
1385
1386
1387}
1388
1389void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1390{
1391
1392
1393
1394
1395 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1396}
1397
1398void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1399{
1400 uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
1401 if ((env->CP0_Config5 >> CP0C5_MI) & 1) {
1402 mask |= 0xFFFFFFFF00000000ULL;
1403 }
1404 env->CP0_WatchHi[sel] = arg1 & mask;
1405 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1406}
1407
1408void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1409{
1410 env->CP0_WatchHi[sel] = ((uint64_t) (arg1) << 32) |
1411 (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL);
1412}
1413
1414void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1415{
1416 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1417 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1418}
1419
1420void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1421{
1422 env->CP0_Framemask = arg1;
1423}
1424
1425void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1426{
1427 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1428 if (arg1 & (1 << CP0DB_DM)) {
1429 env->hflags |= MIPS_HFLAG_DM;
1430 } else {
1431 env->hflags &= ~MIPS_HFLAG_DM;
1432 }
1433}
1434
1435void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1436{
1437 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1438 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1439 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1440
1441
1442 if (other_tc == other->current_tc) {
1443 other->active_tc.CP0_Debug_tcstatus = val;
1444 } else {
1445 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1446 }
1447 other->CP0_Debug = (other->CP0_Debug &
1448 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1449 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1450}
1451
1452void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1453{
1454 env->CP0_Performance0 = arg1 & 0x000007ff;
1455}
1456
1457void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1458{
1459 int32_t wst = arg1 & (1 << CP0EC_WST);
1460 int32_t spr = arg1 & (1 << CP0EC_SPR);
1461 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1462
1463 env->CP0_ErrCtl = wst | spr | itc;
1464
1465 if (itc && !wst && !spr) {
1466 env->hflags |= MIPS_HFLAG_ITC_CACHE;
1467 } else {
1468 env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1469 }
1470}
1471
1472void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1473{
1474 if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1475
1476
1477
1478
1479
1480 env->CP0_TagLo = arg1;
1481 } else {
1482 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1483 }
1484}
1485
1486void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1487{
1488 env->CP0_DataLo = arg1;
1489}
1490
1491void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1492{
1493 env->CP0_TagHi = arg1;
1494}
1495
1496void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1497{
1498 env->CP0_DataHi = arg1;
1499}
1500
1501
1502target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1503{
1504 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1505 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1506
1507 if (other_tc == other->current_tc) {
1508 return other->active_tc.gpr[sel];
1509 } else {
1510 return other->tcs[other_tc].gpr[sel];
1511 }
1512}
1513
1514target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1515{
1516 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1517 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1518
1519 if (other_tc == other->current_tc) {
1520 return other->active_tc.LO[sel];
1521 } else {
1522 return other->tcs[other_tc].LO[sel];
1523 }
1524}
1525
1526target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1527{
1528 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1529 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1530
1531 if (other_tc == other->current_tc) {
1532 return other->active_tc.HI[sel];
1533 } else {
1534 return other->tcs[other_tc].HI[sel];
1535 }
1536}
1537
1538target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1539{
1540 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1541 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1542
1543 if (other_tc == other->current_tc) {
1544 return other->active_tc.ACX[sel];
1545 } else {
1546 return other->tcs[other_tc].ACX[sel];
1547 }
1548}
1549
1550target_ulong helper_mftdsp(CPUMIPSState *env)
1551{
1552 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1553 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1554
1555 if (other_tc == other->current_tc) {
1556 return other->active_tc.DSPControl;
1557 } else {
1558 return other->tcs[other_tc].DSPControl;
1559 }
1560}
1561
1562void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1563{
1564 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1565 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1566
1567 if (other_tc == other->current_tc) {
1568 other->active_tc.gpr[sel] = arg1;
1569 } else {
1570 other->tcs[other_tc].gpr[sel] = arg1;
1571 }
1572}
1573
1574void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1575{
1576 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1577 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1578
1579 if (other_tc == other->current_tc) {
1580 other->active_tc.LO[sel] = arg1;
1581 } else {
1582 other->tcs[other_tc].LO[sel] = arg1;
1583 }
1584}
1585
1586void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1587{
1588 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1589 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1590
1591 if (other_tc == other->current_tc) {
1592 other->active_tc.HI[sel] = arg1;
1593 } else {
1594 other->tcs[other_tc].HI[sel] = arg1;
1595 }
1596}
1597
1598void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1599{
1600 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1601 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1602
1603 if (other_tc == other->current_tc) {
1604 other->active_tc.ACX[sel] = arg1;
1605 } else {
1606 other->tcs[other_tc].ACX[sel] = arg1;
1607 }
1608}
1609
1610void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1611{
1612 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1613 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1614
1615 if (other_tc == other->current_tc) {
1616 other->active_tc.DSPControl = arg1;
1617 } else {
1618 other->tcs[other_tc].DSPControl = arg1;
1619 }
1620}
1621
1622
1623target_ulong helper_dmt(void)
1624{
1625
1626 return 0;
1627}
1628
1629target_ulong helper_emt(void)
1630{
1631
1632 return 0;
1633}
1634
1635target_ulong helper_dvpe(CPUMIPSState *env)
1636{
1637 CPUState *other_cs = first_cpu;
1638 target_ulong prev = env->mvp->CP0_MVPControl;
1639
1640 CPU_FOREACH(other_cs) {
1641 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1642
1643 if (&other_cpu->env != env) {
1644 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1645 mips_vpe_sleep(other_cpu);
1646 }
1647 }
1648 return prev;
1649}
1650
1651target_ulong helper_evpe(CPUMIPSState *env)
1652{
1653 CPUState *other_cs = first_cpu;
1654 target_ulong prev = env->mvp->CP0_MVPControl;
1655
1656 CPU_FOREACH(other_cs) {
1657 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1658
1659 if (&other_cpu->env != env
1660
1661 && !mips_vpe_is_wfi(other_cpu)) {
1662
1663 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1664 mips_vpe_wake(other_cpu);
1665 }
1666 }
1667 return prev;
1668}
1669#endif
1670
1671
1672#ifndef CONFIG_USER_ONLY
1673target_ulong helper_dvp(CPUMIPSState *env)
1674{
1675 CPUState *other_cs = first_cpu;
1676 target_ulong prev = env->CP0_VPControl;
1677
1678 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
1679 CPU_FOREACH(other_cs) {
1680 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1681
1682 if (&other_cpu->env != env) {
1683 mips_vpe_sleep(other_cpu);
1684 }
1685 }
1686 env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
1687 }
1688 return prev;
1689}
1690
1691target_ulong helper_evp(CPUMIPSState *env)
1692{
1693 CPUState *other_cs = first_cpu;
1694 target_ulong prev = env->CP0_VPControl;
1695
1696 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
1697 CPU_FOREACH(other_cs) {
1698 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1699 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
1700
1701
1702
1703
1704 mips_vpe_wake(other_cpu);
1705 }
1706 }
1707 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
1708 }
1709 return prev;
1710}
1711#endif
1712