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15#include "qemu/osdep.h"
16#include <virglrenderer.h>
17#include "virgl.h"
18
19#include <epoxy/gl.h>
20
21void
22vg_virgl_update_cursor_data(VuGpu *g, uint32_t resource_id,
23 gpointer data)
24{
25 uint32_t width, height;
26 uint32_t *cursor;
27
28 cursor = virgl_renderer_get_cursor_data(resource_id, &width, &height);
29 g_return_if_fail(cursor != NULL);
30 g_return_if_fail(width == 64);
31 g_return_if_fail(height == 64);
32
33 memcpy(data, cursor, 64 * 64 * sizeof(uint32_t));
34 free(cursor);
35}
36
37static void
38virgl_cmd_context_create(VuGpu *g,
39 struct virtio_gpu_ctrl_command *cmd)
40{
41 struct virtio_gpu_ctx_create cc;
42
43 VUGPU_FILL_CMD(cc);
44
45 virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen,
46 cc.debug_name);
47}
48
49static void
50virgl_cmd_context_destroy(VuGpu *g,
51 struct virtio_gpu_ctrl_command *cmd)
52{
53 struct virtio_gpu_ctx_destroy cd;
54
55 VUGPU_FILL_CMD(cd);
56
57 virgl_renderer_context_destroy(cd.hdr.ctx_id);
58}
59
60static void
61virgl_cmd_create_resource_2d(VuGpu *g,
62 struct virtio_gpu_ctrl_command *cmd)
63{
64 struct virtio_gpu_resource_create_2d c2d;
65 struct virgl_renderer_resource_create_args args;
66
67 VUGPU_FILL_CMD(c2d);
68
69 args.handle = c2d.resource_id;
70 args.target = 2;
71 args.format = c2d.format;
72 args.bind = (1 << 1);
73 args.width = c2d.width;
74 args.height = c2d.height;
75 args.depth = 1;
76 args.array_size = 1;
77 args.last_level = 0;
78 args.nr_samples = 0;
79 args.flags = VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP;
80 virgl_renderer_resource_create(&args, NULL, 0);
81}
82
83static void
84virgl_cmd_create_resource_3d(VuGpu *g,
85 struct virtio_gpu_ctrl_command *cmd)
86{
87 struct virtio_gpu_resource_create_3d c3d;
88 struct virgl_renderer_resource_create_args args;
89
90 VUGPU_FILL_CMD(c3d);
91
92 args.handle = c3d.resource_id;
93 args.target = c3d.target;
94 args.format = c3d.format;
95 args.bind = c3d.bind;
96 args.width = c3d.width;
97 args.height = c3d.height;
98 args.depth = c3d.depth;
99 args.array_size = c3d.array_size;
100 args.last_level = c3d.last_level;
101 args.nr_samples = c3d.nr_samples;
102 args.flags = c3d.flags;
103 virgl_renderer_resource_create(&args, NULL, 0);
104}
105
106static void
107virgl_cmd_resource_unref(VuGpu *g,
108 struct virtio_gpu_ctrl_command *cmd)
109{
110 struct virtio_gpu_resource_unref unref;
111
112 VUGPU_FILL_CMD(unref);
113
114 virgl_renderer_resource_unref(unref.resource_id);
115}
116
117
118#ifndef VIRTIO_GPU_CAPSET_VIRGL2
119#define VIRTIO_GPU_CAPSET_VIRGL2 2
120#endif
121
122static void
123virgl_cmd_get_capset_info(VuGpu *g,
124 struct virtio_gpu_ctrl_command *cmd)
125{
126 struct virtio_gpu_get_capset_info info;
127 struct virtio_gpu_resp_capset_info resp;
128
129 VUGPU_FILL_CMD(info);
130
131 if (info.capset_index == 0) {
132 resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL;
133 virgl_renderer_get_cap_set(resp.capset_id,
134 &resp.capset_max_version,
135 &resp.capset_max_size);
136 } else if (info.capset_index == 1) {
137 resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL2;
138 virgl_renderer_get_cap_set(resp.capset_id,
139 &resp.capset_max_version,
140 &resp.capset_max_size);
141 } else {
142 resp.capset_max_version = 0;
143 resp.capset_max_size = 0;
144 }
145 resp.hdr.type = VIRTIO_GPU_RESP_OK_CAPSET_INFO;
146 vg_ctrl_response(g, cmd, &resp.hdr, sizeof(resp));
147}
148
149uint32_t
150vg_virgl_get_num_capsets(void)
151{
152 uint32_t capset2_max_ver, capset2_max_size;
153 virgl_renderer_get_cap_set(VIRTIO_GPU_CAPSET_VIRGL2,
154 &capset2_max_ver,
155 &capset2_max_size);
156
157 return capset2_max_ver ? 2 : 1;
158}
159
160static void
161virgl_cmd_get_capset(VuGpu *g,
162 struct virtio_gpu_ctrl_command *cmd)
163{
164 struct virtio_gpu_get_capset gc;
165 struct virtio_gpu_resp_capset *resp;
166 uint32_t max_ver, max_size;
167
168 VUGPU_FILL_CMD(gc);
169
170 virgl_renderer_get_cap_set(gc.capset_id, &max_ver,
171 &max_size);
172 resp = g_malloc0(sizeof(*resp) + max_size);
173
174 resp->hdr.type = VIRTIO_GPU_RESP_OK_CAPSET;
175 virgl_renderer_fill_caps(gc.capset_id,
176 gc.capset_version,
177 (void *)resp->capset_data);
178 vg_ctrl_response(g, cmd, &resp->hdr, sizeof(*resp) + max_size);
179 g_free(resp);
180}
181
182static void
183virgl_cmd_submit_3d(VuGpu *g,
184 struct virtio_gpu_ctrl_command *cmd)
185{
186 struct virtio_gpu_cmd_submit cs;
187 void *buf;
188 size_t s;
189
190 VUGPU_FILL_CMD(cs);
191
192 buf = g_malloc(cs.size);
193 s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num,
194 sizeof(cs), buf, cs.size);
195 if (s != cs.size) {
196 g_critical("%s: size mismatch (%zd/%d)", __func__, s, cs.size);
197 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
198 goto out;
199 }
200
201 virgl_renderer_submit_cmd(buf, cs.hdr.ctx_id, cs.size / 4);
202
203out:
204 g_free(buf);
205}
206
207static void
208virgl_cmd_transfer_to_host_2d(VuGpu *g,
209 struct virtio_gpu_ctrl_command *cmd)
210{
211 struct virtio_gpu_transfer_to_host_2d t2d;
212 struct virtio_gpu_box box;
213
214 VUGPU_FILL_CMD(t2d);
215
216 box.x = t2d.r.x;
217 box.y = t2d.r.y;
218 box.z = 0;
219 box.w = t2d.r.width;
220 box.h = t2d.r.height;
221 box.d = 1;
222
223 virgl_renderer_transfer_write_iov(t2d.resource_id,
224 0,
225 0,
226 0,
227 0,
228 (struct virgl_box *)&box,
229 t2d.offset, NULL, 0);
230}
231
232static void
233virgl_cmd_transfer_to_host_3d(VuGpu *g,
234 struct virtio_gpu_ctrl_command *cmd)
235{
236 struct virtio_gpu_transfer_host_3d t3d;
237
238 VUGPU_FILL_CMD(t3d);
239
240 virgl_renderer_transfer_write_iov(t3d.resource_id,
241 t3d.hdr.ctx_id,
242 t3d.level,
243 t3d.stride,
244 t3d.layer_stride,
245 (struct virgl_box *)&t3d.box,
246 t3d.offset, NULL, 0);
247}
248
249static void
250virgl_cmd_transfer_from_host_3d(VuGpu *g,
251 struct virtio_gpu_ctrl_command *cmd)
252{
253 struct virtio_gpu_transfer_host_3d tf3d;
254
255 VUGPU_FILL_CMD(tf3d);
256
257 virgl_renderer_transfer_read_iov(tf3d.resource_id,
258 tf3d.hdr.ctx_id,
259 tf3d.level,
260 tf3d.stride,
261 tf3d.layer_stride,
262 (struct virgl_box *)&tf3d.box,
263 tf3d.offset, NULL, 0);
264}
265
266static void
267virgl_resource_attach_backing(VuGpu *g,
268 struct virtio_gpu_ctrl_command *cmd)
269{
270 struct virtio_gpu_resource_attach_backing att_rb;
271 struct iovec *res_iovs;
272 int ret;
273
274 VUGPU_FILL_CMD(att_rb);
275
276 ret = vg_create_mapping_iov(g, &att_rb, cmd, &res_iovs);
277 if (ret != 0) {
278 cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
279 return;
280 }
281
282 virgl_renderer_resource_attach_iov(att_rb.resource_id,
283 res_iovs, att_rb.nr_entries);
284}
285
286static void
287virgl_resource_detach_backing(VuGpu *g,
288 struct virtio_gpu_ctrl_command *cmd)
289{
290 struct virtio_gpu_resource_detach_backing detach_rb;
291 struct iovec *res_iovs = NULL;
292 int num_iovs = 0;
293
294 VUGPU_FILL_CMD(detach_rb);
295
296 virgl_renderer_resource_detach_iov(detach_rb.resource_id,
297 &res_iovs,
298 &num_iovs);
299 if (res_iovs == NULL || num_iovs == 0) {
300 return;
301 }
302 g_free(res_iovs);
303}
304
305static void
306virgl_cmd_set_scanout(VuGpu *g,
307 struct virtio_gpu_ctrl_command *cmd)
308{
309 struct virtio_gpu_set_scanout ss;
310 struct virgl_renderer_resource_info info;
311 int ret;
312
313 VUGPU_FILL_CMD(ss);
314
315 if (ss.scanout_id >= VIRTIO_GPU_MAX_SCANOUTS) {
316 g_critical("%s: illegal scanout id specified %d",
317 __func__, ss.scanout_id);
318 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
319 return;
320 }
321
322 memset(&info, 0, sizeof(info));
323
324 if (ss.resource_id && ss.r.width && ss.r.height) {
325 ret = virgl_renderer_resource_get_info(ss.resource_id, &info);
326 if (ret == -1) {
327 g_critical("%s: illegal resource specified %d\n",
328 __func__, ss.resource_id);
329 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
330 return;
331 }
332
333 int fd = -1;
334 if (virgl_renderer_get_fd_for_texture(info.tex_id, &fd) < 0) {
335 g_critical("%s: failed to get fd for texture\n", __func__);
336 cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
337 return;
338 }
339 assert(fd >= 0);
340 VhostUserGpuMsg msg = {
341 .request = VHOST_USER_GPU_DMABUF_SCANOUT,
342 .size = sizeof(VhostUserGpuDMABUFScanout),
343 .payload.dmabuf_scanout.scanout_id = ss.scanout_id,
344 .payload.dmabuf_scanout.x = ss.r.x,
345 .payload.dmabuf_scanout.y = ss.r.y,
346 .payload.dmabuf_scanout.width = ss.r.width,
347 .payload.dmabuf_scanout.height = ss.r.height,
348 .payload.dmabuf_scanout.fd_width = info.width,
349 .payload.dmabuf_scanout.fd_height = info.height,
350 .payload.dmabuf_scanout.fd_stride = info.stride,
351 .payload.dmabuf_scanout.fd_flags = info.flags,
352 .payload.dmabuf_scanout.fd_drm_fourcc = info.drm_fourcc
353 };
354 vg_send_msg(g, &msg, fd);
355 close(fd);
356 } else {
357 VhostUserGpuMsg msg = {
358 .request = VHOST_USER_GPU_DMABUF_SCANOUT,
359 .size = sizeof(VhostUserGpuDMABUFScanout),
360 .payload.dmabuf_scanout.scanout_id = ss.scanout_id,
361 };
362 g_debug("disable scanout");
363 vg_send_msg(g, &msg, -1);
364 }
365 g->scanout[ss.scanout_id].resource_id = ss.resource_id;
366}
367
368static void
369virgl_cmd_resource_flush(VuGpu *g,
370 struct virtio_gpu_ctrl_command *cmd)
371{
372 struct virtio_gpu_resource_flush rf;
373 int i;
374
375 VUGPU_FILL_CMD(rf);
376
377 glFlush();
378 if (!rf.resource_id) {
379 g_debug("bad resource id for flush..?");
380 return;
381 }
382 for (i = 0; i < VIRTIO_GPU_MAX_SCANOUTS; i++) {
383 if (g->scanout[i].resource_id != rf.resource_id) {
384 continue;
385 }
386 VhostUserGpuMsg msg = {
387 .request = VHOST_USER_GPU_DMABUF_UPDATE,
388 .size = sizeof(VhostUserGpuUpdate),
389 .payload.update.scanout_id = i,
390 .payload.update.x = rf.r.x,
391 .payload.update.y = rf.r.y,
392 .payload.update.width = rf.r.width,
393 .payload.update.height = rf.r.height
394 };
395 vg_send_msg(g, &msg, -1);
396 vg_wait_ok(g);
397 }
398}
399
400static void
401virgl_cmd_ctx_attach_resource(VuGpu *g,
402 struct virtio_gpu_ctrl_command *cmd)
403{
404 struct virtio_gpu_ctx_resource att_res;
405
406 VUGPU_FILL_CMD(att_res);
407
408 virgl_renderer_ctx_attach_resource(att_res.hdr.ctx_id, att_res.resource_id);
409}
410
411static void
412virgl_cmd_ctx_detach_resource(VuGpu *g,
413 struct virtio_gpu_ctrl_command *cmd)
414{
415 struct virtio_gpu_ctx_resource det_res;
416
417 VUGPU_FILL_CMD(det_res);
418
419 virgl_renderer_ctx_detach_resource(det_res.hdr.ctx_id, det_res.resource_id);
420}
421
422void vg_virgl_process_cmd(VuGpu *g, struct virtio_gpu_ctrl_command *cmd)
423{
424 virgl_renderer_force_ctx_0();
425 switch (cmd->cmd_hdr.type) {
426 case VIRTIO_GPU_CMD_CTX_CREATE:
427 virgl_cmd_context_create(g, cmd);
428 break;
429 case VIRTIO_GPU_CMD_CTX_DESTROY:
430 virgl_cmd_context_destroy(g, cmd);
431 break;
432 case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D:
433 virgl_cmd_create_resource_2d(g, cmd);
434 break;
435 case VIRTIO_GPU_CMD_RESOURCE_CREATE_3D:
436 virgl_cmd_create_resource_3d(g, cmd);
437 break;
438 case VIRTIO_GPU_CMD_SUBMIT_3D:
439 virgl_cmd_submit_3d(g, cmd);
440 break;
441 case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D:
442 virgl_cmd_transfer_to_host_2d(g, cmd);
443 break;
444 case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D:
445 virgl_cmd_transfer_to_host_3d(g, cmd);
446 break;
447 case VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D:
448 virgl_cmd_transfer_from_host_3d(g, cmd);
449 break;
450 case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING:
451 virgl_resource_attach_backing(g, cmd);
452 break;
453 case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING:
454 virgl_resource_detach_backing(g, cmd);
455 break;
456 case VIRTIO_GPU_CMD_SET_SCANOUT:
457 virgl_cmd_set_scanout(g, cmd);
458 break;
459 case VIRTIO_GPU_CMD_RESOURCE_FLUSH:
460 virgl_cmd_resource_flush(g, cmd);
461 break;
462 case VIRTIO_GPU_CMD_RESOURCE_UNREF:
463 virgl_cmd_resource_unref(g, cmd);
464 break;
465 case VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE:
466
467 virgl_cmd_ctx_attach_resource(g, cmd);
468 break;
469 case VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE:
470
471 virgl_cmd_ctx_detach_resource(g, cmd);
472 break;
473 case VIRTIO_GPU_CMD_GET_CAPSET_INFO:
474 virgl_cmd_get_capset_info(g, cmd);
475 break;
476 case VIRTIO_GPU_CMD_GET_CAPSET:
477 virgl_cmd_get_capset(g, cmd);
478 break;
479 case VIRTIO_GPU_CMD_GET_DISPLAY_INFO:
480 vg_get_display_info(g, cmd);
481 break;
482 default:
483 g_debug("TODO handle ctrl %x\n", cmd->cmd_hdr.type);
484 cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
485 break;
486 }
487
488 if (cmd->state != VG_CMD_STATE_NEW) {
489 return;
490 }
491
492 if (cmd->error) {
493 g_warning("%s: ctrl 0x%x, error 0x%x\n", __func__,
494 cmd->cmd_hdr.type, cmd->error);
495 vg_ctrl_response_nodata(g, cmd, cmd->error);
496 return;
497 }
498
499 if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) {
500 vg_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
501 return;
502 }
503
504 g_debug("Creating fence id:%" PRId64 " type:%d",
505 cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
506 virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
507}
508
509static void
510virgl_write_fence(void *opaque, uint32_t fence)
511{
512 VuGpu *g = opaque;
513 struct virtio_gpu_ctrl_command *cmd, *tmp;
514
515 QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) {
516
517
518
519
520 if (cmd->cmd_hdr.fence_id > fence) {
521 continue;
522 }
523 g_debug("FENCE %" PRIu64, cmd->cmd_hdr.fence_id);
524 vg_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
525 QTAILQ_REMOVE(&g->fenceq, cmd, next);
526 free(cmd);
527 g->inflight--;
528 }
529}
530
531#if defined(VIRGL_RENDERER_CALLBACKS_VERSION) && \
532 VIRGL_RENDERER_CALLBACKS_VERSION >= 2
533static int
534virgl_get_drm_fd(void *opaque)
535{
536 VuGpu *g = opaque;
537
538 return g->drm_rnode_fd;
539}
540#endif
541
542static struct virgl_renderer_callbacks virgl_cbs = {
543#if defined(VIRGL_RENDERER_CALLBACKS_VERSION) && \
544 VIRGL_RENDERER_CALLBACKS_VERSION >= 2
545 .get_drm_fd = virgl_get_drm_fd,
546 .version = 2,
547#else
548 .version = 1,
549#endif
550 .write_fence = virgl_write_fence,
551};
552
553static void
554vg_virgl_poll(VuDev *dev, int condition, void *data)
555{
556 virgl_renderer_poll();
557}
558
559bool
560vg_virgl_init(VuGpu *g)
561{
562 int ret;
563
564 if (g->drm_rnode_fd && virgl_cbs.version == 1) {
565 g_warning("virgl will use the default rendernode");
566 }
567
568 ret = virgl_renderer_init(g,
569 VIRGL_RENDERER_USE_EGL |
570 VIRGL_RENDERER_THREAD_SYNC,
571 &virgl_cbs);
572 if (ret != 0) {
573 return false;
574 }
575
576 ret = virgl_renderer_get_poll_fd();
577 if (ret != -1) {
578 g->renderer_source =
579 vug_source_new(&g->dev, ret, G_IO_IN, vg_virgl_poll, g);
580 }
581
582 return true;
583}
584
