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9
10#include "qemu/osdep.h"
11#include "qemu-common.h"
12#include "qemu/datadir.h"
13#include "qemu/error-report.h"
14#include "qapi/error.h"
15#include <libfdt.h>
16#include "hw/arm/boot.h"
17#include "hw/arm/linux-boot-if.h"
18#include "sysemu/kvm.h"
19#include "sysemu/sysemu.h"
20#include "sysemu/numa.h"
21#include "hw/boards.h"
22#include "sysemu/reset.h"
23#include "hw/loader.h"
24#include "elf.h"
25#include "sysemu/device_tree.h"
26#include "qemu/config-file.h"
27#include "qemu/option.h"
28#include "exec/address-spaces.h"
29#include "qemu/units.h"
30
31
32
33
34
35#define KERNEL_ARGS_ADDR 0x100
36#define KERNEL_NOLOAD_ADDR 0x02000000
37#define KERNEL_LOAD_ADDR 0x00010000
38#define KERNEL64_LOAD_ADDR 0x00080000
39
40#define ARM64_TEXT_OFFSET_OFFSET 8
41#define ARM64_MAGIC_OFFSET 56
42
43#define BOOTLOADER_MAX_SIZE (4 * KiB)
44
45AddressSpace *arm_boot_address_space(ARMCPU *cpu,
46 const struct arm_boot_info *info)
47{
48
49
50
51
52 int asidx;
53 CPUState *cs = CPU(cpu);
54
55 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) {
56 asidx = ARMASIdx_S;
57 } else {
58 asidx = ARMASIdx_NS;
59 }
60
61 return cpu_get_address_space(cs, asidx);
62}
63
64typedef enum {
65 FIXUP_NONE = 0,
66 FIXUP_TERMINATOR,
67 FIXUP_BOARDID,
68 FIXUP_BOARD_SETUP,
69 FIXUP_ARGPTR_LO,
70 FIXUP_ARGPTR_HI,
71 FIXUP_ENTRYPOINT_LO,
72 FIXUP_ENTRYPOINT_HI,
73 FIXUP_GIC_CPU_IF,
74 FIXUP_BOOTREG,
75 FIXUP_DSB,
76 FIXUP_MAX,
77} FixupType;
78
79typedef struct ARMInsnFixup {
80 uint32_t insn;
81 FixupType fixup;
82} ARMInsnFixup;
83
84static const ARMInsnFixup bootloader_aarch64[] = {
85 { 0x580000c0 },
86 { 0xaa1f03e1 },
87 { 0xaa1f03e2 },
88 { 0xaa1f03e3 },
89 { 0x58000084 },
90 { 0xd61f0080 },
91 { 0, FIXUP_ARGPTR_LO },
92 { 0, FIXUP_ARGPTR_HI},
93 { 0, FIXUP_ENTRYPOINT_LO },
94 { 0, FIXUP_ENTRYPOINT_HI },
95 { 0, FIXUP_TERMINATOR }
96};
97
98
99
100
101
102
103
104static const ARMInsnFixup bootloader[] = {
105 { 0xe28fe004 },
106 { 0xe51ff004 },
107 { 0, FIXUP_BOARD_SETUP },
108#define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3
109 { 0xe3a00000 },
110 { 0xe59f1004 },
111 { 0xe59f2004 },
112 { 0xe59ff004 },
113 { 0, FIXUP_BOARDID },
114 { 0, FIXUP_ARGPTR_LO },
115 { 0, FIXUP_ENTRYPOINT_LO },
116 { 0, FIXUP_TERMINATOR }
117};
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133#define DSB_INSN 0xf57ff04f
134#define CP15_DSB_INSN 0xee070f9a
135
136static const ARMInsnFixup smpboot[] = {
137 { 0xe59f2028 },
138 { 0xe59f0028 },
139 { 0xe3a01001 },
140 { 0xe5821000 },
141 { 0xe3a010ff },
142 { 0xe5821004 },
143 { 0, FIXUP_DSB },
144 { 0xe320f003 },
145 { 0xe5901000 },
146 { 0xe1110001 },
147 { 0x0afffffb },
148 { 0xe12fff11 },
149 { 0, FIXUP_GIC_CPU_IF },
150 { 0, FIXUP_BOOTREG },
151 { 0, FIXUP_TERMINATOR }
152};
153
154static void write_bootloader(const char *name, hwaddr addr,
155 const ARMInsnFixup *insns, uint32_t *fixupcontext,
156 AddressSpace *as)
157{
158
159
160
161
162
163 int i, len;
164 uint32_t *code;
165
166 len = 0;
167 while (insns[len].fixup != FIXUP_TERMINATOR) {
168 len++;
169 }
170
171 code = g_new0(uint32_t, len);
172
173 for (i = 0; i < len; i++) {
174 uint32_t insn = insns[i].insn;
175 FixupType fixup = insns[i].fixup;
176
177 switch (fixup) {
178 case FIXUP_NONE:
179 break;
180 case FIXUP_BOARDID:
181 case FIXUP_BOARD_SETUP:
182 case FIXUP_ARGPTR_LO:
183 case FIXUP_ARGPTR_HI:
184 case FIXUP_ENTRYPOINT_LO:
185 case FIXUP_ENTRYPOINT_HI:
186 case FIXUP_GIC_CPU_IF:
187 case FIXUP_BOOTREG:
188 case FIXUP_DSB:
189 insn = fixupcontext[fixup];
190 break;
191 default:
192 abort();
193 }
194 code[i] = tswap32(insn);
195 }
196
197 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE);
198
199 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as);
200
201 g_free(code);
202}
203
204static void default_write_secondary(ARMCPU *cpu,
205 const struct arm_boot_info *info)
206{
207 uint32_t fixupcontext[FIXUP_MAX];
208 AddressSpace *as = arm_boot_address_space(cpu, info);
209
210 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr;
211 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr;
212 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
213 fixupcontext[FIXUP_DSB] = DSB_INSN;
214 } else {
215 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN;
216 }
217
218 write_bootloader("smpboot", info->smp_loader_start,
219 smpboot, fixupcontext, as);
220}
221
222void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
223 const struct arm_boot_info *info,
224 hwaddr mvbar_addr)
225{
226 AddressSpace *as = arm_boot_address_space(cpu, info);
227 int n;
228 uint32_t mvbar_blob[] = {
229
230
231
232
233 0xeafffffe,
234 0xeafffffe,
235 0xe1b0f00e,
236 0xeafffffe,
237 0xeafffffe,
238 0xeafffffe,
239 0xeafffffe,
240 0xeafffffe,
241 };
242 uint32_t board_setup_blob[] = {
243
244 0xee110f51,
245 0xe3800b03,
246 0xee010f51,
247 0xe3a00e00 + (mvbar_addr >> 4),
248 0xee0c0f30,
249 0xee110f11,
250 0xe3800031,
251 0xee010f11,
252 0xe1a0100e,
253 0xe1600070,
254 0xe1a0f001,
255 };
256
257
258 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100);
259
260
261 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr)
262 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr));
263
264 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) {
265 mvbar_blob[n] = tswap32(mvbar_blob[n]);
266 }
267 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob),
268 mvbar_addr, as);
269
270 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
271 board_setup_blob[n] = tswap32(board_setup_blob[n]);
272 }
273 rom_add_blob_fixed_as("board-setup", board_setup_blob,
274 sizeof(board_setup_blob), info->board_setup_addr, as);
275}
276
277static void default_reset_secondary(ARMCPU *cpu,
278 const struct arm_boot_info *info)
279{
280 AddressSpace *as = arm_boot_address_space(cpu, info);
281 CPUState *cs = CPU(cpu);
282
283 address_space_stl_notdirty(as, info->smp_bootreg_addr,
284 0, MEMTXATTRS_UNSPECIFIED, NULL);
285 cpu_set_pc(cs, info->smp_loader_start);
286}
287
288static inline bool have_dtb(const struct arm_boot_info *info)
289{
290 return info->dtb_filename || info->get_dtb;
291}
292
293#define WRITE_WORD(p, value) do { \
294 address_space_stl_notdirty(as, p, value, \
295 MEMTXATTRS_UNSPECIFIED, NULL); \
296 p += 4; \
297} while (0)
298
299static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as)
300{
301 int initrd_size = info->initrd_size;
302 hwaddr base = info->loader_start;
303 hwaddr p;
304
305 p = base + KERNEL_ARGS_ADDR;
306
307 WRITE_WORD(p, 5);
308 WRITE_WORD(p, 0x54410001);
309 WRITE_WORD(p, 1);
310 WRITE_WORD(p, 0x1000);
311 WRITE_WORD(p, 0);
312
313
314 WRITE_WORD(p, 4);
315 WRITE_WORD(p, 0x54410002);
316 WRITE_WORD(p, info->ram_size);
317 WRITE_WORD(p, info->loader_start);
318 if (initrd_size) {
319
320 WRITE_WORD(p, 4);
321 WRITE_WORD(p, 0x54420005);
322 WRITE_WORD(p, info->initrd_start);
323 WRITE_WORD(p, initrd_size);
324 }
325 if (info->kernel_cmdline && *info->kernel_cmdline) {
326
327 int cmdline_size;
328
329 cmdline_size = strlen(info->kernel_cmdline);
330 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED,
331 info->kernel_cmdline, cmdline_size + 1);
332 cmdline_size = (cmdline_size >> 2) + 1;
333 WRITE_WORD(p, cmdline_size + 2);
334 WRITE_WORD(p, 0x54410009);
335 p += cmdline_size * 4;
336 }
337 if (info->atag_board) {
338
339 int atag_board_len;
340 uint8_t atag_board_buf[0x1000];
341
342 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;
343 WRITE_WORD(p, (atag_board_len + 8) >> 2);
344 WRITE_WORD(p, 0x414f4d50);
345 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED,
346 atag_board_buf, atag_board_len);
347 p += atag_board_len;
348 }
349
350 WRITE_WORD(p, 0);
351 WRITE_WORD(p, 0);
352}
353
354static void set_kernel_args_old(const struct arm_boot_info *info,
355 AddressSpace *as)
356{
357 hwaddr p;
358 const char *s;
359 int initrd_size = info->initrd_size;
360 hwaddr base = info->loader_start;
361
362
363 p = base + KERNEL_ARGS_ADDR;
364
365 WRITE_WORD(p, 4096);
366
367 WRITE_WORD(p, info->ram_size / 4096);
368
369 WRITE_WORD(p, 0);
370#define FLAG_READONLY 1
371#define FLAG_RDLOAD 4
372#define FLAG_RDPROMPT 8
373
374 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT);
375
376 WRITE_WORD(p, (31 << 8) | 0);
377
378 WRITE_WORD(p, 0);
379
380 WRITE_WORD(p, 0);
381
382 WRITE_WORD(p, 0);
383
384 WRITE_WORD(p, 0);
385
386 WRITE_WORD(p, 0);
387
388
389
390
391 WRITE_WORD(p, 0);
392
393 WRITE_WORD(p, 0);
394 WRITE_WORD(p, 0);
395 WRITE_WORD(p, 0);
396 WRITE_WORD(p, 0);
397
398 WRITE_WORD(p, 0);
399
400 if (initrd_size) {
401 WRITE_WORD(p, info->initrd_start);
402 } else {
403 WRITE_WORD(p, 0);
404 }
405
406 WRITE_WORD(p, initrd_size);
407
408 WRITE_WORD(p, 0);
409
410 WRITE_WORD(p, 0);
411
412 WRITE_WORD(p, 0);
413
414 WRITE_WORD(p, 0);
415
416 WRITE_WORD(p, 0);
417
418 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) {
419 WRITE_WORD(p, 0);
420 }
421 s = info->kernel_cmdline;
422 if (s) {
423 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1);
424 } else {
425 WRITE_WORD(p, 0);
426 }
427}
428
429static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base,
430 uint32_t scells, hwaddr mem_len,
431 int numa_node_id)
432{
433 char *nodename;
434 int ret;
435
436 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base);
437 qemu_fdt_add_subnode(fdt, nodename);
438 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
439 ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base,
440 scells, mem_len);
441 if (ret < 0) {
442 goto out;
443 }
444
445
446 if (numa_node_id >= 0) {
447 ret = qemu_fdt_setprop_cell(fdt, nodename,
448 "numa-node-id", numa_node_id);
449 }
450out:
451 g_free(nodename);
452 return ret;
453}
454
455static void fdt_add_psci_node(void *fdt)
456{
457 uint32_t cpu_suspend_fn;
458 uint32_t cpu_off_fn;
459 uint32_t cpu_on_fn;
460 uint32_t migrate_fn;
461 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
462 const char *psci_method;
463 int64_t psci_conduit;
464 int rc;
465
466 psci_conduit = object_property_get_int(OBJECT(armcpu),
467 "psci-conduit",
468 &error_abort);
469 switch (psci_conduit) {
470 case QEMU_PSCI_CONDUIT_DISABLED:
471 return;
472 case QEMU_PSCI_CONDUIT_HVC:
473 psci_method = "hvc";
474 break;
475 case QEMU_PSCI_CONDUIT_SMC:
476 psci_method = "smc";
477 break;
478 default:
479 g_assert_not_reached();
480 }
481
482
483
484
485
486 rc = fdt_path_offset(fdt, "/psci");
487 if (rc >= 0) {
488 return;
489 }
490
491 qemu_fdt_add_subnode(fdt, "/psci");
492 if (armcpu->psci_version == 2) {
493 const char comp[] = "arm,psci-0.2\0arm,psci";
494 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
495
496 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF;
497 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) {
498 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND;
499 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON;
500 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE;
501 } else {
502 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND;
503 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON;
504 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE;
505 }
506 } else {
507 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci");
508
509 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND;
510 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF;
511 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON;
512 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE;
513 }
514
515
516
517
518
519
520 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method);
521
522 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn);
523 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn);
524 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn);
525 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn);
526}
527
528int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
529 hwaddr addr_limit, AddressSpace *as, MachineState *ms)
530{
531 void *fdt = NULL;
532 int size, rc, n = 0;
533 uint32_t acells, scells;
534 unsigned int i;
535 hwaddr mem_base, mem_len;
536 char **node_path;
537 Error *err = NULL;
538
539 if (binfo->dtb_filename) {
540 char *filename;
541 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename);
542 if (!filename) {
543 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
544 goto fail;
545 }
546
547 fdt = load_device_tree(filename, &size);
548 if (!fdt) {
549 fprintf(stderr, "Couldn't open dtb file %s\n", filename);
550 g_free(filename);
551 goto fail;
552 }
553 g_free(filename);
554 } else {
555 fdt = binfo->get_dtb(binfo, &size);
556 if (!fdt) {
557 fprintf(stderr, "Board was unable to create a dtb blob\n");
558 goto fail;
559 }
560 }
561
562 if (addr_limit > addr && size > (addr_limit - addr)) {
563
564
565
566
567 g_free(fdt);
568 return 0;
569 }
570
571 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
572 NULL, &error_fatal);
573 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
574 NULL, &error_fatal);
575 if (acells == 0 || scells == 0) {
576 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n");
577 goto fail;
578 }
579
580 if (scells < 2 && binfo->ram_size >= 4 * GiB) {
581
582
583
584 fprintf(stderr, "qemu: dtb file not compatible with "
585 "RAM size > 4GB\n");
586 goto fail;
587 }
588
589
590 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err);
591 if (err) {
592 error_report_err(err);
593 goto fail;
594 }
595 while (node_path[n]) {
596 if (g_str_has_prefix(node_path[n], "/memory")) {
597 qemu_fdt_nop_node(fdt, node_path[n]);
598 }
599 n++;
600 }
601 g_strfreev(node_path);
602
603 if (ms->numa_state != NULL && ms->numa_state->num_nodes > 0) {
604 mem_base = binfo->loader_start;
605 for (i = 0; i < ms->numa_state->num_nodes; i++) {
606 mem_len = ms->numa_state->nodes[i].node_mem;
607 rc = fdt_add_memory_node(fdt, acells, mem_base,
608 scells, mem_len, i);
609 if (rc < 0) {
610 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n",
611 mem_base);
612 goto fail;
613 }
614
615 mem_base += mem_len;
616 }
617 } else {
618 rc = fdt_add_memory_node(fdt, acells, binfo->loader_start,
619 scells, binfo->ram_size, -1);
620 if (rc < 0) {
621 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n",
622 binfo->loader_start);
623 goto fail;
624 }
625 }
626
627 rc = fdt_path_offset(fdt, "/chosen");
628 if (rc < 0) {
629 qemu_fdt_add_subnode(fdt, "/chosen");
630 }
631
632 if (ms->kernel_cmdline && *ms->kernel_cmdline) {
633 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
634 ms->kernel_cmdline);
635 if (rc < 0) {
636 fprintf(stderr, "couldn't set /chosen/bootargs\n");
637 goto fail;
638 }
639 }
640
641 if (binfo->initrd_size) {
642 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
643 binfo->initrd_start);
644 if (rc < 0) {
645 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
646 goto fail;
647 }
648
649 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
650 binfo->initrd_start + binfo->initrd_size);
651 if (rc < 0) {
652 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
653 goto fail;
654 }
655 }
656
657 fdt_add_psci_node(fdt);
658
659 if (binfo->modify_dtb) {
660 binfo->modify_dtb(binfo, fdt);
661 }
662
663 qemu_fdt_dumpdtb(fdt, size);
664
665
666
667
668 rom_add_blob_fixed_as("dtb", fdt, size, addr, as);
669
670 g_free(fdt);
671
672 return size;
673
674fail:
675 g_free(fdt);
676 return -1;
677}
678
679static void do_cpu_reset(void *opaque)
680{
681 ARMCPU *cpu = opaque;
682 CPUState *cs = CPU(cpu);
683 CPUARMState *env = &cpu->env;
684 const struct arm_boot_info *info = env->boot_info;
685
686 cpu_reset(cs);
687 if (info) {
688 if (!info->is_linux) {
689 int i;
690
691 uint64_t entry = info->entry;
692
693 switch (info->endianness) {
694 case ARM_ENDIANNESS_LE:
695 env->cp15.sctlr_el[1] &= ~SCTLR_E0E;
696 for (i = 1; i < 4; ++i) {
697 env->cp15.sctlr_el[i] &= ~SCTLR_EE;
698 }
699 env->uncached_cpsr &= ~CPSR_E;
700 break;
701 case ARM_ENDIANNESS_BE8:
702 env->cp15.sctlr_el[1] |= SCTLR_E0E;
703 for (i = 1; i < 4; ++i) {
704 env->cp15.sctlr_el[i] |= SCTLR_EE;
705 }
706 env->uncached_cpsr |= CPSR_E;
707 break;
708 case ARM_ENDIANNESS_BE32:
709 env->cp15.sctlr_el[1] |= SCTLR_B;
710 break;
711 case ARM_ENDIANNESS_UNKNOWN:
712 break;
713 default:
714 g_assert_not_reached();
715 }
716
717 cpu_set_pc(cs, entry);
718 } else {
719
720
721
722
723
724
725 if (arm_feature(env, ARM_FEATURE_EL3)) {
726
727
728
729
730
731
732 if (env->aarch64) {
733 env->cp15.scr_el3 |= SCR_RW;
734 if (arm_feature(env, ARM_FEATURE_EL2)) {
735 env->cp15.hcr_el2 |= HCR_RW;
736 env->pstate = PSTATE_MODE_EL2h;
737 } else {
738 env->pstate = PSTATE_MODE_EL1h;
739 }
740 if (cpu_isar_feature(aa64_pauth, cpu)) {
741 env->cp15.scr_el3 |= SCR_API | SCR_APK;
742 }
743 if (cpu_isar_feature(aa64_mte, cpu)) {
744 env->cp15.scr_el3 |= SCR_ATA;
745 }
746 if (cpu_isar_feature(aa64_sve, cpu)) {
747 env->cp15.cptr_el[3] |= CPTR_EZ;
748 }
749
750 assert(!info->secure_boot);
751
752
753
754
755 assert(!info->secure_board_setup);
756 }
757
758 if (arm_feature(env, ARM_FEATURE_EL2)) {
759
760 env->cp15.scr_el3 |= SCR_HCE;
761 }
762
763
764 if (!info->secure_boot &&
765 (cs != first_cpu || !info->secure_board_setup)) {
766
767 env->cp15.scr_el3 |= SCR_NS;
768
769 env->cp15.nsacr |= 3 << 10;
770 }
771 }
772
773 if (!env->aarch64 && !info->secure_boot &&
774 arm_feature(env, ARM_FEATURE_EL2)) {
775
776
777
778
779
780
781 cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw);
782 }
783
784 if (cs == first_cpu) {
785 AddressSpace *as = arm_boot_address_space(cpu, info);
786
787 cpu_set_pc(cs, info->loader_start);
788
789 if (!have_dtb(info)) {
790 if (old_param) {
791 set_kernel_args_old(info, as);
792 } else {
793 set_kernel_args(info, as);
794 }
795 }
796 } else {
797 info->secondary_cpu_reset_hook(cpu, info);
798 }
799 }
800 arm_rebuild_hflags(env);
801 }
802}
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
822 uint16_t data_key, const char *image_name,
823 bool try_decompress)
824{
825 size_t size = -1;
826 uint8_t *data;
827
828 if (image_name == NULL) {
829 return;
830 }
831
832 if (try_decompress) {
833 size = load_image_gzipped_buffer(image_name,
834 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data);
835 }
836
837 if (size == (size_t)-1) {
838 gchar *contents;
839 gsize length;
840
841 if (!g_file_get_contents(image_name, &contents, &length, NULL)) {
842 error_report("failed to load \"%s\"", image_name);
843 exit(1);
844 }
845 size = length;
846 data = (uint8_t *)contents;
847 }
848
849 fw_cfg_add_i32(fw_cfg, size_key, size);
850 fw_cfg_add_bytes(fw_cfg, data_key, data, size);
851}
852
853static int do_arm_linux_init(Object *obj, void *opaque)
854{
855 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) {
856 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj);
857 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj);
858 struct arm_boot_info *info = opaque;
859
860 if (albifc->arm_linux_init) {
861 albifc->arm_linux_init(albif, info->secure_boot);
862 }
863 }
864 return 0;
865}
866
867static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
868 uint64_t *lowaddr, uint64_t *highaddr,
869 int elf_machine, AddressSpace *as)
870{
871 bool elf_is64;
872 union {
873 Elf32_Ehdr h32;
874 Elf64_Ehdr h64;
875 } elf_header;
876 int data_swab = 0;
877 bool big_endian;
878 int64_t ret = -1;
879 Error *err = NULL;
880
881
882 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err);
883 if (err) {
884 error_free(err);
885 return ret;
886 }
887
888 if (elf_is64) {
889 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB;
890 info->endianness = big_endian ? ARM_ENDIANNESS_BE8
891 : ARM_ENDIANNESS_LE;
892 } else {
893 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB;
894 if (big_endian) {
895 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) {
896 info->endianness = ARM_ENDIANNESS_BE8;
897 } else {
898 info->endianness = ARM_ENDIANNESS_BE32;
899
900
901
902
903
904
905
906 data_swab = 2;
907 }
908 } else {
909 info->endianness = ARM_ENDIANNESS_LE;
910 }
911 }
912
913 ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL,
914 pentry, lowaddr, highaddr, NULL, big_endian, elf_machine,
915 1, data_swab, as);
916 if (ret <= 0) {
917
918 exit(1);
919 }
920
921 return ret;
922}
923
924static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
925 hwaddr *entry, AddressSpace *as)
926{
927 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR;
928 uint64_t kernel_size = 0;
929 uint8_t *buffer;
930 int size;
931
932
933 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES,
934 &buffer);
935
936 if (size < 0) {
937 gsize len;
938
939
940 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) {
941 return -1;
942 }
943 size = len;
944 }
945
946
947 if (size > ARM64_MAGIC_OFFSET + 4 &&
948 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) {
949 uint64_t hdrvals[2];
950
951
952
953
954
955 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals));
956
957 kernel_size = le64_to_cpu(hdrvals[1]);
958
959 if (kernel_size != 0) {
960 kernel_load_offset = le64_to_cpu(hdrvals[0]);
961
962
963
964
965
966
967
968
969
970
971 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) {
972 kernel_load_offset += 2 * MiB;
973 }
974 }
975 }
976
977
978
979
980
981
982 if (kernel_size == 0) {
983 kernel_size = size;
984 }
985
986 *entry = mem_base + kernel_load_offset;
987 rom_add_blob_fixed_as(filename, buffer, size, *entry, as);
988
989 g_free(buffer);
990
991 return kernel_size;
992}
993
994static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
995 struct arm_boot_info *info)
996{
997
998 CPUState *cs;
999 AddressSpace *as = arm_boot_address_space(cpu, info);
1000 int kernel_size;
1001 int initrd_size;
1002 int is_linux = 0;
1003 uint64_t elf_entry;
1004
1005 uint64_t image_low_addr = 0, image_high_addr = 0;
1006 int elf_machine;
1007 hwaddr entry;
1008 static const ARMInsnFixup *primary_loader;
1009 uint64_t ram_end = info->loader_start + info->ram_size;
1010
1011 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1012 primary_loader = bootloader_aarch64;
1013 elf_machine = EM_AARCH64;
1014 } else {
1015 primary_loader = bootloader;
1016 if (!info->write_board_setup) {
1017 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET;
1018 }
1019 elf_machine = EM_ARM;
1020 }
1021
1022 if (!info->secondary_cpu_reset_hook) {
1023 info->secondary_cpu_reset_hook = default_reset_secondary;
1024 }
1025 if (!info->write_secondary_boot) {
1026 info->write_secondary_boot = default_write_secondary;
1027 }
1028
1029 if (info->nb_cpus == 0)
1030 info->nb_cpus = 1;
1031
1032
1033 kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr,
1034 &image_high_addr, elf_machine, as);
1035 if (kernel_size > 0 && have_dtb(info)) {
1036
1037
1038
1039
1040 if (image_low_addr > info->loader_start
1041 || image_high_addr < info->loader_start) {
1042
1043
1044
1045
1046 if (image_low_addr < info->loader_start) {
1047 image_low_addr = 0;
1048 }
1049 info->dtb_start = info->loader_start;
1050 info->dtb_limit = image_low_addr;
1051 }
1052 }
1053 entry = elf_entry;
1054 if (kernel_size < 0) {
1055 uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR;
1056 kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr,
1057 &is_linux, NULL, NULL, as);
1058 if (kernel_size >= 0) {
1059 image_low_addr = loadaddr;
1060 image_high_addr = image_low_addr + kernel_size;
1061 }
1062 }
1063 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {
1064 kernel_size = load_aarch64_image(info->kernel_filename,
1065 info->loader_start, &entry, as);
1066 is_linux = 1;
1067 if (kernel_size >= 0) {
1068 image_low_addr = entry;
1069 image_high_addr = image_low_addr + kernel_size;
1070 }
1071 } else if (kernel_size < 0) {
1072
1073 entry = info->loader_start + KERNEL_LOAD_ADDR;
1074 kernel_size = load_image_targphys_as(info->kernel_filename, entry,
1075 ram_end - KERNEL_LOAD_ADDR, as);
1076 is_linux = 1;
1077 if (kernel_size >= 0) {
1078 image_low_addr = entry;
1079 image_high_addr = image_low_addr + kernel_size;
1080 }
1081 }
1082 if (kernel_size < 0) {
1083 error_report("could not load kernel '%s'", info->kernel_filename);
1084 exit(1);
1085 }
1086
1087 if (kernel_size > info->ram_size) {
1088 error_report("kernel '%s' is too large to fit in RAM "
1089 "(kernel size %d, RAM size %" PRId64 ")",
1090 info->kernel_filename, kernel_size, info->ram_size);
1091 exit(1);
1092 }
1093
1094 info->entry = entry;
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111 info->initrd_start = info->loader_start +
1112 MIN(info->ram_size / 2, 128 * MiB);
1113 if (image_high_addr) {
1114 info->initrd_start = MAX(info->initrd_start, image_high_addr);
1115 }
1116 info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start);
1117
1118 if (is_linux) {
1119 uint32_t fixupcontext[FIXUP_MAX];
1120
1121 if (info->initrd_filename) {
1122
1123 if (info->initrd_start >= ram_end) {
1124 error_report("not enough space after kernel to load initrd");
1125 exit(1);
1126 }
1127
1128 initrd_size = load_ramdisk_as(info->initrd_filename,
1129 info->initrd_start,
1130 ram_end - info->initrd_start, as);
1131 if (initrd_size < 0) {
1132 initrd_size = load_image_targphys_as(info->initrd_filename,
1133 info->initrd_start,
1134 ram_end -
1135 info->initrd_start,
1136 as);
1137 }
1138 if (initrd_size < 0) {
1139 error_report("could not load initrd '%s'",
1140 info->initrd_filename);
1141 exit(1);
1142 }
1143 if (info->initrd_start + initrd_size > ram_end) {
1144 error_report("could not load initrd '%s': "
1145 "too big to fit into RAM after the kernel",
1146 info->initrd_filename);
1147 exit(1);
1148 }
1149 } else {
1150 initrd_size = 0;
1151 }
1152 info->initrd_size = initrd_size;
1153
1154 fixupcontext[FIXUP_BOARDID] = info->board_id;
1155 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr;
1156
1157
1158
1159
1160
1161 if (have_dtb(info)) {
1162 hwaddr align;
1163
1164 if (elf_machine == EM_AARCH64) {
1165
1166
1167
1168
1169
1170
1171
1172 align = 2 * MiB;
1173 } else {
1174
1175
1176
1177
1178 align = 4 * KiB;
1179 }
1180
1181
1182 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size,
1183 align);
1184 if (info->dtb_start >= ram_end) {
1185 error_report("Not enough space for DTB after kernel/initrd");
1186 exit(1);
1187 }
1188 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start;
1189 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32;
1190 } else {
1191 fixupcontext[FIXUP_ARGPTR_LO] =
1192 info->loader_start + KERNEL_ARGS_ADDR;
1193 fixupcontext[FIXUP_ARGPTR_HI] =
1194 (info->loader_start + KERNEL_ARGS_ADDR) >> 32;
1195 if (info->ram_size >= 4 * GiB) {
1196 error_report("RAM size must be less than 4GB to boot"
1197 " Linux kernel using ATAGS (try passing a device tree"
1198 " using -dtb)");
1199 exit(1);
1200 }
1201 }
1202 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry;
1203 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32;
1204
1205 write_bootloader("bootloader", info->loader_start,
1206 primary_loader, fixupcontext, as);
1207
1208 if (info->nb_cpus > 1) {
1209 info->write_secondary_boot(cpu, info);
1210 }
1211 if (info->write_board_setup) {
1212 info->write_board_setup(cpu, info);
1213 }
1214
1215
1216
1217
1218
1219 object_child_foreach_recursive(object_get_root(),
1220 do_arm_linux_init, info);
1221 }
1222 info->is_linux = is_linux;
1223
1224 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
1225 ARM_CPU(cs)->env.boot_info = info;
1226 }
1227}
1228
1229static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info)
1230{
1231
1232
1233 if (have_dtb(info)) {
1234
1235
1236
1237
1238
1239 info->dtb_start = info->loader_start;
1240 }
1241
1242 if (info->kernel_filename) {
1243 FWCfgState *fw_cfg;
1244 bool try_decompressing_kernel;
1245
1246 fw_cfg = fw_cfg_find();
1247 try_decompressing_kernel = arm_feature(&cpu->env,
1248 ARM_FEATURE_AARCH64);
1249
1250
1251
1252
1253
1254
1255 load_image_to_fw_cfg(fw_cfg,
1256 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
1257 info->kernel_filename,
1258 try_decompressing_kernel);
1259 load_image_to_fw_cfg(fw_cfg,
1260 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
1261 info->initrd_filename, false);
1262
1263 if (info->kernel_cmdline) {
1264 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1265 strlen(info->kernel_cmdline) + 1);
1266 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
1267 info->kernel_cmdline);
1268 }
1269 }
1270
1271
1272
1273
1274
1275
1276}
1277
1278void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
1279{
1280 CPUState *cs;
1281 AddressSpace *as = arm_boot_address_space(cpu, info);
1282
1283
1284
1285
1286
1287
1288
1289 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
1290 qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
1291 }
1292
1293
1294
1295
1296
1297
1298 assert(!(info->secure_board_setup && kvm_enabled()));
1299 info->kernel_filename = ms->kernel_filename;
1300 info->kernel_cmdline = ms->kernel_cmdline;
1301 info->initrd_filename = ms->initrd_filename;
1302 info->dtb_filename = ms->dtb;
1303 info->dtb_limit = 0;
1304
1305
1306 if (!info->kernel_filename || info->firmware_loaded) {
1307 arm_setup_firmware_boot(cpu, info);
1308 } else {
1309 arm_setup_direct_kernel_boot(cpu, info);
1310 }
1311
1312 if (!info->skip_dtb_autoload && have_dtb(info)) {
1313 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1314 exit(1);
1315 }
1316 }
1317}
1318
1319static const TypeInfo arm_linux_boot_if_info = {
1320 .name = TYPE_ARM_LINUX_BOOT_IF,
1321 .parent = TYPE_INTERFACE,
1322 .class_size = sizeof(ARMLinuxBootIfClass),
1323};
1324
1325static void arm_linux_boot_register_types(void)
1326{
1327 type_register_static(&arm_linux_boot_if_info);
1328}
1329
1330type_init(arm_linux_boot_register_types)
1331