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20#include "qemu/osdep.h"
21#include "qemu-common.h"
22#include "qemu/datadir.h"
23#include "qapi/error.h"
24#include "hw/sysbus.h"
25#include "migration/vmstate.h"
26#include "hw/arm/boot.h"
27#include "hw/loader.h"
28#include "net/net.h"
29#include "sysemu/runstate.h"
30#include "sysemu/sysemu.h"
31#include "hw/boards.h"
32#include "exec/address-spaces.h"
33#include "qemu/error-report.h"
34#include "hw/char/pl011.h"
35#include "hw/ide/ahci.h"
36#include "hw/cpu/a9mpcore.h"
37#include "hw/cpu/a15mpcore.h"
38#include "qemu/log.h"
39#include "qom/object.h"
40#include "cpu.h"
41
42#define SMP_BOOT_ADDR 0x100
43#define SMP_BOOT_REG 0x40
44#define MPCORE_PERIPHBASE 0xfff10000
45
46#define MVBAR_ADDR 0x200
47#define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t))
48
49#define NIRQ_GIC 160
50
51
52
53static void hb_write_board_setup(ARMCPU *cpu,
54 const struct arm_boot_info *info)
55{
56 arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
57}
58
59static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
60{
61 int n;
62 uint32_t smpboot[] = {
63 0xee100fb0,
64 0xe210000f,
65 0xe3a03040,
66 0xe0830200,
67 0xe59f2024,
68 0xe3a01001,
69 0xe5821100,
70 0xe3a010ff,
71 0xe5821104,
72 0xf57ff04f,
73 0xe320f003,
74 0xe5901000,
75 0xe1110001,
76 0x0afffffb,
77 0xe12fff11,
78 MPCORE_PERIPHBASE
79 };
80 for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
81 smpboot[n] = tswap32(smpboot[n]);
82 }
83 rom_add_blob_fixed_as("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR,
84 arm_boot_address_space(cpu, info));
85}
86
87static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
88{
89 CPUARMState *env = &cpu->env;
90
91 switch (info->nb_cpus) {
92 case 4:
93 address_space_stl_notdirty(&address_space_memory,
94 SMP_BOOT_REG + 0x30, 0,
95 MEMTXATTRS_UNSPECIFIED, NULL);
96
97 case 3:
98 address_space_stl_notdirty(&address_space_memory,
99 SMP_BOOT_REG + 0x20, 0,
100 MEMTXATTRS_UNSPECIFIED, NULL);
101
102 case 2:
103 address_space_stl_notdirty(&address_space_memory,
104 SMP_BOOT_REG + 0x10, 0,
105 MEMTXATTRS_UNSPECIFIED, NULL);
106 env->regs[15] = SMP_BOOT_ADDR;
107 break;
108 default:
109 break;
110 }
111}
112
113#define NUM_REGS 0x200
114static void hb_regs_write(void *opaque, hwaddr offset,
115 uint64_t value, unsigned size)
116{
117 uint32_t *regs = opaque;
118
119 if (offset == 0xf00) {
120 if (value == 1 || value == 2) {
121 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
122 } else if (value == 3) {
123 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
124 }
125 }
126
127 if (offset / 4 >= NUM_REGS) {
128 qemu_log_mask(LOG_GUEST_ERROR,
129 "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset);
130 return;
131 }
132 regs[offset / 4] = value;
133}
134
135static uint64_t hb_regs_read(void *opaque, hwaddr offset,
136 unsigned size)
137{
138 uint32_t value;
139 uint32_t *regs = opaque;
140
141 if (offset / 4 >= NUM_REGS) {
142 qemu_log_mask(LOG_GUEST_ERROR,
143 "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset);
144 return 0;
145 }
146 value = regs[offset / 4];
147
148 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
149 value |= 0x30000000;
150 }
151
152 return value;
153}
154
155static const MemoryRegionOps hb_mem_ops = {
156 .read = hb_regs_read,
157 .write = hb_regs_write,
158 .endianness = DEVICE_NATIVE_ENDIAN,
159};
160
161#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
162OBJECT_DECLARE_SIMPLE_TYPE(HighbankRegsState, HIGHBANK_REGISTERS)
163
164struct HighbankRegsState {
165
166 SysBusDevice parent_obj;
167
168
169 MemoryRegion iomem;
170 uint32_t regs[NUM_REGS];
171};
172
173static VMStateDescription vmstate_highbank_regs = {
174 .name = "highbank-regs",
175 .version_id = 0,
176 .minimum_version_id = 0,
177 .fields = (VMStateField[]) {
178 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
179 VMSTATE_END_OF_LIST(),
180 },
181};
182
183static void highbank_regs_reset(DeviceState *dev)
184{
185 HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
186
187 s->regs[0x40] = 0x05F20121;
188 s->regs[0x41] = 0x2;
189 s->regs[0x42] = 0x05F30121;
190 s->regs[0x43] = 0x05F40121;
191}
192
193static void highbank_regs_init(Object *obj)
194{
195 HighbankRegsState *s = HIGHBANK_REGISTERS(obj);
196 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
197
198 memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs,
199 "highbank_regs", 0x1000);
200 sysbus_init_mmio(dev, &s->iomem);
201}
202
203static void highbank_regs_class_init(ObjectClass *klass, void *data)
204{
205 DeviceClass *dc = DEVICE_CLASS(klass);
206
207 dc->desc = "Calxeda Highbank registers";
208 dc->vmsd = &vmstate_highbank_regs;
209 dc->reset = highbank_regs_reset;
210}
211
212static const TypeInfo highbank_regs_info = {
213 .name = TYPE_HIGHBANK_REGISTERS,
214 .parent = TYPE_SYS_BUS_DEVICE,
215 .instance_size = sizeof(HighbankRegsState),
216 .instance_init = highbank_regs_init,
217 .class_init = highbank_regs_class_init,
218};
219
220static void highbank_regs_register_types(void)
221{
222 type_register_static(&highbank_regs_info);
223}
224
225type_init(highbank_regs_register_types)
226
227static struct arm_boot_info highbank_binfo;
228
229enum cxmachines {
230 CALXEDA_HIGHBANK,
231 CALXEDA_MIDWAY,
232};
233
234
235
236
237
238
239
240static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
241{
242 DeviceState *dev = NULL;
243 SysBusDevice *busdev;
244 qemu_irq pic[128];
245 int n;
246 unsigned int smp_cpus = machine->smp.cpus;
247 qemu_irq cpu_irq[4];
248 qemu_irq cpu_fiq[4];
249 qemu_irq cpu_virq[4];
250 qemu_irq cpu_vfiq[4];
251 MemoryRegion *sysram;
252 MemoryRegion *sysmem;
253 char *sysboot_filename;
254
255 switch (machine_id) {
256 case CALXEDA_HIGHBANK:
257 machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
258 break;
259 case CALXEDA_MIDWAY:
260 machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
261 break;
262 default:
263 assert(0);
264 }
265
266 for (n = 0; n < smp_cpus; n++) {
267 Object *cpuobj;
268 ARMCPU *cpu;
269
270 cpuobj = object_new(machine->cpu_type);
271 cpu = ARM_CPU(cpuobj);
272
273 object_property_set_int(cpuobj, "psci-conduit", QEMU_PSCI_CONDUIT_SMC,
274 &error_abort);
275
276 if (n) {
277
278 object_property_set_bool(cpuobj, "start-powered-off", true,
279 &error_abort);
280 }
281
282 if (object_property_find(cpuobj, "reset-cbar")) {
283 object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE,
284 &error_abort);
285 }
286 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
287 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
288 cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
289 cpu_virq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ);
290 cpu_vfiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VFIQ);
291 }
292
293 sysmem = get_system_memory();
294
295 memory_region_add_subregion(sysmem, 0, machine->ram);
296
297 sysram = g_new(MemoryRegion, 1);
298 memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
299 &error_fatal);
300 memory_region_add_subregion(sysmem, 0xfff88000, sysram);
301 if (machine->firmware != NULL) {
302 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
303 if (sysboot_filename != NULL) {
304 if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
305 error_report("Unable to load %s", machine->firmware);
306 exit(1);
307 }
308 g_free(sysboot_filename);
309 } else {
310 error_report("Unable to find %s", machine->firmware);
311 exit(1);
312 }
313 }
314
315 switch (machine_id) {
316 case CALXEDA_HIGHBANK:
317 dev = qdev_new("l2x0");
318 busdev = SYS_BUS_DEVICE(dev);
319 sysbus_realize_and_unref(busdev, &error_fatal);
320 sysbus_mmio_map(busdev, 0, 0xfff12000);
321
322 dev = qdev_new(TYPE_A9MPCORE_PRIV);
323 break;
324 case CALXEDA_MIDWAY:
325 dev = qdev_new(TYPE_A15MPCORE_PRIV);
326 break;
327 }
328 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
329 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
330 busdev = SYS_BUS_DEVICE(dev);
331 sysbus_realize_and_unref(busdev, &error_fatal);
332 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
333 for (n = 0; n < smp_cpus; n++) {
334 sysbus_connect_irq(busdev, n, cpu_irq[n]);
335 sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
336 sysbus_connect_irq(busdev, n + 2 * smp_cpus, cpu_virq[n]);
337 sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]);
338 }
339
340 for (n = 0; n < 128; n++) {
341 pic[n] = qdev_get_gpio_in(dev, n);
342 }
343
344 dev = qdev_new("sp804");
345 qdev_prop_set_uint32(dev, "freq0", 150000000);
346 qdev_prop_set_uint32(dev, "freq1", 150000000);
347 busdev = SYS_BUS_DEVICE(dev);
348 sysbus_realize_and_unref(busdev, &error_fatal);
349 sysbus_mmio_map(busdev, 0, 0xfff34000);
350 sysbus_connect_irq(busdev, 0, pic[18]);
351 pl011_create(0xfff36000, pic[20], serial_hd(0));
352
353 dev = qdev_new(TYPE_HIGHBANK_REGISTERS);
354 busdev = SYS_BUS_DEVICE(dev);
355 sysbus_realize_and_unref(busdev, &error_fatal);
356 sysbus_mmio_map(busdev, 0, 0xfff3c000);
357
358 sysbus_create_simple("pl061", 0xfff30000, pic[14]);
359 sysbus_create_simple("pl061", 0xfff31000, pic[15]);
360 sysbus_create_simple("pl061", 0xfff32000, pic[16]);
361 sysbus_create_simple("pl061", 0xfff33000, pic[17]);
362 sysbus_create_simple("pl031", 0xfff35000, pic[19]);
363 sysbus_create_simple("pl022", 0xfff39000, pic[23]);
364
365 sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]);
366
367 if (nd_table[0].used) {
368 qemu_check_nic_model(&nd_table[0], "xgmac");
369 dev = qdev_new("xgmac");
370 qdev_set_nic_properties(dev, &nd_table[0]);
371 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
372 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
373 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
374 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
375 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
376
377 qemu_check_nic_model(&nd_table[1], "xgmac");
378 dev = qdev_new("xgmac");
379 qdev_set_nic_properties(dev, &nd_table[1]);
380 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
381 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
382 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
383 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
384 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
385 }
386
387
388
389 highbank_binfo.ram_size = machine->ram_size;
390
391
392
393
394 highbank_binfo.board_id = -1;
395 highbank_binfo.nb_cpus = smp_cpus;
396 highbank_binfo.loader_start = 0;
397 highbank_binfo.write_secondary_boot = hb_write_secondary;
398 highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
399 highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
400 highbank_binfo.write_board_setup = hb_write_board_setup;
401 highbank_binfo.secure_board_setup = true;
402
403 arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo);
404}
405
406static void highbank_init(MachineState *machine)
407{
408 calxeda_init(machine, CALXEDA_HIGHBANK);
409}
410
411static void midway_init(MachineState *machine)
412{
413 calxeda_init(machine, CALXEDA_MIDWAY);
414}
415
416static void highbank_class_init(ObjectClass *oc, void *data)
417{
418 MachineClass *mc = MACHINE_CLASS(oc);
419
420 mc->desc = "Calxeda Highbank (ECX-1000)";
421 mc->init = highbank_init;
422 mc->block_default_type = IF_IDE;
423 mc->units_per_default_bus = 1;
424 mc->max_cpus = 4;
425 mc->ignore_memory_transaction_failures = true;
426 mc->default_ram_id = "highbank.dram";
427}
428
429static const TypeInfo highbank_type = {
430 .name = MACHINE_TYPE_NAME("highbank"),
431 .parent = TYPE_MACHINE,
432 .class_init = highbank_class_init,
433};
434
435static void midway_class_init(ObjectClass *oc, void *data)
436{
437 MachineClass *mc = MACHINE_CLASS(oc);
438
439 mc->desc = "Calxeda Midway (ECX-2000)";
440 mc->init = midway_init;
441 mc->block_default_type = IF_IDE;
442 mc->units_per_default_bus = 1;
443 mc->max_cpus = 4;
444 mc->ignore_memory_transaction_failures = true;
445 mc->default_ram_id = "highbank.dram";
446}
447
448static const TypeInfo midway_type = {
449 .name = MACHINE_TYPE_NAME("midway"),
450 .parent = TYPE_MACHINE,
451 .class_init = midway_class_init,
452};
453
454static void calxeda_machines_init(void)
455{
456 type_register_static(&highbank_type);
457 type_register_static(&midway_type);
458}
459
460type_init(calxeda_machines_init)
461