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47#include "qemu/osdep.h"
48#include "qemu/units.h"
49#include "qemu/cutils.h"
50#include "qapi/error.h"
51#include "qemu/error-report.h"
52#include "hw/arm/boot.h"
53#include "hw/arm/armv7m.h"
54#include "hw/or-irq.h"
55#include "hw/boards.h"
56#include "exec/address-spaces.h"
57#include "sysemu/sysemu.h"
58#include "hw/misc/unimp.h"
59#include "hw/char/cmsdk-apb-uart.h"
60#include "hw/timer/cmsdk-apb-timer.h"
61#include "hw/misc/mps2-scc.h"
62#include "hw/misc/mps2-fpgaio.h"
63#include "hw/misc/tz-mpc.h"
64#include "hw/misc/tz-msc.h"
65#include "hw/arm/armsse.h"
66#include "hw/dma/pl080.h"
67#include "hw/rtc/pl031.h"
68#include "hw/ssi/pl022.h"
69#include "hw/i2c/arm_sbcon_i2c.h"
70#include "hw/net/lan9118.h"
71#include "net/net.h"
72#include "hw/core/split-irq.h"
73#include "hw/qdev-clock.h"
74#include "qom/object.h"
75
76#define MPS2TZ_NUMIRQ_MAX 96
77#define MPS2TZ_RAM_MAX 5
78
79typedef enum MPS2TZFPGAType {
80 FPGA_AN505,
81 FPGA_AN521,
82 FPGA_AN524,
83 FPGA_AN547,
84} MPS2TZFPGAType;
85
86
87
88
89
90
91
92typedef struct RAMInfo {
93 const char *name;
94 uint32_t base;
95 uint32_t size;
96 int mpc;
97 int mrindex;
98 int flags;
99} RAMInfo;
100
101
102
103
104
105
106
107#define IS_ALIAS 1
108#define IS_ROM 2
109
110struct MPS2TZMachineClass {
111 MachineClass parent;
112 MPS2TZFPGAType fpga_type;
113 uint32_t scc_id;
114 uint32_t sysclk_frq;
115 uint32_t apb_periph_frq;
116 uint32_t len_oscclk;
117 const uint32_t *oscclk;
118 uint32_t fpgaio_num_leds;
119 bool fpgaio_has_switches;
120 bool fpgaio_has_dbgctrl;
121 int numirq;
122 int uart_overflow_irq;
123 uint32_t init_svtor;
124 const RAMInfo *raminfo;
125 const char *armsse_type;
126};
127
128struct MPS2TZMachineState {
129 MachineState parent;
130
131 ARMSSE iotkit;
132 MemoryRegion ram[MPS2TZ_RAM_MAX];
133 MemoryRegion eth_usb_container;
134
135 MPS2SCC scc;
136 MPS2FPGAIO fpgaio;
137 TZPPC ppc[5];
138 TZMPC mpc[3];
139 PL022State spi[5];
140 ArmSbconI2CState i2c[5];
141 UnimplementedDeviceState i2s_audio;
142 UnimplementedDeviceState gpio[4];
143 UnimplementedDeviceState gfx;
144 UnimplementedDeviceState cldc;
145 UnimplementedDeviceState usb;
146 PL031State rtc;
147 PL080State dma[4];
148 TZMSC msc[4];
149 CMSDKAPBUART uart[6];
150 SplitIRQ sec_resp_splitter;
151 qemu_or_irq uart_irq_orgate;
152 DeviceState *lan9118;
153 SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX];
154 Clock *sysclk;
155 Clock *s32kclk;
156};
157
158#define TYPE_MPS2TZ_MACHINE "mps2tz"
159#define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")
160#define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521")
161#define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524")
162#define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547")
163
164OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
165
166
167#define S32KCLK_FRQ (32 * 1000)
168
169
170
171
172
173#if HOST_LONG_BITS == 32
174#define MPS3_DDR_SIZE (1 * GiB)
175#else
176#define MPS3_DDR_SIZE (2 * GiB)
177#endif
178
179static const uint32_t an505_oscclk[] = {
180 40000000,
181 24580000,
182 25000000,
183};
184
185static const uint32_t an524_oscclk[] = {
186 24000000,
187 32000000,
188 50000000,
189 50000000,
190 24576000,
191 23750000,
192};
193
194static const RAMInfo an505_raminfo[] = { {
195 .name = "ssram-0",
196 .base = 0x00000000,
197 .size = 0x00400000,
198 .mpc = 0,
199 .mrindex = 0,
200 }, {
201 .name = "ssram-1",
202 .base = 0x28000000,
203 .size = 0x00200000,
204 .mpc = 1,
205 .mrindex = 1,
206 }, {
207 .name = "ssram-2",
208 .base = 0x28200000,
209 .size = 0x00200000,
210 .mpc = 2,
211 .mrindex = 2,
212 }, {
213 .name = "ssram-0-alias",
214 .base = 0x00400000,
215 .size = 0x00400000,
216 .mpc = 0,
217 .mrindex = 3,
218 .flags = IS_ALIAS,
219 }, {
220
221 .name = "mps.ram",
222 .base = 0x80000000,
223 .size = 16 * MiB,
224 .mpc = -1,
225 .mrindex = -1,
226 }, {
227 .name = NULL,
228 },
229};
230
231static const RAMInfo an524_raminfo[] = { {
232 .name = "bram",
233 .base = 0x00000000,
234 .size = 512 * KiB,
235 .mpc = 0,
236 .mrindex = 0,
237 }, {
238 .name = "sram",
239 .base = 0x20000000,
240 .size = 32 * 4 * KiB,
241 .mpc = -1,
242 .mrindex = 1,
243 }, {
244
245 .name = "QSPI",
246 .base = 0x28000000,
247 .size = 8 * MiB,
248 .mpc = 1,
249 .mrindex = 2,
250 .flags = IS_ROM,
251 }, {
252 .name = "DDR",
253 .base = 0x60000000,
254 .size = MPS3_DDR_SIZE,
255 .mpc = 2,
256 .mrindex = -1,
257 }, {
258 .name = NULL,
259 },
260};
261
262static const RAMInfo an547_raminfo[] = { {
263 .name = "itcm",
264 .base = 0x00000000,
265 .size = 512 * KiB,
266 .mpc = -1,
267 .mrindex = 0,
268 }, {
269 .name = "sram",
270 .base = 0x01000000,
271 .size = 2 * MiB,
272 .mpc = 0,
273 .mrindex = 1,
274 }, {
275 .name = "dtcm",
276 .base = 0x20000000,
277 .size = 4 * 128 * KiB,
278 .mpc = -1,
279 .mrindex = 2,
280 }, {
281 .name = "sram 2",
282 .base = 0x21000000,
283 .size = 4 * MiB,
284 .mpc = -1,
285 .mrindex = 3,
286 }, {
287
288 .name = "QSPI",
289 .base = 0x28000000,
290 .size = 8 * MiB,
291 .mpc = 1,
292 .mrindex = 4,
293 .flags = IS_ROM,
294 }, {
295 .name = "DDR",
296 .base = 0x60000000,
297 .size = MPS3_DDR_SIZE,
298 .mpc = 2,
299 .mrindex = -1,
300 }, {
301 .name = NULL,
302 },
303};
304
305static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc)
306{
307 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
308 const RAMInfo *p;
309 const RAMInfo *found = NULL;
310
311 for (p = mmc->raminfo; p->name; p++) {
312 if (p->mpc == mpc && !(p->flags & IS_ALIAS)) {
313
314 g_assert(!found);
315 found = p;
316 }
317 }
318
319 assert(found);
320 return found;
321}
322
323static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms,
324 const RAMInfo *raminfo)
325{
326
327 MemoryRegion *ram;
328
329 if (raminfo->mrindex < 0) {
330
331 MachineState *machine = MACHINE(mms);
332 assert(!(raminfo->flags & IS_ROM));
333 return machine->ram;
334 }
335
336 assert(raminfo->mrindex < MPS2TZ_RAM_MAX);
337 ram = &mms->ram[raminfo->mrindex];
338
339 memory_region_init_ram(ram, NULL, raminfo->name,
340 raminfo->size, &error_fatal);
341 if (raminfo->flags & IS_ROM) {
342 memory_region_set_readonly(ram, true);
343 }
344 return ram;
345}
346
347
348
349
350static void make_ram_alias(MemoryRegion *mr, const char *name,
351 MemoryRegion *orig, hwaddr base)
352{
353 memory_region_init_alias(mr, NULL, name, orig, 0,
354 memory_region_size(orig));
355 memory_region_add_subregion(get_system_memory(), base, mr);
356}
357
358static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno)
359{
360
361
362
363
364
365 MachineClass *mc = MACHINE_GET_CLASS(mms);
366 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
367
368 assert(irqno >= 32 && irqno < (mmc->numirq + 32));
369
370
371
372
373
374 irqno -= 32;
375
376 if (mc->max_cpus > 1) {
377 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0);
378 } else {
379 return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno);
380 }
381}
382
383
384
385
386
387
388
389
390typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque,
391 const char *name, hwaddr size,
392 const int *irqs);
393
394typedef struct PPCPortInfo {
395 const char *name;
396 MakeDevFn *devfn;
397 void *opaque;
398 hwaddr addr;
399 hwaddr size;
400 int irqs[3];
401} PPCPortInfo;
402
403typedef struct PPCInfo {
404 const char *name;
405 PPCPortInfo ports[TZ_NUM_PORTS];
406} PPCInfo;
407
408static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,
409 void *opaque,
410 const char *name, hwaddr size,
411 const int *irqs)
412{
413
414
415
416 UnimplementedDeviceState *uds = opaque;
417
418 object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE);
419 qdev_prop_set_string(DEVICE(uds), "name", name);
420 qdev_prop_set_uint64(DEVICE(uds), "size", size);
421 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
422 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
423}
424
425static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
426 const char *name, hwaddr size,
427 const int *irqs)
428{
429
430 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
431 CMSDKAPBUART *uart = opaque;
432 int i = uart - &mms->uart[0];
433 SysBusDevice *s;
434 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
435
436 object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART);
437 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
438 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq);
439 sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal);
440 s = SYS_BUS_DEVICE(uart);
441 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
442 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1]));
443 sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
444 sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
445 sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2]));
446 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0);
447}
448
449static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,
450 const char *name, hwaddr size,
451 const int *irqs)
452{
453 MPS2SCC *scc = opaque;
454 DeviceState *sccdev;
455 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
456 uint32_t i;
457
458 object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC);
459 sccdev = DEVICE(scc);
460 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
461 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
462 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
463 qdev_prop_set_uint32(sccdev, "len-oscclk", mmc->len_oscclk);
464 for (i = 0; i < mmc->len_oscclk; i++) {
465 g_autofree char *propname = g_strdup_printf("oscclk[%u]", i);
466 qdev_prop_set_uint32(sccdev, propname, mmc->oscclk[i]);
467 }
468 sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal);
469 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);
470}
471
472static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque,
473 const char *name, hwaddr size,
474 const int *irqs)
475{
476 MPS2FPGAIO *fpgaio = opaque;
477 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
478
479 object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO);
480 qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds);
481 qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_switches);
482 qdev_prop_set_bit(DEVICE(fpgaio), "has-dbgctrl", mmc->fpgaio_has_dbgctrl);
483 sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal);
484 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0);
485}
486
487static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
488 const char *name, hwaddr size,
489 const int *irqs)
490{
491 SysBusDevice *s;
492 NICInfo *nd = &nd_table[0];
493
494
495
496
497 qemu_check_nic_model(nd, "lan9118");
498 mms->lan9118 = qdev_new(TYPE_LAN9118);
499 qdev_set_nic_properties(mms->lan9118, nd);
500
501 s = SYS_BUS_DEVICE(mms->lan9118);
502 sysbus_realize_and_unref(s, &error_fatal);
503 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
504 return sysbus_mmio_get_region(s, 0);
505}
506
507static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque,
508 const char *name, hwaddr size,
509 const int *irqs)
510{
511
512
513
514
515 SysBusDevice *s;
516 NICInfo *nd = &nd_table[0];
517
518 memory_region_init(&mms->eth_usb_container, OBJECT(mms),
519 "mps2-tz-eth-usb-container", 0x200000);
520
521
522
523
524
525 qemu_check_nic_model(nd, "lan9118");
526 mms->lan9118 = qdev_new(TYPE_LAN9118);
527 qdev_set_nic_properties(mms->lan9118, nd);
528
529 s = SYS_BUS_DEVICE(mms->lan9118);
530 sysbus_realize_and_unref(s, &error_fatal);
531 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
532
533 memory_region_add_subregion(&mms->eth_usb_container,
534 0, sysbus_mmio_get_region(s, 0));
535
536
537 object_initialize_child(OBJECT(mms), "usb-otg",
538 &mms->usb, TYPE_UNIMPLEMENTED_DEVICE);
539 qdev_prop_set_string(DEVICE(&mms->usb), "name", "usb-otg");
540 qdev_prop_set_uint64(DEVICE(&mms->usb), "size", 0x100000);
541 s = SYS_BUS_DEVICE(&mms->usb);
542 sysbus_realize(s, &error_fatal);
543
544 memory_region_add_subregion(&mms->eth_usb_container,
545 0x100000, sysbus_mmio_get_region(s, 0));
546
547 return &mms->eth_usb_container;
548}
549
550static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
551 const char *name, hwaddr size,
552 const int *irqs)
553{
554 TZMPC *mpc = opaque;
555 int i = mpc - &mms->mpc[0];
556 MemoryRegion *upstream;
557 const RAMInfo *raminfo = find_raminfo_for_mpc(mms, i);
558 MemoryRegion *ram = mr_for_raminfo(mms, raminfo);
559
560 object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC);
561 object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram),
562 &error_fatal);
563 sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal);
564
565 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
566 memory_region_add_subregion(get_system_memory(), raminfo->base, upstream);
567
568 qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0,
569 qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
570 "mpcexp_status", i));
571
572
573 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0);
574}
575
576static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque,
577 const char *name, hwaddr size,
578 const int *irqs)
579{
580
581 PL080State *dma = opaque;
582 int i = dma - &mms->dma[0];
583 SysBusDevice *s;
584 char *mscname = g_strdup_printf("%s-msc", name);
585 TZMSC *msc = &mms->msc[i];
586 DeviceState *iotkitdev = DEVICE(&mms->iotkit);
587 MemoryRegion *msc_upstream;
588 MemoryRegion *msc_downstream;
589
590
591
592
593
594
595
596 object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC);
597 msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0);
598 object_property_set_link(OBJECT(msc), "downstream",
599 OBJECT(msc_downstream), &error_fatal);
600 object_property_set_link(OBJECT(msc), "idau", OBJECT(mms), &error_fatal);
601 sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal);
602
603 qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0,
604 qdev_get_gpio_in_named(iotkitdev,
605 "mscexp_status", i));
606 qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i,
607 qdev_get_gpio_in_named(DEVICE(msc),
608 "irq_clear", 0));
609 qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i,
610 qdev_get_gpio_in_named(DEVICE(msc),
611 "cfg_nonsec", 0));
612 qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter),
613 ARRAY_SIZE(mms->ppc) + i,
614 qdev_get_gpio_in_named(DEVICE(msc),
615 "cfg_sec_resp", 0));
616 msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0);
617
618 object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081);
619 object_property_set_link(OBJECT(dma), "downstream", OBJECT(msc_upstream),
620 &error_fatal);
621 sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal);
622
623 s = SYS_BUS_DEVICE(dma);
624
625 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
626 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1]));
627 sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqs[2]));
628
629 g_free(mscname);
630 return sysbus_mmio_get_region(s, 0);
631}
632
633static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque,
634 const char *name, hwaddr size,
635 const int *irqs)
636{
637
638
639
640
641
642
643
644
645 PL022State *spi = opaque;
646 SysBusDevice *s;
647
648 object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022);
649 sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal);
650 s = SYS_BUS_DEVICE(spi);
651 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
652 return sysbus_mmio_get_region(s, 0);
653}
654
655static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque,
656 const char *name, hwaddr size,
657 const int *irqs)
658{
659 ArmSbconI2CState *i2c = opaque;
660 SysBusDevice *s;
661
662 object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C);
663 s = SYS_BUS_DEVICE(i2c);
664 sysbus_realize(s, &error_fatal);
665 return sysbus_mmio_get_region(s, 0);
666}
667
668static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque,
669 const char *name, hwaddr size,
670 const int *irqs)
671{
672 PL031State *pl031 = opaque;
673 SysBusDevice *s;
674
675 object_initialize_child(OBJECT(mms), name, pl031, TYPE_PL031);
676 s = SYS_BUS_DEVICE(pl031);
677 sysbus_realize(s, &error_fatal);
678
679
680
681
682 return sysbus_mmio_get_region(s, 0);
683}
684
685static void create_non_mpc_ram(MPS2TZMachineState *mms)
686{
687
688
689
690
691 const RAMInfo *p;
692 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
693
694 for (p = mmc->raminfo; p->name; p++) {
695 if (p->flags & IS_ALIAS) {
696 SysBusDevice *mpc_sbd = SYS_BUS_DEVICE(&mms->mpc[p->mpc]);
697 MemoryRegion *upstream = sysbus_mmio_get_region(mpc_sbd, 1);
698 make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->base);
699 } else if (p->mpc == -1) {
700
701 MemoryRegion *mr = mr_for_raminfo(mms, p);
702 memory_region_add_subregion(get_system_memory(), p->base, mr);
703 }
704 }
705}
706
707static uint32_t boot_ram_size(MPS2TZMachineState *mms)
708{
709
710 const RAMInfo *p;
711 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
712
713 for (p = mmc->raminfo; p->name; p++) {
714 if (p->base == 0) {
715 return p->size;
716 }
717 }
718 g_assert_not_reached();
719}
720
721static void mps2tz_common_init(MachineState *machine)
722{
723 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);
724 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
725 MachineClass *mc = MACHINE_GET_CLASS(machine);
726 MemoryRegion *system_memory = get_system_memory();
727 DeviceState *iotkitdev;
728 DeviceState *dev_splitter;
729 const PPCInfo *ppcs;
730 int num_ppcs;
731 int i;
732
733 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
734 error_report("This board can only be used with CPU %s",
735 mc->default_cpu_type);
736 exit(1);
737 }
738
739 if (machine->ram_size != mc->default_ram_size) {
740 char *sz = size_to_str(mc->default_ram_size);
741 error_report("Invalid RAM size, should be %s", sz);
742 g_free(sz);
743 exit(EXIT_FAILURE);
744 }
745
746
747 mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
748 clock_set_hz(mms->sysclk, mmc->sysclk_frq);
749 mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
750 clock_set_hz(mms->s32kclk, S32KCLK_FRQ);
751
752 object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
753 mmc->armsse_type);
754 iotkitdev = DEVICE(&mms->iotkit);
755 object_property_set_link(OBJECT(&mms->iotkit), "memory",
756 OBJECT(system_memory), &error_abort);
757 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
758 qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
759 qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
760 qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
761 sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
762
763
764
765
766
767
768
769 assert(mmc->numirq <= MPS2TZ_NUMIRQ_MAX);
770 if (mc->max_cpus > 1) {
771 for (i = 0; i < mmc->numirq; i++) {
772 char *name = g_strdup_printf("mps2-irq-splitter%d", i);
773 SplitIRQ *splitter = &mms->cpu_irq_splitter[i];
774
775 object_initialize_child_with_props(OBJECT(machine), name,
776 splitter, sizeof(*splitter),
777 TYPE_SPLIT_IRQ, &error_fatal,
778 NULL);
779 g_free(name);
780
781 object_property_set_int(OBJECT(splitter), "num-lines", 2,
782 &error_fatal);
783 qdev_realize(DEVICE(splitter), NULL, &error_fatal);
784 qdev_connect_gpio_out(DEVICE(splitter), 0,
785 qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
786 "EXP_IRQ", i));
787 qdev_connect_gpio_out(DEVICE(splitter), 1,
788 qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
789 "EXP_CPU1_IRQ", i));
790 }
791 }
792
793
794
795
796 object_initialize_child(OBJECT(machine), "sec-resp-splitter",
797 &mms->sec_resp_splitter, TYPE_SPLIT_IRQ);
798 object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines",
799 ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc),
800 &error_fatal);
801 qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal);
802 dev_splitter = DEVICE(&mms->sec_resp_splitter);
803 qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0,
804 qdev_get_gpio_in(dev_splitter, 0));
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826 object_initialize_child(OBJECT(mms), "uart-irq-orgate",
827 &mms->uart_irq_orgate, TYPE_OR_IRQ);
828 object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines",
829 2 * ARRAY_SIZE(mms->uart),
830 &error_fatal);
831 qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal);
832 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0,
833 get_sse_irq_in(mms, mmc->uart_overflow_irq));
834
835
836
837
838
839
840
841
842
843
844
845
846 const PPCInfo an505_ppcs[] = { {
847 .name = "apb_ppcexp0",
848 .ports = {
849 { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 },
850 { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 },
851 { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 },
852 },
853 }, {
854 .name = "apb_ppcexp1",
855 .ports = {
856 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51 } },
857 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52 } },
858 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53 } },
859 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54 } },
860 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55 } },
861 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, { 32, 33, 42 } },
862 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, { 34, 35, 43 } },
863 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, { 36, 37, 44 } },
864 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, { 38, 39, 45 } },
865 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, { 40, 41, 46 } },
866 { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 },
867 { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 },
868 { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 },
869 { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 },
870 },
871 }, {
872 .name = "apb_ppcexp2",
873 .ports = {
874 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 },
875 { "i2s-audio", make_unimp_dev, &mms->i2s_audio,
876 0x40301000, 0x1000 },
877 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 },
878 },
879 }, {
880 .name = "ahb_ppcexp0",
881 .ports = {
882 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 },
883 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 },
884 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 },
885 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 },
886 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 },
887 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000, { 48 } },
888 },
889 }, {
890 .name = "ahb_ppcexp1",
891 .ports = {
892 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58, 56, 57 } },
893 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61, 59, 60 } },
894 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64, 62, 63 } },
895 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67, 65, 66 } },
896 },
897 },
898 };
899
900 const PPCInfo an524_ppcs[] = { {
901 .name = "apb_ppcexp0",
902 .ports = {
903 { "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 },
904 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 },
905 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 },
906 },
907 }, {
908 .name = "apb_ppcexp1",
909 .ports = {
910 { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000 },
911 { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000 },
912 { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52 } },
913 { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53 } },
914 { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54 } },
915 { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000 },
916 { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000 },
917 { },
918 { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000 },
919 },
920 }, {
921 .name = "apb_ppcexp2",
922 .ports = {
923 { "scc", make_scc, &mms->scc, 0x41300000, 0x1000 },
924 { "i2s-audio", make_unimp_dev, &mms->i2s_audio,
925 0x41301000, 0x1000 },
926 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 },
927 { "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, { 32, 33, 42 } },
928 { "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, { 34, 35, 43 } },
929 { "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, { 36, 37, 44 } },
930 { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, { 38, 39, 45 } },
931 { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, { 40, 41, 46 } },
932 { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, { 124, 125, 126 } },
933
934 { },
935 { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 },
936 { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 },
937 },
938 }, {
939 .name = "ahb_ppcexp0",
940 .ports = {
941 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 },
942 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 },
943 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 },
944 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 },
945 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 48 } },
946 },
947 },
948 };
949
950 const PPCInfo an547_ppcs[] = { {
951 .name = "apb_ppcexp0",
952 .ports = {
953 { "ssram-mpc", make_mpc, &mms->mpc[0], 0x57000000, 0x1000 },
954 { "qspi-mpc", make_mpc, &mms->mpc[1], 0x57001000, 0x1000 },
955 { "ddr-mpc", make_mpc, &mms->mpc[2], 0x57002000, 0x1000 },
956 },
957 }, {
958 .name = "apb_ppcexp1",
959 .ports = {
960 { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000 },
961 { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000 },
962 { "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53 } },
963 { "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54 } },
964 { "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55 } },
965 { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000 },
966 { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000 },
967 { },
968 { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000 },
969 },
970 }, {
971 .name = "apb_ppcexp2",
972 .ports = {
973 { "scc", make_scc, &mms->scc, 0x49300000, 0x1000 },
974 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 0x49301000, 0x1000 },
975 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x49302000, 0x1000 },
976 { "uart0", make_uart, &mms->uart[0], 0x49303000, 0x1000, { 33, 34, 43 } },
977 { "uart1", make_uart, &mms->uart[1], 0x49304000, 0x1000, { 35, 36, 44 } },
978 { "uart2", make_uart, &mms->uart[2], 0x49305000, 0x1000, { 37, 38, 45 } },
979 { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, { 39, 40, 46 } },
980 { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, { 41, 42, 47 } },
981 { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, { 125, 126, 127 } },
982
983 { },
984 { "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 },
985 { "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 },
986 },
987 }, {
988 .name = "ahb_ppcexp0",
989 .ports = {
990 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 },
991 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 },
992 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 },
993 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 },
994 { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } },
995 },
996 },
997 };
998
999 switch (mmc->fpga_type) {
1000 case FPGA_AN505:
1001 case FPGA_AN521:
1002 ppcs = an505_ppcs;
1003 num_ppcs = ARRAY_SIZE(an505_ppcs);
1004 break;
1005 case FPGA_AN524:
1006 ppcs = an524_ppcs;
1007 num_ppcs = ARRAY_SIZE(an524_ppcs);
1008 break;
1009 case FPGA_AN547:
1010 ppcs = an547_ppcs;
1011 num_ppcs = ARRAY_SIZE(an547_ppcs);
1012 break;
1013 default:
1014 g_assert_not_reached();
1015 }
1016
1017 for (i = 0; i < num_ppcs; i++) {
1018 const PPCInfo *ppcinfo = &ppcs[i];
1019 TZPPC *ppc = &mms->ppc[i];
1020 DeviceState *ppcdev;
1021 int port;
1022 char *gpioname;
1023
1024 object_initialize_child(OBJECT(machine), ppcinfo->name, ppc,
1025 TYPE_TZ_PPC);
1026 ppcdev = DEVICE(ppc);
1027
1028 for (port = 0; port < TZ_NUM_PORTS; port++) {
1029 const PPCPortInfo *pinfo = &ppcinfo->ports[port];
1030 MemoryRegion *mr;
1031 char *portname;
1032
1033 if (!pinfo->devfn) {
1034 continue;
1035 }
1036
1037 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size,
1038 pinfo->irqs);
1039 portname = g_strdup_printf("port[%d]", port);
1040 object_property_set_link(OBJECT(ppc), portname, OBJECT(mr),
1041 &error_fatal);
1042 g_free(portname);
1043 }
1044
1045 sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal);
1046
1047 for (port = 0; port < TZ_NUM_PORTS; port++) {
1048 const PPCPortInfo *pinfo = &ppcinfo->ports[port];
1049
1050 if (!pinfo->devfn) {
1051 continue;
1052 }
1053 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr);
1054
1055 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name);
1056 qdev_connect_gpio_out_named(iotkitdev, gpioname, port,
1057 qdev_get_gpio_in_named(ppcdev,
1058 "cfg_nonsec",
1059 port));
1060 g_free(gpioname);
1061 gpioname = g_strdup_printf("%s_ap", ppcinfo->name);
1062 qdev_connect_gpio_out_named(iotkitdev, gpioname, port,
1063 qdev_get_gpio_in_named(ppcdev,
1064 "cfg_ap", port));
1065 g_free(gpioname);
1066 }
1067
1068 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name);
1069 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0,
1070 qdev_get_gpio_in_named(ppcdev,
1071 "irq_enable", 0));
1072 g_free(gpioname);
1073 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name);
1074 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0,
1075 qdev_get_gpio_in_named(ppcdev,
1076 "irq_clear", 0));
1077 g_free(gpioname);
1078 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name);
1079 qdev_connect_gpio_out_named(ppcdev, "irq", 0,
1080 qdev_get_gpio_in_named(iotkitdev,
1081 gpioname, 0));
1082 g_free(gpioname);
1083
1084 qdev_connect_gpio_out(dev_splitter, i,
1085 qdev_get_gpio_in_named(ppcdev,
1086 "cfg_sec_resp", 0));
1087 }
1088
1089 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000);
1090
1091 if (mmc->fpga_type == FPGA_AN547) {
1092 create_unimplemented_device("U55 timing adapter 0", 0x48102000, 0x1000);
1093 create_unimplemented_device("U55 timing adapter 1", 0x48103000, 0x1000);
1094 }
1095
1096 create_non_mpc_ram(mms);
1097
1098 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
1099 boot_ram_size(mms));
1100}
1101
1102static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address,
1103 int *iregion, bool *exempt, bool *ns, bool *nsc)
1104{
1105
1106
1107
1108
1109
1110
1111 int region = extract32(address, 28, 4);
1112
1113 *ns = !(region & 1);
1114 *nsc = false;
1115
1116 *exempt = (address & 0xeff00000) == 0xe0000000;
1117 *iregion = region;
1118}
1119
1120static void mps2tz_class_init(ObjectClass *oc, void *data)
1121{
1122 MachineClass *mc = MACHINE_CLASS(oc);
1123 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
1124
1125 mc->init = mps2tz_common_init;
1126 iic->check = mps2_tz_idau_check;
1127}
1128
1129static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
1130{
1131
1132
1133
1134
1135 MachineClass *mc = MACHINE_CLASS(mmc);
1136 const RAMInfo *p;
1137
1138 for (p = mmc->raminfo; p->name; p++) {
1139 if (p->mrindex < 0) {
1140
1141 mc->default_ram_size = p->size;
1142 mc->default_ram_id = p->name;
1143 return;
1144 }
1145 }
1146 g_assert_not_reached();
1147}
1148
1149static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
1150{
1151 MachineClass *mc = MACHINE_CLASS(oc);
1152 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
1153
1154 mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33";
1155 mc->default_cpus = 1;
1156 mc->min_cpus = mc->default_cpus;
1157 mc->max_cpus = mc->default_cpus;
1158 mmc->fpga_type = FPGA_AN505;
1159 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
1160 mmc->scc_id = 0x41045050;
1161 mmc->sysclk_frq = 20 * 1000 * 1000;
1162 mmc->apb_periph_frq = mmc->sysclk_frq;
1163 mmc->oscclk = an505_oscclk;
1164 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk);
1165 mmc->fpgaio_num_leds = 2;
1166 mmc->fpgaio_has_switches = false;
1167 mmc->fpgaio_has_dbgctrl = false;
1168 mmc->numirq = 92;
1169 mmc->uart_overflow_irq = 47;
1170 mmc->init_svtor = 0x10000000;
1171 mmc->raminfo = an505_raminfo;
1172 mmc->armsse_type = TYPE_IOTKIT;
1173 mps2tz_set_default_ram_info(mmc);
1174}
1175
1176static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
1177{
1178 MachineClass *mc = MACHINE_CLASS(oc);
1179 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
1180
1181 mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33";
1182 mc->default_cpus = 2;
1183 mc->min_cpus = mc->default_cpus;
1184 mc->max_cpus = mc->default_cpus;
1185 mmc->fpga_type = FPGA_AN521;
1186 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
1187 mmc->scc_id = 0x41045210;
1188 mmc->sysclk_frq = 20 * 1000 * 1000;
1189 mmc->apb_periph_frq = mmc->sysclk_frq;
1190 mmc->oscclk = an505_oscclk;
1191 mmc->len_oscclk = ARRAY_SIZE(an505_oscclk);
1192 mmc->fpgaio_num_leds = 2;
1193 mmc->fpgaio_has_switches = false;
1194 mmc->fpgaio_has_dbgctrl = false;
1195 mmc->numirq = 92;
1196 mmc->uart_overflow_irq = 47;
1197 mmc->init_svtor = 0x10000000;
1198 mmc->raminfo = an505_raminfo;
1199 mmc->armsse_type = TYPE_SSE200;
1200 mps2tz_set_default_ram_info(mmc);
1201}
1202
1203static void mps3tz_an524_class_init(ObjectClass *oc, void *data)
1204{
1205 MachineClass *mc = MACHINE_CLASS(oc);
1206 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
1207
1208 mc->desc = "ARM MPS3 with AN524 FPGA image for dual Cortex-M33";
1209 mc->default_cpus = 2;
1210 mc->min_cpus = mc->default_cpus;
1211 mc->max_cpus = mc->default_cpus;
1212 mmc->fpga_type = FPGA_AN524;
1213 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
1214 mmc->scc_id = 0x41045240;
1215 mmc->sysclk_frq = 32 * 1000 * 1000;
1216 mmc->apb_periph_frq = mmc->sysclk_frq;
1217 mmc->oscclk = an524_oscclk;
1218 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk);
1219 mmc->fpgaio_num_leds = 10;
1220 mmc->fpgaio_has_switches = true;
1221 mmc->fpgaio_has_dbgctrl = false;
1222 mmc->numirq = 95;
1223 mmc->uart_overflow_irq = 47;
1224 mmc->init_svtor = 0x10000000;
1225 mmc->raminfo = an524_raminfo;
1226 mmc->armsse_type = TYPE_SSE200;
1227 mps2tz_set_default_ram_info(mmc);
1228}
1229
1230static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
1231{
1232 MachineClass *mc = MACHINE_CLASS(oc);
1233 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
1234
1235 mc->desc = "ARM MPS3 with AN547 FPGA image for Cortex-M55";
1236 mc->default_cpus = 1;
1237 mc->min_cpus = mc->default_cpus;
1238 mc->max_cpus = mc->default_cpus;
1239 mmc->fpga_type = FPGA_AN547;
1240 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m55");
1241 mmc->scc_id = 0x41055470;
1242 mmc->sysclk_frq = 32 * 1000 * 1000;
1243 mmc->apb_periph_frq = 25 * 1000 * 1000;
1244 mmc->oscclk = an524_oscclk;
1245 mmc->len_oscclk = ARRAY_SIZE(an524_oscclk);
1246 mmc->fpgaio_num_leds = 10;
1247 mmc->fpgaio_has_switches = true;
1248 mmc->fpgaio_has_dbgctrl = true;
1249 mmc->numirq = 96;
1250 mmc->uart_overflow_irq = 48;
1251 mmc->init_svtor = 0x00000000;
1252 mmc->raminfo = an547_raminfo;
1253 mmc->armsse_type = TYPE_SSE300;
1254 mps2tz_set_default_ram_info(mmc);
1255}
1256
1257static const TypeInfo mps2tz_info = {
1258 .name = TYPE_MPS2TZ_MACHINE,
1259 .parent = TYPE_MACHINE,
1260 .abstract = true,
1261 .instance_size = sizeof(MPS2TZMachineState),
1262 .class_size = sizeof(MPS2TZMachineClass),
1263 .class_init = mps2tz_class_init,
1264 .interfaces = (InterfaceInfo[]) {
1265 { TYPE_IDAU_INTERFACE },
1266 { }
1267 },
1268};
1269
1270static const TypeInfo mps2tz_an505_info = {
1271 .name = TYPE_MPS2TZ_AN505_MACHINE,
1272 .parent = TYPE_MPS2TZ_MACHINE,
1273 .class_init = mps2tz_an505_class_init,
1274};
1275
1276static const TypeInfo mps2tz_an521_info = {
1277 .name = TYPE_MPS2TZ_AN521_MACHINE,
1278 .parent = TYPE_MPS2TZ_MACHINE,
1279 .class_init = mps2tz_an521_class_init,
1280};
1281
1282static const TypeInfo mps3tz_an524_info = {
1283 .name = TYPE_MPS3TZ_AN524_MACHINE,
1284 .parent = TYPE_MPS2TZ_MACHINE,
1285 .class_init = mps3tz_an524_class_init,
1286};
1287
1288static const TypeInfo mps3tz_an547_info = {
1289 .name = TYPE_MPS3TZ_AN547_MACHINE,
1290 .parent = TYPE_MPS2TZ_MACHINE,
1291 .class_init = mps3tz_an547_class_init,
1292};
1293
1294static void mps2tz_machine_init(void)
1295{
1296 type_register_static(&mps2tz_info);
1297 type_register_static(&mps2tz_an505_info);
1298 type_register_static(&mps2tz_an521_info);
1299 type_register_static(&mps3tz_an524_info);
1300 type_register_static(&mps3tz_an547_info);
1301}
1302
1303type_init(mps2tz_machine_init);
1304