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27#include "qemu/osdep.h"
28#include "qemu/units.h"
29#include "qemu/cutils.h"
30#include "qapi/error.h"
31#include "qemu/error-report.h"
32#include "hw/arm/boot.h"
33#include "hw/arm/armv7m.h"
34#include "hw/or-irq.h"
35#include "hw/boards.h"
36#include "exec/address-spaces.h"
37#include "sysemu/sysemu.h"
38#include "hw/misc/unimp.h"
39#include "hw/char/cmsdk-apb-uart.h"
40#include "hw/timer/cmsdk-apb-timer.h"
41#include "hw/timer/cmsdk-apb-dualtimer.h"
42#include "hw/misc/mps2-scc.h"
43#include "hw/misc/mps2-fpgaio.h"
44#include "hw/ssi/pl022.h"
45#include "hw/i2c/arm_sbcon_i2c.h"
46#include "hw/net/lan9118.h"
47#include "net/net.h"
48#include "hw/watchdog/cmsdk-apb-watchdog.h"
49#include "hw/qdev-clock.h"
50#include "qom/object.h"
51
52typedef enum MPS2FPGAType {
53 FPGA_AN385,
54 FPGA_AN386,
55 FPGA_AN500,
56 FPGA_AN511,
57} MPS2FPGAType;
58
59struct MPS2MachineClass {
60 MachineClass parent;
61 MPS2FPGAType fpga_type;
62 uint32_t scc_id;
63 bool has_block_ram;
64 hwaddr ethernet_base;
65 hwaddr psram_base;
66};
67
68struct MPS2MachineState {
69 MachineState parent;
70
71 ARMv7MState armv7m;
72 MemoryRegion ssram1;
73 MemoryRegion ssram1_m;
74 MemoryRegion ssram23;
75 MemoryRegion ssram23_m;
76 MemoryRegion blockram;
77 MemoryRegion blockram_m1;
78 MemoryRegion blockram_m2;
79 MemoryRegion blockram_m3;
80 MemoryRegion sram;
81
82 MPS2SCC scc;
83 MPS2FPGAIO fpgaio;
84
85 CMSDKAPBDualTimer dualtimer;
86 CMSDKAPBWatchdog watchdog;
87 CMSDKAPBTimer timer[2];
88 Clock *sysclk;
89};
90
91#define TYPE_MPS2_MACHINE "mps2"
92#define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
93#define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386")
94#define TYPE_MPS2_AN500_MACHINE MACHINE_TYPE_NAME("mps2-an500")
95#define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
96
97OBJECT_DECLARE_TYPE(MPS2MachineState, MPS2MachineClass, MPS2_MACHINE)
98
99
100#define SYSCLK_FRQ 25000000
101
102
103
104
105static void make_ram(MemoryRegion *mr, const char *name,
106 hwaddr base, hwaddr size)
107{
108 memory_region_init_ram(mr, NULL, name, size, &error_fatal);
109 memory_region_add_subregion(get_system_memory(), base, mr);
110}
111
112
113
114
115static void make_ram_alias(MemoryRegion *mr, const char *name,
116 MemoryRegion *orig, hwaddr base)
117{
118 memory_region_init_alias(mr, NULL, name, orig, 0,
119 memory_region_size(orig));
120 memory_region_add_subregion(get_system_memory(), base, mr);
121}
122
123static void mps2_common_init(MachineState *machine)
124{
125 MPS2MachineState *mms = MPS2_MACHINE(machine);
126 MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);
127 MemoryRegion *system_memory = get_system_memory();
128 MachineClass *mc = MACHINE_GET_CLASS(machine);
129 DeviceState *armv7m, *sccdev;
130 int i;
131
132 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
133 error_report("This board can only be used with CPU %s",
134 mc->default_cpu_type);
135 exit(1);
136 }
137
138 if (machine->ram_size != mc->default_ram_size) {
139 char *sz = size_to_str(mc->default_ram_size);
140 error_report("Invalid RAM size, should be %s", sz);
141 g_free(sz);
142 exit(EXIT_FAILURE);
143 }
144
145
146 mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
147 clock_set_hz(mms->sysclk, SYSCLK_FRQ);
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179
180 memory_region_add_subregion(system_memory, mmc->psram_base, machine->ram);
181
182 if (mmc->has_block_ram) {
183 make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000);
184 make_ram_alias(&mms->blockram_m1, "mps.blockram_m1",
185 &mms->blockram, 0x01004000);
186 make_ram_alias(&mms->blockram_m2, "mps.blockram_m2",
187 &mms->blockram, 0x01008000);
188 make_ram_alias(&mms->blockram_m3, "mps.blockram_m3",
189 &mms->blockram, 0x0100c000);
190 }
191
192 switch (mmc->fpga_type) {
193 case FPGA_AN385:
194 case FPGA_AN386:
195 case FPGA_AN500:
196 make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
197 make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
198 make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
199 make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
200 &mms->ssram23, 0x20400000);
201 break;
202 case FPGA_AN511:
203 make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000);
204 make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000);
205 make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000);
206 make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000);
207 break;
208 default:
209 g_assert_not_reached();
210 }
211
212 object_initialize_child(OBJECT(mms), "armv7m", &mms->armv7m, TYPE_ARMV7M);
213 armv7m = DEVICE(&mms->armv7m);
214 switch (mmc->fpga_type) {
215 case FPGA_AN385:
216 case FPGA_AN386:
217 case FPGA_AN500:
218 qdev_prop_set_uint32(armv7m, "num-irq", 32);
219 break;
220 case FPGA_AN511:
221 qdev_prop_set_uint32(armv7m, "num-irq", 64);
222 break;
223 default:
224 g_assert_not_reached();
225 }
226 qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
227 qdev_prop_set_bit(armv7m, "enable-bitband", true);
228 object_property_set_link(OBJECT(&mms->armv7m), "memory",
229 OBJECT(system_memory), &error_abort);
230 sysbus_realize(SYS_BUS_DEVICE(&mms->armv7m), &error_fatal);
231
232 create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
233 create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
234 create_unimplemented_device("Block RAM", 0x01000000, 0x00010000);
235 create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000);
236 create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000);
237 create_unimplemented_device("PSRAM", 0x21000000, 0x01000000);
238
239
240
241
242 create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
243 0x40000000, 0x00010000);
244 create_unimplemented_device("CMSDK AHB peripheral region @0x40010000",
245 0x40010000, 0x00010000);
246 create_unimplemented_device("Extra peripheral region @0x40020000",
247 0x40020000, 0x00010000);
248
249 create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
250 create_unimplemented_device("VGA", 0x41000000, 0x0200000);
251
252 switch (mmc->fpga_type) {
253 case FPGA_AN385:
254 case FPGA_AN386:
255 case FPGA_AN500:
256 {
257
258
259
260 Object *orgate;
261 DeviceState *orgate_dev;
262
263 orgate = object_new(TYPE_OR_IRQ);
264 object_property_set_int(orgate, "num-lines", 6, &error_fatal);
265 qdev_realize(DEVICE(orgate), NULL, &error_fatal);
266 orgate_dev = DEVICE(orgate);
267 qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
268
269 for (i = 0; i < 5; i++) {
270 static const hwaddr uartbase[] = {0x40004000, 0x40005000,
271 0x40006000, 0x40007000,
272 0x40009000};
273
274 static const int uartirq[] = {0, 2, 4, 18, 20};
275 qemu_irq txovrint = NULL, rxovrint = NULL;
276
277 if (i < 3) {
278 txovrint = qdev_get_gpio_in(orgate_dev, i * 2);
279 rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1);
280 }
281
282 cmsdk_apb_uart_create(uartbase[i],
283 qdev_get_gpio_in(armv7m, uartirq[i] + 1),
284 qdev_get_gpio_in(armv7m, uartirq[i]),
285 txovrint, rxovrint,
286 NULL,
287 serial_hd(i), SYSCLK_FRQ);
288 }
289 break;
290 }
291 case FPGA_AN511:
292 {
293
294
295
296 Object *orgate;
297 DeviceState *orgate_dev;
298
299 orgate = object_new(TYPE_OR_IRQ);
300 object_property_set_int(orgate, "num-lines", 10, &error_fatal);
301 qdev_realize(DEVICE(orgate), NULL, &error_fatal);
302 orgate_dev = DEVICE(orgate);
303 qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
304
305 for (i = 0; i < 5; i++) {
306
307 static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56};
308 static const hwaddr uartbase[] = {0x40004000, 0x40005000,
309 0x4002c000, 0x4002d000,
310 0x4002e000};
311 Object *txrx_orgate;
312 DeviceState *txrx_orgate_dev;
313
314 txrx_orgate = object_new(TYPE_OR_IRQ);
315 object_property_set_int(txrx_orgate, "num-lines", 2, &error_fatal);
316 qdev_realize(DEVICE(txrx_orgate), NULL, &error_fatal);
317 txrx_orgate_dev = DEVICE(txrx_orgate);
318 qdev_connect_gpio_out(txrx_orgate_dev, 0,
319 qdev_get_gpio_in(armv7m, uart_txrx_irqno[i]));
320 cmsdk_apb_uart_create(uartbase[i],
321 qdev_get_gpio_in(txrx_orgate_dev, 0),
322 qdev_get_gpio_in(txrx_orgate_dev, 1),
323 qdev_get_gpio_in(orgate_dev, i * 2),
324 qdev_get_gpio_in(orgate_dev, i * 2 + 1),
325 NULL,
326 serial_hd(i), SYSCLK_FRQ);
327 }
328 break;
329 }
330 default:
331 g_assert_not_reached();
332 }
333 for (i = 0; i < 4; i++) {
334 static const hwaddr gpiobase[] = {0x40010000, 0x40011000,
335 0x40012000, 0x40013000};
336 create_unimplemented_device("cmsdk-ahb-gpio", gpiobase[i], 0x1000);
337 }
338
339
340 for (i = 0; i < ARRAY_SIZE(mms->timer); i++) {
341 g_autofree char *name = g_strdup_printf("timer%d", i);
342 hwaddr base = 0x40000000 + i * 0x1000;
343 int irqno = 8 + i;
344 SysBusDevice *sbd;
345
346 object_initialize_child(OBJECT(mms), name, &mms->timer[i],
347 TYPE_CMSDK_APB_TIMER);
348 sbd = SYS_BUS_DEVICE(&mms->timer[i]);
349 qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk);
350 sysbus_realize_and_unref(sbd, &error_fatal);
351 sysbus_mmio_map(sbd, 0, base);
352 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno));
353 }
354
355 object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
356 TYPE_CMSDK_APB_DUALTIMER);
357 qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk);
358 sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
359 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
360 qdev_get_gpio_in(armv7m, 10));
361 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
362 object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
363 TYPE_CMSDK_APB_WATCHDOG);
364 qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk);
365 sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
366 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
367 qdev_get_gpio_in_named(armv7m, "NMI", 0));
368 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0x40008000);
369
370
371 object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
372 sccdev = DEVICE(&mms->scc);
373 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
374 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
375 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
376
377 qdev_prop_set_uint32(sccdev, "len-oscclk", 3);
378 qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000);
379 qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000);
380 qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000);
381 sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
382 sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000);
383 object_initialize_child(OBJECT(mms), "fpgaio",
384 &mms->fpgaio, TYPE_MPS2_FPGAIO);
385 qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000);
386 sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
387 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000);
388 sysbus_create_simple(TYPE_PL022, 0x40025000,
389 qdev_get_gpio_in(armv7m, 22));
390 for (i = 0; i < 2; i++) {
391 static const int spi_irqno[] = {11, 24};
392 static const hwaddr spibase[] = {0x40020000,
393 0x40021000,
394 0x40026000,
395 0x40027000};
396 DeviceState *orgate_dev;
397 Object *orgate;
398 int j;
399
400 orgate = object_new(TYPE_OR_IRQ);
401 object_property_set_int(orgate, "num-lines", 2, &error_fatal);
402 orgate_dev = DEVICE(orgate);
403 qdev_realize(orgate_dev, NULL, &error_fatal);
404 qdev_connect_gpio_out(orgate_dev, 0,
405 qdev_get_gpio_in(armv7m, spi_irqno[i]));
406 for (j = 0; j < 2; j++) {
407 sysbus_create_simple(TYPE_PL022, spibase[2 * i + j],
408 qdev_get_gpio_in(orgate_dev, j));
409 }
410 }
411 for (i = 0; i < 4; i++) {
412 static const hwaddr i2cbase[] = {0x40022000,
413 0x40023000,
414 0x40029000,
415 0x4002a000};
416 sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL);
417 }
418 create_unimplemented_device("i2s", 0x40024000, 0x400);
419
420
421
422
423 lan9118_init(&nd_table[0], mmc->ethernet_base,
424 qdev_get_gpio_in(armv7m,
425 mmc->fpga_type == FPGA_AN511 ? 47 : 13));
426
427 system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
428
429 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
430 0x400000);
431}
432
433static void mps2_class_init(ObjectClass *oc, void *data)
434{
435 MachineClass *mc = MACHINE_CLASS(oc);
436
437 mc->init = mps2_common_init;
438 mc->max_cpus = 1;
439 mc->default_ram_size = 16 * MiB;
440 mc->default_ram_id = "mps.ram";
441}
442
443static void mps2_an385_class_init(ObjectClass *oc, void *data)
444{
445 MachineClass *mc = MACHINE_CLASS(oc);
446 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
447
448 mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
449 mmc->fpga_type = FPGA_AN385;
450 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
451 mmc->scc_id = 0x41043850;
452 mmc->psram_base = 0x21000000;
453 mmc->ethernet_base = 0x40200000;
454 mmc->has_block_ram = true;
455}
456
457static void mps2_an386_class_init(ObjectClass *oc, void *data)
458{
459 MachineClass *mc = MACHINE_CLASS(oc);
460 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
461
462 mc->desc = "ARM MPS2 with AN386 FPGA image for Cortex-M4";
463 mmc->fpga_type = FPGA_AN386;
464 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
465 mmc->scc_id = 0x41043860;
466 mmc->psram_base = 0x21000000;
467 mmc->ethernet_base = 0x40200000;
468 mmc->has_block_ram = true;
469}
470
471static void mps2_an500_class_init(ObjectClass *oc, void *data)
472{
473 MachineClass *mc = MACHINE_CLASS(oc);
474 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
475
476 mc->desc = "ARM MPS2 with AN500 FPGA image for Cortex-M7";
477 mmc->fpga_type = FPGA_AN500;
478 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m7");
479 mmc->scc_id = 0x41045000;
480 mmc->psram_base = 0x60000000;
481 mmc->ethernet_base = 0xa0000000;
482 mmc->has_block_ram = false;
483}
484
485static void mps2_an511_class_init(ObjectClass *oc, void *data)
486{
487 MachineClass *mc = MACHINE_CLASS(oc);
488 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
489
490 mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
491 mmc->fpga_type = FPGA_AN511;
492 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
493 mmc->scc_id = 0x41045110;
494 mmc->psram_base = 0x21000000;
495 mmc->ethernet_base = 0x40200000;
496 mmc->has_block_ram = false;
497}
498
499static const TypeInfo mps2_info = {
500 .name = TYPE_MPS2_MACHINE,
501 .parent = TYPE_MACHINE,
502 .abstract = true,
503 .instance_size = sizeof(MPS2MachineState),
504 .class_size = sizeof(MPS2MachineClass),
505 .class_init = mps2_class_init,
506};
507
508static const TypeInfo mps2_an385_info = {
509 .name = TYPE_MPS2_AN385_MACHINE,
510 .parent = TYPE_MPS2_MACHINE,
511 .class_init = mps2_an385_class_init,
512};
513
514static const TypeInfo mps2_an386_info = {
515 .name = TYPE_MPS2_AN386_MACHINE,
516 .parent = TYPE_MPS2_MACHINE,
517 .class_init = mps2_an386_class_init,
518};
519
520static const TypeInfo mps2_an500_info = {
521 .name = TYPE_MPS2_AN500_MACHINE,
522 .parent = TYPE_MPS2_MACHINE,
523 .class_init = mps2_an500_class_init,
524};
525
526static const TypeInfo mps2_an511_info = {
527 .name = TYPE_MPS2_AN511_MACHINE,
528 .parent = TYPE_MPS2_MACHINE,
529 .class_init = mps2_an511_class_init,
530};
531
532static void mps2_machine_init(void)
533{
534 type_register_static(&mps2_info);
535 type_register_static(&mps2_an385_info);
536 type_register_static(&mps2_an386_info);
537 type_register_static(&mps2_an500_info);
538 type_register_static(&mps2_an511_info);
539}
540
541type_init(mps2_machine_init);
542