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10#include "qemu/osdep.h"
11#include "qapi/error.h"
12#include "hw/sysbus.h"
13#include "hw/ssi/ssi.h"
14#include "hw/arm/boot.h"
15#include "qemu/timer.h"
16#include "hw/i2c/i2c.h"
17#include "net/net.h"
18#include "hw/boards.h"
19#include "qemu/log.h"
20#include "exec/address-spaces.h"
21#include "sysemu/sysemu.h"
22#include "hw/arm/armv7m.h"
23#include "hw/char/pl011.h"
24#include "hw/input/gamepad.h"
25#include "hw/irq.h"
26#include "hw/watchdog/cmsdk-apb-watchdog.h"
27#include "migration/vmstate.h"
28#include "hw/misc/unimp.h"
29#include "hw/qdev-clock.h"
30#include "cpu.h"
31#include "qom/object.h"
32
33#define GPIO_A 0
34#define GPIO_B 1
35#define GPIO_C 2
36#define GPIO_D 3
37#define GPIO_E 4
38#define GPIO_F 5
39#define GPIO_G 6
40
41#define BP_OLED_I2C 0x01
42#define BP_OLED_SSI 0x02
43#define BP_GAMEPAD 0x04
44
45#define NUM_IRQ_LINES 64
46
47typedef const struct {
48 const char *name;
49 uint32_t did0;
50 uint32_t did1;
51 uint32_t dc0;
52 uint32_t dc1;
53 uint32_t dc2;
54 uint32_t dc3;
55 uint32_t dc4;
56 uint32_t peripherals;
57} stellaris_board_info;
58
59
60
61#define TYPE_STELLARIS_GPTM "stellaris-gptm"
62OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM)
63
64struct gptm_state {
65 SysBusDevice parent_obj;
66
67 MemoryRegion iomem;
68 uint32_t config;
69 uint32_t mode[2];
70 uint32_t control;
71 uint32_t state;
72 uint32_t mask;
73 uint32_t load[2];
74 uint32_t match[2];
75 uint32_t prescale[2];
76 uint32_t match_prescale[2];
77 uint32_t rtc;
78 int64_t tick[2];
79 struct gptm_state *opaque[2];
80 QEMUTimer *timer[2];
81
82 qemu_irq trigger;
83 qemu_irq irq;
84};
85
86static void gptm_update_irq(gptm_state *s)
87{
88 int level;
89 level = (s->state & s->mask) != 0;
90 qemu_set_irq(s->irq, level);
91}
92
93static void gptm_stop(gptm_state *s, int n)
94{
95 timer_del(s->timer[n]);
96}
97
98static void gptm_reload(gptm_state *s, int n, int reset)
99{
100 int64_t tick;
101 if (reset)
102 tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
103 else
104 tick = s->tick[n];
105
106 if (s->config == 0) {
107
108 uint32_t count;
109 count = s->load[0] | (s->load[1] << 16);
110 tick += (int64_t)count * system_clock_scale;
111 } else if (s->config == 1) {
112
113 tick += NANOSECONDS_PER_SECOND;
114 } else if (s->mode[n] == 0xa) {
115
116 } else {
117 qemu_log_mask(LOG_UNIMP,
118 "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
119 s->mode[n]);
120 return;
121 }
122 s->tick[n] = tick;
123 timer_mod(s->timer[n], tick);
124}
125
126static void gptm_tick(void *opaque)
127{
128 gptm_state **p = (gptm_state **)opaque;
129 gptm_state *s;
130 int n;
131
132 s = *p;
133 n = p - s->opaque;
134 if (s->config == 0) {
135 s->state |= 1;
136 if ((s->control & 0x20)) {
137
138 qemu_irq_pulse(s->trigger);
139 }
140 if (s->mode[0] & 1) {
141
142 s->control &= ~1;
143 } else {
144
145 gptm_reload(s, 0, 0);
146 }
147 } else if (s->config == 1) {
148
149 uint32_t match;
150 s->rtc++;
151 match = s->match[0] | (s->match[1] << 16);
152 if (s->rtc > match)
153 s->rtc = 0;
154 if (s->rtc == 0) {
155 s->state |= 8;
156 }
157 gptm_reload(s, 0, 0);
158 } else if (s->mode[n] == 0xa) {
159
160 } else {
161 qemu_log_mask(LOG_UNIMP,
162 "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
163 s->mode[n]);
164 }
165 gptm_update_irq(s);
166}
167
168static uint64_t gptm_read(void *opaque, hwaddr offset,
169 unsigned size)
170{
171 gptm_state *s = (gptm_state *)opaque;
172
173 switch (offset) {
174 case 0x00:
175 return s->config;
176 case 0x04:
177 return s->mode[0];
178 case 0x08:
179 return s->mode[1];
180 case 0x0c:
181 return s->control;
182 case 0x18:
183 return s->mask;
184 case 0x1c:
185 return s->state;
186 case 0x20:
187 return s->state & s->mask;
188 case 0x24:
189 return 0;
190 case 0x28:
191 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
192 case 0x2c:
193 return s->load[1];
194 case 0x30:
195 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
196 case 0x34:
197 return s->match[1];
198 case 0x38:
199 return s->prescale[0];
200 case 0x3c:
201 return s->prescale[1];
202 case 0x40:
203 return s->match_prescale[0];
204 case 0x44:
205 return s->match_prescale[1];
206 case 0x48:
207 if (s->config == 1) {
208 return s->rtc;
209 }
210 qemu_log_mask(LOG_UNIMP,
211 "GPTM: read of TAR but timer read not supported\n");
212 return 0;
213 case 0x4c:
214 qemu_log_mask(LOG_UNIMP,
215 "GPTM: read of TBR but timer read not supported\n");
216 return 0;
217 default:
218 qemu_log_mask(LOG_GUEST_ERROR,
219 "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n",
220 offset);
221 return 0;
222 }
223}
224
225static void gptm_write(void *opaque, hwaddr offset,
226 uint64_t value, unsigned size)
227{
228 gptm_state *s = (gptm_state *)opaque;
229 uint32_t oldval;
230
231
232
233
234 switch (offset) {
235 case 0x00:
236 s->config = value;
237 break;
238 case 0x04:
239 s->mode[0] = value;
240 break;
241 case 0x08:
242 s->mode[1] = value;
243 break;
244 case 0x0c:
245 oldval = s->control;
246 s->control = value;
247
248 if ((oldval ^ value) & 1) {
249 if (value & 1) {
250 gptm_reload(s, 0, 1);
251 } else {
252 gptm_stop(s, 0);
253 }
254 }
255 if (((oldval ^ value) & 0x100) && s->config >= 4) {
256 if (value & 0x100) {
257 gptm_reload(s, 1, 1);
258 } else {
259 gptm_stop(s, 1);
260 }
261 }
262 break;
263 case 0x18:
264 s->mask = value & 0x77;
265 gptm_update_irq(s);
266 break;
267 case 0x24:
268 s->state &= ~value;
269 break;
270 case 0x28:
271 s->load[0] = value & 0xffff;
272 if (s->config < 4) {
273 s->load[1] = value >> 16;
274 }
275 break;
276 case 0x2c:
277 s->load[1] = value & 0xffff;
278 break;
279 case 0x30:
280 s->match[0] = value & 0xffff;
281 if (s->config < 4) {
282 s->match[1] = value >> 16;
283 }
284 break;
285 case 0x34:
286 s->match[1] = value >> 16;
287 break;
288 case 0x38:
289 s->prescale[0] = value;
290 break;
291 case 0x3c:
292 s->prescale[1] = value;
293 break;
294 case 0x40:
295 s->match_prescale[0] = value;
296 break;
297 case 0x44:
298 s->match_prescale[0] = value;
299 break;
300 default:
301 qemu_log_mask(LOG_GUEST_ERROR,
302 "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n",
303 offset);
304 }
305 gptm_update_irq(s);
306}
307
308static const MemoryRegionOps gptm_ops = {
309 .read = gptm_read,
310 .write = gptm_write,
311 .endianness = DEVICE_NATIVE_ENDIAN,
312};
313
314static const VMStateDescription vmstate_stellaris_gptm = {
315 .name = "stellaris_gptm",
316 .version_id = 1,
317 .minimum_version_id = 1,
318 .fields = (VMStateField[]) {
319 VMSTATE_UINT32(config, gptm_state),
320 VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
321 VMSTATE_UINT32(control, gptm_state),
322 VMSTATE_UINT32(state, gptm_state),
323 VMSTATE_UINT32(mask, gptm_state),
324 VMSTATE_UNUSED(8),
325 VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
326 VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
327 VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
328 VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
329 VMSTATE_UINT32(rtc, gptm_state),
330 VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
331 VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2),
332 VMSTATE_END_OF_LIST()
333 }
334};
335
336static void stellaris_gptm_init(Object *obj)
337{
338 DeviceState *dev = DEVICE(obj);
339 gptm_state *s = STELLARIS_GPTM(obj);
340 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
341
342 sysbus_init_irq(sbd, &s->irq);
343 qdev_init_gpio_out(dev, &s->trigger, 1);
344
345 memory_region_init_io(&s->iomem, obj, &gptm_ops, s,
346 "gptm", 0x1000);
347 sysbus_init_mmio(sbd, &s->iomem);
348
349 s->opaque[0] = s->opaque[1] = s;
350}
351
352static void stellaris_gptm_realize(DeviceState *dev, Error **errp)
353{
354 gptm_state *s = STELLARIS_GPTM(dev);
355 s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
356 s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
357}
358
359
360
361#define TYPE_STELLARIS_SYS "stellaris-sys"
362OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS)
363
364struct ssys_state {
365 SysBusDevice parent_obj;
366
367 MemoryRegion iomem;
368 uint32_t pborctl;
369 uint32_t ldopctl;
370 uint32_t int_status;
371 uint32_t int_mask;
372 uint32_t resc;
373 uint32_t rcc;
374 uint32_t rcc2;
375 uint32_t rcgc[3];
376 uint32_t scgc[3];
377 uint32_t dcgc[3];
378 uint32_t clkvclr;
379 uint32_t ldoarst;
380 qemu_irq irq;
381 Clock *sysclk;
382
383 uint32_t user0;
384 uint32_t user1;
385 uint32_t did0;
386 uint32_t did1;
387 uint32_t dc0;
388 uint32_t dc1;
389 uint32_t dc2;
390 uint32_t dc3;
391 uint32_t dc4;
392};
393
394static void ssys_update(ssys_state *s)
395{
396 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
397}
398
399static uint32_t pllcfg_sandstorm[16] = {
400 0x31c0,
401 0x1ae0,
402 0x18c0,
403 0xd573,
404 0x37a6,
405 0x1ae2,
406 0x0c40,
407 0x98bc,
408 0x935b,
409 0x09c0,
410 0x4dee,
411 0x0c41,
412 0x75db,
413 0x1ae6,
414 0x0600,
415 0x585b
416};
417
418static uint32_t pllcfg_fury[16] = {
419 0x3200,
420 0x1b20,
421 0x1900,
422 0xf42b,
423 0x37e3,
424 0x1b21,
425 0x0c80,
426 0x98ee,
427 0xd5b4,
428 0x0a00,
429 0x4e27,
430 0x1902,
431 0xec1c,
432 0x1b23,
433 0x0640,
434 0xb11c
435};
436
437#define DID0_VER_MASK 0x70000000
438#define DID0_VER_0 0x00000000
439#define DID0_VER_1 0x10000000
440
441#define DID0_CLASS_MASK 0x00FF0000
442#define DID0_CLASS_SANDSTORM 0x00000000
443#define DID0_CLASS_FURY 0x00010000
444
445static int ssys_board_class(const ssys_state *s)
446{
447 uint32_t did0 = s->did0;
448 switch (did0 & DID0_VER_MASK) {
449 case DID0_VER_0:
450 return DID0_CLASS_SANDSTORM;
451 case DID0_VER_1:
452 switch (did0 & DID0_CLASS_MASK) {
453 case DID0_CLASS_SANDSTORM:
454 case DID0_CLASS_FURY:
455 return did0 & DID0_CLASS_MASK;
456 }
457
458 default:
459
460
461
462 g_assert_not_reached();
463 }
464}
465
466static uint64_t ssys_read(void *opaque, hwaddr offset,
467 unsigned size)
468{
469 ssys_state *s = (ssys_state *)opaque;
470
471 switch (offset) {
472 case 0x000:
473 return s->did0;
474 case 0x004:
475 return s->did1;
476 case 0x008:
477 return s->dc0;
478 case 0x010:
479 return s->dc1;
480 case 0x014:
481 return s->dc2;
482 case 0x018:
483 return s->dc3;
484 case 0x01c:
485 return s->dc4;
486 case 0x030:
487 return s->pborctl;
488 case 0x034:
489 return s->ldopctl;
490 case 0x040:
491 return 0;
492 case 0x044:
493 return 0;
494 case 0x048:
495 return 0;
496 case 0x050:
497 return s->int_status;
498 case 0x054:
499 return s->int_mask;
500 case 0x058:
501 return s->int_status & s->int_mask;
502 case 0x05c:
503 return s->resc;
504 case 0x060:
505 return s->rcc;
506 case 0x064:
507 {
508 int xtal;
509 xtal = (s->rcc >> 6) & 0xf;
510 switch (ssys_board_class(s)) {
511 case DID0_CLASS_FURY:
512 return pllcfg_fury[xtal];
513 case DID0_CLASS_SANDSTORM:
514 return pllcfg_sandstorm[xtal];
515 default:
516 g_assert_not_reached();
517 }
518 }
519 case 0x070:
520 return s->rcc2;
521 case 0x100:
522 return s->rcgc[0];
523 case 0x104:
524 return s->rcgc[1];
525 case 0x108:
526 return s->rcgc[2];
527 case 0x110:
528 return s->scgc[0];
529 case 0x114:
530 return s->scgc[1];
531 case 0x118:
532 return s->scgc[2];
533 case 0x120:
534 return s->dcgc[0];
535 case 0x124:
536 return s->dcgc[1];
537 case 0x128:
538 return s->dcgc[2];
539 case 0x150:
540 return s->clkvclr;
541 case 0x160:
542 return s->ldoarst;
543 case 0x1e0:
544 return s->user0;
545 case 0x1e4:
546 return s->user1;
547 default:
548 qemu_log_mask(LOG_GUEST_ERROR,
549 "SSYS: read at bad offset 0x%x\n", (int)offset);
550 return 0;
551 }
552}
553
554static bool ssys_use_rcc2(ssys_state *s)
555{
556 return (s->rcc2 >> 31) & 0x1;
557}
558
559
560
561
562
563
564static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
565{
566
567
568
569
570
571 if (ssys_use_rcc2(s)) {
572 system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
573 } else {
574 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
575 }
576 clock_set_ns(s->sysclk, system_clock_scale);
577 if (propagate_clock) {
578 clock_propagate(s->sysclk);
579 }
580}
581
582static void ssys_write(void *opaque, hwaddr offset,
583 uint64_t value, unsigned size)
584{
585 ssys_state *s = (ssys_state *)opaque;
586
587 switch (offset) {
588 case 0x030:
589 s->pborctl = value & 0xffff;
590 break;
591 case 0x034:
592 s->ldopctl = value & 0x1f;
593 break;
594 case 0x040:
595 case 0x044:
596 case 0x048:
597 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n");
598 break;
599 case 0x054:
600 s->int_mask = value & 0x7f;
601 break;
602 case 0x058:
603 s->int_status &= ~value;
604 break;
605 case 0x05c:
606 s->resc = value & 0x3f;
607 break;
608 case 0x060:
609 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
610
611 s->int_status |= (1 << 6);
612 }
613 s->rcc = value;
614 ssys_calculate_system_clock(s, true);
615 break;
616 case 0x070:
617 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
618 break;
619 }
620
621 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
622
623 s->int_status |= (1 << 6);
624 }
625 s->rcc2 = value;
626 ssys_calculate_system_clock(s, true);
627 break;
628 case 0x100:
629 s->rcgc[0] = value;
630 break;
631 case 0x104:
632 s->rcgc[1] = value;
633 break;
634 case 0x108:
635 s->rcgc[2] = value;
636 break;
637 case 0x110:
638 s->scgc[0] = value;
639 break;
640 case 0x114:
641 s->scgc[1] = value;
642 break;
643 case 0x118:
644 s->scgc[2] = value;
645 break;
646 case 0x120:
647 s->dcgc[0] = value;
648 break;
649 case 0x124:
650 s->dcgc[1] = value;
651 break;
652 case 0x128:
653 s->dcgc[2] = value;
654 break;
655 case 0x150:
656 s->clkvclr = value;
657 break;
658 case 0x160:
659 s->ldoarst = value;
660 break;
661 default:
662 qemu_log_mask(LOG_GUEST_ERROR,
663 "SSYS: write at bad offset 0x%x\n", (int)offset);
664 }
665 ssys_update(s);
666}
667
668static const MemoryRegionOps ssys_ops = {
669 .read = ssys_read,
670 .write = ssys_write,
671 .endianness = DEVICE_NATIVE_ENDIAN,
672};
673
674static void stellaris_sys_reset_enter(Object *obj, ResetType type)
675{
676 ssys_state *s = STELLARIS_SYS(obj);
677
678 s->pborctl = 0x7ffd;
679 s->rcc = 0x078e3ac0;
680
681 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
682 s->rcc2 = 0;
683 } else {
684 s->rcc2 = 0x07802810;
685 }
686 s->rcgc[0] = 1;
687 s->scgc[0] = 1;
688 s->dcgc[0] = 1;
689}
690
691static void stellaris_sys_reset_hold(Object *obj)
692{
693 ssys_state *s = STELLARIS_SYS(obj);
694
695
696 ssys_calculate_system_clock(s, true);
697}
698
699static void stellaris_sys_reset_exit(Object *obj)
700{
701}
702
703static int stellaris_sys_post_load(void *opaque, int version_id)
704{
705 ssys_state *s = opaque;
706
707 ssys_calculate_system_clock(s, false);
708
709 return 0;
710}
711
712static const VMStateDescription vmstate_stellaris_sys = {
713 .name = "stellaris_sys",
714 .version_id = 2,
715 .minimum_version_id = 1,
716 .post_load = stellaris_sys_post_load,
717 .fields = (VMStateField[]) {
718 VMSTATE_UINT32(pborctl, ssys_state),
719 VMSTATE_UINT32(ldopctl, ssys_state),
720 VMSTATE_UINT32(int_mask, ssys_state),
721 VMSTATE_UINT32(int_status, ssys_state),
722 VMSTATE_UINT32(resc, ssys_state),
723 VMSTATE_UINT32(rcc, ssys_state),
724 VMSTATE_UINT32_V(rcc2, ssys_state, 2),
725 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
726 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
727 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
728 VMSTATE_UINT32(clkvclr, ssys_state),
729 VMSTATE_UINT32(ldoarst, ssys_state),
730
731 VMSTATE_END_OF_LIST()
732 }
733};
734
735static Property stellaris_sys_properties[] = {
736 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0),
737 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0),
738 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0),
739 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0),
740 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0),
741 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0),
742 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0),
743 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0),
744 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0),
745 DEFINE_PROP_END_OF_LIST()
746};
747
748static void stellaris_sys_instance_init(Object *obj)
749{
750 ssys_state *s = STELLARIS_SYS(obj);
751 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
752
753 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
754 sysbus_init_mmio(sbd, &s->iomem);
755 sysbus_init_irq(sbd, &s->irq);
756 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
757}
758
759static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq,
760 stellaris_board_info *board,
761 uint8_t *macaddr)
762{
763 DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS);
764 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
765
766
767 qdev_prop_set_uint32(dev, "user0",
768 macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16));
769 qdev_prop_set_uint32(dev, "user1",
770 macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16));
771 qdev_prop_set_uint32(dev, "did0", board->did0);
772 qdev_prop_set_uint32(dev, "did1", board->did1);
773 qdev_prop_set_uint32(dev, "dc0", board->dc0);
774 qdev_prop_set_uint32(dev, "dc1", board->dc1);
775 qdev_prop_set_uint32(dev, "dc2", board->dc2);
776 qdev_prop_set_uint32(dev, "dc3", board->dc3);
777 qdev_prop_set_uint32(dev, "dc4", board->dc4);
778
779 sysbus_realize_and_unref(sbd, &error_fatal);
780 sysbus_mmio_map(sbd, 0, base);
781 sysbus_connect_irq(sbd, 0, irq);
782
783 return dev;
784}
785
786
787
788#define TYPE_STELLARIS_I2C "stellaris-i2c"
789OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
790
791struct stellaris_i2c_state {
792 SysBusDevice parent_obj;
793
794 I2CBus *bus;
795 qemu_irq irq;
796 MemoryRegion iomem;
797 uint32_t msa;
798 uint32_t mcs;
799 uint32_t mdr;
800 uint32_t mtpr;
801 uint32_t mimr;
802 uint32_t mris;
803 uint32_t mcr;
804};
805
806#define STELLARIS_I2C_MCS_BUSY 0x01
807#define STELLARIS_I2C_MCS_ERROR 0x02
808#define STELLARIS_I2C_MCS_ADRACK 0x04
809#define STELLARIS_I2C_MCS_DATACK 0x08
810#define STELLARIS_I2C_MCS_ARBLST 0x10
811#define STELLARIS_I2C_MCS_IDLE 0x20
812#define STELLARIS_I2C_MCS_BUSBSY 0x40
813
814static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
815 unsigned size)
816{
817 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
818
819 switch (offset) {
820 case 0x00:
821 return s->msa;
822 case 0x04:
823
824 return s->mcs | STELLARIS_I2C_MCS_IDLE;
825 case 0x08:
826 return s->mdr;
827 case 0x0c:
828 return s->mtpr;
829 case 0x10:
830 return s->mimr;
831 case 0x14:
832 return s->mris;
833 case 0x18:
834 return s->mris & s->mimr;
835 case 0x20:
836 return s->mcr;
837 default:
838 qemu_log_mask(LOG_GUEST_ERROR,
839 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
840 return 0;
841 }
842}
843
844static void stellaris_i2c_update(stellaris_i2c_state *s)
845{
846 int level;
847
848 level = (s->mris & s->mimr) != 0;
849 qemu_set_irq(s->irq, level);
850}
851
852static void stellaris_i2c_write(void *opaque, hwaddr offset,
853 uint64_t value, unsigned size)
854{
855 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
856
857 switch (offset) {
858 case 0x00:
859 s->msa = value & 0xff;
860 break;
861 case 0x04:
862 if ((s->mcr & 0x10) == 0) {
863
864 break;
865 }
866
867 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
868 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
869 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
870 } else {
871 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
872 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
873 }
874 }
875
876 if (!i2c_bus_busy(s->bus)
877 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
878 s->mcs |= STELLARIS_I2C_MCS_ERROR;
879 break;
880 }
881 s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
882 if (value & 1) {
883
884
885 if (s->msa & 1) {
886
887 s->mdr = i2c_recv(s->bus);
888 } else {
889
890 i2c_send(s->bus, s->mdr);
891 }
892
893 s->mris |= 1;
894 }
895 if (value & 4) {
896
897 i2c_end_transfer(s->bus);
898 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
899 }
900 break;
901 case 0x08:
902 s->mdr = value & 0xff;
903 break;
904 case 0x0c:
905 s->mtpr = value & 0xff;
906 break;
907 case 0x10:
908 s->mimr = 1;
909 break;
910 case 0x1c:
911 s->mris &= ~value;
912 break;
913 case 0x20:
914 if (value & 1) {
915 qemu_log_mask(LOG_UNIMP,
916 "stellaris_i2c: Loopback not implemented\n");
917 }
918 if (value & 0x20) {
919 qemu_log_mask(LOG_UNIMP,
920 "stellaris_i2c: Slave mode not implemented\n");
921 }
922 s->mcr = value & 0x31;
923 break;
924 default:
925 qemu_log_mask(LOG_GUEST_ERROR,
926 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
927 }
928 stellaris_i2c_update(s);
929}
930
931static void stellaris_i2c_reset(stellaris_i2c_state *s)
932{
933 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
934 i2c_end_transfer(s->bus);
935
936 s->msa = 0;
937 s->mcs = 0;
938 s->mdr = 0;
939 s->mtpr = 1;
940 s->mimr = 0;
941 s->mris = 0;
942 s->mcr = 0;
943 stellaris_i2c_update(s);
944}
945
946static const MemoryRegionOps stellaris_i2c_ops = {
947 .read = stellaris_i2c_read,
948 .write = stellaris_i2c_write,
949 .endianness = DEVICE_NATIVE_ENDIAN,
950};
951
952static const VMStateDescription vmstate_stellaris_i2c = {
953 .name = "stellaris_i2c",
954 .version_id = 1,
955 .minimum_version_id = 1,
956 .fields = (VMStateField[]) {
957 VMSTATE_UINT32(msa, stellaris_i2c_state),
958 VMSTATE_UINT32(mcs, stellaris_i2c_state),
959 VMSTATE_UINT32(mdr, stellaris_i2c_state),
960 VMSTATE_UINT32(mtpr, stellaris_i2c_state),
961 VMSTATE_UINT32(mimr, stellaris_i2c_state),
962 VMSTATE_UINT32(mris, stellaris_i2c_state),
963 VMSTATE_UINT32(mcr, stellaris_i2c_state),
964 VMSTATE_END_OF_LIST()
965 }
966};
967
968static void stellaris_i2c_init(Object *obj)
969{
970 DeviceState *dev = DEVICE(obj);
971 stellaris_i2c_state *s = STELLARIS_I2C(obj);
972 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
973 I2CBus *bus;
974
975 sysbus_init_irq(sbd, &s->irq);
976 bus = i2c_init_bus(dev, "i2c");
977 s->bus = bus;
978
979 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
980 "i2c", 0x1000);
981 sysbus_init_mmio(sbd, &s->iomem);
982
983 stellaris_i2c_reset(s);
984}
985
986
987
988
989#define STELLARIS_ADC_EM_CONTROLLER 0
990#define STELLARIS_ADC_EM_COMP 1
991#define STELLARIS_ADC_EM_EXTERNAL 4
992#define STELLARIS_ADC_EM_TIMER 5
993#define STELLARIS_ADC_EM_PWM0 6
994#define STELLARIS_ADC_EM_PWM1 7
995#define STELLARIS_ADC_EM_PWM2 8
996
997#define STELLARIS_ADC_FIFO_EMPTY 0x0100
998#define STELLARIS_ADC_FIFO_FULL 0x1000
999
1000#define TYPE_STELLARIS_ADC "stellaris-adc"
1001typedef struct StellarisADCState stellaris_adc_state;
1002DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC,
1003 TYPE_STELLARIS_ADC)
1004
1005struct StellarisADCState {
1006 SysBusDevice parent_obj;
1007
1008 MemoryRegion iomem;
1009 uint32_t actss;
1010 uint32_t ris;
1011 uint32_t im;
1012 uint32_t emux;
1013 uint32_t ostat;
1014 uint32_t ustat;
1015 uint32_t sspri;
1016 uint32_t sac;
1017 struct {
1018 uint32_t state;
1019 uint32_t data[16];
1020 } fifo[4];
1021 uint32_t ssmux[4];
1022 uint32_t ssctl[4];
1023 uint32_t noise;
1024 qemu_irq irq[4];
1025};
1026
1027static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
1028{
1029 int tail;
1030
1031 tail = s->fifo[n].state & 0xf;
1032 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
1033 s->ustat |= 1 << n;
1034 } else {
1035 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
1036 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
1037 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
1038 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
1039 }
1040 return s->fifo[n].data[tail];
1041}
1042
1043static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
1044 uint32_t value)
1045{
1046 int head;
1047
1048
1049
1050 head = (s->fifo[n].state >> 4) & 0xf;
1051 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
1052 s->ostat |= 1 << n;
1053 return;
1054 }
1055 s->fifo[n].data[head] = value;
1056 head = (head + 1) & 0xf;
1057 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
1058 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
1059 if ((s->fifo[n].state & 0xf) == head)
1060 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
1061}
1062
1063static void stellaris_adc_update(stellaris_adc_state *s)
1064{
1065 int level;
1066 int n;
1067
1068 for (n = 0; n < 4; n++) {
1069 level = (s->ris & s->im & (1 << n)) != 0;
1070 qemu_set_irq(s->irq[n], level);
1071 }
1072}
1073
1074static void stellaris_adc_trigger(void *opaque, int irq, int level)
1075{
1076 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1077 int n;
1078
1079 for (n = 0; n < 4; n++) {
1080 if ((s->actss & (1 << n)) == 0) {
1081 continue;
1082 }
1083
1084 if (((s->emux >> (n * 4)) & 0xff) != 5) {
1085 continue;
1086 }
1087
1088
1089
1090 s->noise = s->noise * 314159 + 1;
1091
1092 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
1093 s->ris |= (1 << n);
1094 stellaris_adc_update(s);
1095 }
1096}
1097
1098static void stellaris_adc_reset(stellaris_adc_state *s)
1099{
1100 int n;
1101
1102 for (n = 0; n < 4; n++) {
1103 s->ssmux[n] = 0;
1104 s->ssctl[n] = 0;
1105 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
1106 }
1107}
1108
1109static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
1110 unsigned size)
1111{
1112 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1113
1114
1115 if (offset >= 0x40 && offset < 0xc0) {
1116 int n;
1117 n = (offset - 0x40) >> 5;
1118 switch (offset & 0x1f) {
1119 case 0x00:
1120 return s->ssmux[n];
1121 case 0x04:
1122 return s->ssctl[n];
1123 case 0x08:
1124 return stellaris_adc_fifo_read(s, n);
1125 case 0x0c:
1126 return s->fifo[n].state;
1127 default:
1128 break;
1129 }
1130 }
1131 switch (offset) {
1132 case 0x00:
1133 return s->actss;
1134 case 0x04:
1135 return s->ris;
1136 case 0x08:
1137 return s->im;
1138 case 0x0c:
1139 return s->ris & s->im;
1140 case 0x10:
1141 return s->ostat;
1142 case 0x14:
1143 return s->emux;
1144 case 0x18:
1145 return s->ustat;
1146 case 0x20:
1147 return s->sspri;
1148 case 0x30:
1149 return s->sac;
1150 default:
1151 qemu_log_mask(LOG_GUEST_ERROR,
1152 "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
1153 return 0;
1154 }
1155}
1156
1157static void stellaris_adc_write(void *opaque, hwaddr offset,
1158 uint64_t value, unsigned size)
1159{
1160 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1161
1162
1163 if (offset >= 0x40 && offset < 0xc0) {
1164 int n;
1165 n = (offset - 0x40) >> 5;
1166 switch (offset & 0x1f) {
1167 case 0x00:
1168 s->ssmux[n] = value & 0x33333333;
1169 return;
1170 case 0x04:
1171 if (value != 6) {
1172 qemu_log_mask(LOG_UNIMP,
1173 "ADC: Unimplemented sequence %" PRIx64 "\n",
1174 value);
1175 }
1176 s->ssctl[n] = value;
1177 return;
1178 default:
1179 break;
1180 }
1181 }
1182 switch (offset) {
1183 case 0x00:
1184 s->actss = value & 0xf;
1185 break;
1186 case 0x08:
1187 s->im = value;
1188 break;
1189 case 0x0c:
1190 s->ris &= ~value;
1191 break;
1192 case 0x10:
1193 s->ostat &= ~value;
1194 break;
1195 case 0x14:
1196 s->emux = value;
1197 break;
1198 case 0x18:
1199 s->ustat &= ~value;
1200 break;
1201 case 0x20:
1202 s->sspri = value;
1203 break;
1204 case 0x28:
1205 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n");
1206 break;
1207 case 0x30:
1208 s->sac = value;
1209 break;
1210 default:
1211 qemu_log_mask(LOG_GUEST_ERROR,
1212 "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
1213 }
1214 stellaris_adc_update(s);
1215}
1216
1217static const MemoryRegionOps stellaris_adc_ops = {
1218 .read = stellaris_adc_read,
1219 .write = stellaris_adc_write,
1220 .endianness = DEVICE_NATIVE_ENDIAN,
1221};
1222
1223static const VMStateDescription vmstate_stellaris_adc = {
1224 .name = "stellaris_adc",
1225 .version_id = 1,
1226 .minimum_version_id = 1,
1227 .fields = (VMStateField[]) {
1228 VMSTATE_UINT32(actss, stellaris_adc_state),
1229 VMSTATE_UINT32(ris, stellaris_adc_state),
1230 VMSTATE_UINT32(im, stellaris_adc_state),
1231 VMSTATE_UINT32(emux, stellaris_adc_state),
1232 VMSTATE_UINT32(ostat, stellaris_adc_state),
1233 VMSTATE_UINT32(ustat, stellaris_adc_state),
1234 VMSTATE_UINT32(sspri, stellaris_adc_state),
1235 VMSTATE_UINT32(sac, stellaris_adc_state),
1236 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
1237 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
1238 VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
1239 VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
1240 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
1241 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
1242 VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
1243 VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
1244 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
1245 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
1246 VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
1247 VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
1248 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
1249 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
1250 VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
1251 VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
1252 VMSTATE_UINT32(noise, stellaris_adc_state),
1253 VMSTATE_END_OF_LIST()
1254 }
1255};
1256
1257static void stellaris_adc_init(Object *obj)
1258{
1259 DeviceState *dev = DEVICE(obj);
1260 stellaris_adc_state *s = STELLARIS_ADC(obj);
1261 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1262 int n;
1263
1264 for (n = 0; n < 4; n++) {
1265 sysbus_init_irq(sbd, &s->irq[n]);
1266 }
1267
1268 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
1269 "adc", 0x1000);
1270 sysbus_init_mmio(sbd, &s->iomem);
1271 stellaris_adc_reset(s);
1272 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
1273}
1274
1275
1276static stellaris_board_info stellaris_boards[] = {
1277 { "LM3S811EVB",
1278 0,
1279 0x0032000e,
1280 0x001f001f,
1281 0x001132bf,
1282 0x01071013,
1283 0x3f0f01ff,
1284 0x0000001f,
1285 BP_OLED_I2C
1286 },
1287 { "LM3S6965EVB",
1288 0x10010002,
1289 0x1073402e,
1290 0x00ff007f,
1291 0x001133ff,
1292 0x030f5317,
1293 0x0f0f87ff,
1294 0x5000007f,
1295 BP_OLED_SSI | BP_GAMEPAD
1296 }
1297};
1298
1299static void stellaris_init(MachineState *ms, stellaris_board_info *board)
1300{
1301 static const int uart_irq[] = {5, 6, 33, 34};
1302 static const int timer_irq[] = {19, 21, 23, 35};
1303 static const uint32_t gpio_addr[7] =
1304 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1305 0x40024000, 0x40025000, 0x40026000};
1306 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342 DeviceState *gpio_dev[7], *nvic;
1343 qemu_irq gpio_in[7][8];
1344 qemu_irq gpio_out[7][8];
1345 qemu_irq adc;
1346 int sram_size;
1347 int flash_size;
1348 I2CBus *i2c;
1349 DeviceState *dev;
1350 DeviceState *ssys_dev;
1351 int i;
1352 int j;
1353
1354 MemoryRegion *sram = g_new(MemoryRegion, 1);
1355 MemoryRegion *flash = g_new(MemoryRegion, 1);
1356 MemoryRegion *system_memory = get_system_memory();
1357
1358 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
1359 sram_size = ((board->dc0 >> 18) + 1) * 1024;
1360
1361
1362 memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
1363 &error_fatal);
1364 memory_region_add_subregion(system_memory, 0, flash);
1365
1366 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
1367 &error_fatal);
1368 memory_region_add_subregion(system_memory, 0x20000000, sram);
1369
1370 nvic = qdev_new(TYPE_ARMV7M);
1371 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
1372 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
1373 qdev_prop_set_bit(nvic, "enable-bitband", true);
1374 object_property_set_link(OBJECT(nvic), "memory",
1375 OBJECT(get_system_memory()), &error_abort);
1376
1377 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
1378
1379 if (board->dc1 & (1 << 16)) {
1380 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
1381 qdev_get_gpio_in(nvic, 14),
1382 qdev_get_gpio_in(nvic, 15),
1383 qdev_get_gpio_in(nvic, 16),
1384 qdev_get_gpio_in(nvic, 17),
1385 NULL);
1386 adc = qdev_get_gpio_in(dev, 0);
1387 } else {
1388 adc = NULL;
1389 }
1390 for (i = 0; i < 4; i++) {
1391 if (board->dc2 & (0x10000 << i)) {
1392 dev = sysbus_create_simple(TYPE_STELLARIS_GPTM,
1393 0x40030000 + i * 0x1000,
1394 qdev_get_gpio_in(nvic, timer_irq[i]));
1395
1396
1397 qdev_connect_gpio_out(dev, 0, adc);
1398 }
1399 }
1400
1401 ssys_dev = stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
1402 board, nd_table[0].macaddr.a);
1403
1404
1405 if (board->dc1 & (1 << 3)) {
1406 dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
1407
1408 qdev_connect_clock_in(dev, "WDOGCLK",
1409 qdev_get_clock_out(ssys_dev, "SYSCLK"));
1410
1411 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1412 sysbus_mmio_map(SYS_BUS_DEVICE(dev),
1413 0,
1414 0x40000000u);
1415 sysbus_connect_irq(SYS_BUS_DEVICE(dev),
1416 0,
1417 qdev_get_gpio_in(nvic, 18));
1418 }
1419
1420
1421 for (i = 0; i < 7; i++) {
1422 if (board->dc4 & (1 << i)) {
1423 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1424 qdev_get_gpio_in(nvic,
1425 gpio_irq[i]));
1426 for (j = 0; j < 8; j++) {
1427 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1428 gpio_out[i][j] = NULL;
1429 }
1430 }
1431 }
1432
1433 if (board->dc2 & (1 << 12)) {
1434 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
1435 qdev_get_gpio_in(nvic, 8));
1436 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
1437 if (board->peripherals & BP_OLED_I2C) {
1438 i2c_slave_create_simple(i2c, "ssd0303", 0x3d);
1439 }
1440 }
1441
1442 for (i = 0; i < 4; i++) {
1443 if (board->dc2 & (1 << i)) {
1444 pl011_luminary_create(0x4000c000 + i * 0x1000,
1445 qdev_get_gpio_in(nvic, uart_irq[i]),
1446 serial_hd(i));
1447 }
1448 }
1449 if (board->dc2 & (1 << 4)) {
1450 dev = sysbus_create_simple("pl022", 0x40008000,
1451 qdev_get_gpio_in(nvic, 7));
1452 if (board->peripherals & BP_OLED_SSI) {
1453 void *bus;
1454 DeviceState *sddev;
1455 DeviceState *ssddev;
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465 bus = qdev_get_child_bus(dev, "ssi");
1466
1467 sddev = ssi_create_peripheral(bus, "ssi-sd");
1468 ssddev = ssi_create_peripheral(bus, "ssd0323");
1469 gpio_out[GPIO_D][0] = qemu_irq_split(
1470 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
1471 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
1472 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
1473
1474
1475 qemu_irq_raise(gpio_out[GPIO_D][0]);
1476 }
1477 }
1478 if (board->dc4 & (1 << 28)) {
1479 DeviceState *enet;
1480
1481 qemu_check_nic_model(&nd_table[0], "stellaris");
1482
1483 enet = qdev_new("stellaris_enet");
1484 qdev_set_nic_properties(enet, &nd_table[0]);
1485 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal);
1486 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
1487 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
1488 }
1489 if (board->peripherals & BP_GAMEPAD) {
1490 qemu_irq gpad_irq[5];
1491 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1492
1493 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]);
1494 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]);
1495 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]);
1496 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]);
1497 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]);
1498
1499 stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1500 }
1501 for (i = 0; i < 7; i++) {
1502 if (board->dc4 & (1 << i)) {
1503 for (j = 0; j < 8; j++) {
1504 if (gpio_out[i][j]) {
1505 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1506 }
1507 }
1508 }
1509 }
1510
1511
1512
1513
1514 create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1515 create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1516 create_unimplemented_device("PWM", 0x40028000, 0x1000);
1517 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1518 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1519 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1520 create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1521 create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1522
1523 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size);
1524}
1525
1526
1527static void lm3s811evb_init(MachineState *machine)
1528{
1529 stellaris_init(machine, &stellaris_boards[0]);
1530}
1531
1532static void lm3s6965evb_init(MachineState *machine)
1533{
1534 stellaris_init(machine, &stellaris_boards[1]);
1535}
1536
1537static void lm3s811evb_class_init(ObjectClass *oc, void *data)
1538{
1539 MachineClass *mc = MACHINE_CLASS(oc);
1540
1541 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)";
1542 mc->init = lm3s811evb_init;
1543 mc->ignore_memory_transaction_failures = true;
1544 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1545}
1546
1547static const TypeInfo lm3s811evb_type = {
1548 .name = MACHINE_TYPE_NAME("lm3s811evb"),
1549 .parent = TYPE_MACHINE,
1550 .class_init = lm3s811evb_class_init,
1551};
1552
1553static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
1554{
1555 MachineClass *mc = MACHINE_CLASS(oc);
1556
1557 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)";
1558 mc->init = lm3s6965evb_init;
1559 mc->ignore_memory_transaction_failures = true;
1560 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1561}
1562
1563static const TypeInfo lm3s6965evb_type = {
1564 .name = MACHINE_TYPE_NAME("lm3s6965evb"),
1565 .parent = TYPE_MACHINE,
1566 .class_init = lm3s6965evb_class_init,
1567};
1568
1569static void stellaris_machine_init(void)
1570{
1571 type_register_static(&lm3s811evb_type);
1572 type_register_static(&lm3s6965evb_type);
1573}
1574
1575type_init(stellaris_machine_init)
1576
1577static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
1578{
1579 DeviceClass *dc = DEVICE_CLASS(klass);
1580
1581 dc->vmsd = &vmstate_stellaris_i2c;
1582}
1583
1584static const TypeInfo stellaris_i2c_info = {
1585 .name = TYPE_STELLARIS_I2C,
1586 .parent = TYPE_SYS_BUS_DEVICE,
1587 .instance_size = sizeof(stellaris_i2c_state),
1588 .instance_init = stellaris_i2c_init,
1589 .class_init = stellaris_i2c_class_init,
1590};
1591
1592static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
1593{
1594 DeviceClass *dc = DEVICE_CLASS(klass);
1595
1596 dc->vmsd = &vmstate_stellaris_gptm;
1597 dc->realize = stellaris_gptm_realize;
1598}
1599
1600static const TypeInfo stellaris_gptm_info = {
1601 .name = TYPE_STELLARIS_GPTM,
1602 .parent = TYPE_SYS_BUS_DEVICE,
1603 .instance_size = sizeof(gptm_state),
1604 .instance_init = stellaris_gptm_init,
1605 .class_init = stellaris_gptm_class_init,
1606};
1607
1608static void stellaris_adc_class_init(ObjectClass *klass, void *data)
1609{
1610 DeviceClass *dc = DEVICE_CLASS(klass);
1611
1612 dc->vmsd = &vmstate_stellaris_adc;
1613}
1614
1615static const TypeInfo stellaris_adc_info = {
1616 .name = TYPE_STELLARIS_ADC,
1617 .parent = TYPE_SYS_BUS_DEVICE,
1618 .instance_size = sizeof(stellaris_adc_state),
1619 .instance_init = stellaris_adc_init,
1620 .class_init = stellaris_adc_class_init,
1621};
1622
1623static void stellaris_sys_class_init(ObjectClass *klass, void *data)
1624{
1625 DeviceClass *dc = DEVICE_CLASS(klass);
1626 ResettableClass *rc = RESETTABLE_CLASS(klass);
1627
1628 dc->vmsd = &vmstate_stellaris_sys;
1629 rc->phases.enter = stellaris_sys_reset_enter;
1630 rc->phases.hold = stellaris_sys_reset_hold;
1631 rc->phases.exit = stellaris_sys_reset_exit;
1632 device_class_set_props(dc, stellaris_sys_properties);
1633}
1634
1635static const TypeInfo stellaris_sys_info = {
1636 .name = TYPE_STELLARIS_SYS,
1637 .parent = TYPE_SYS_BUS_DEVICE,
1638 .instance_size = sizeof(ssys_state),
1639 .instance_init = stellaris_sys_instance_init,
1640 .class_init = stellaris_sys_class_init,
1641};
1642
1643static void stellaris_register_types(void)
1644{
1645 type_register_static(&stellaris_i2c_info);
1646 type_register_static(&stellaris_gptm_info);
1647 type_register_static(&stellaris_adc_info);
1648 type_register_static(&stellaris_sys_info);
1649}
1650
1651type_init(stellaris_register_types)
1652