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24#include "qemu/osdep.h"
25#include "qapi/error.h"
26#include "qemu-common.h"
27#include "qemu/datadir.h"
28#include "cpu.h"
29#include "hw/sysbus.h"
30#include "hw/arm/boot.h"
31#include "hw/arm/primecell.h"
32#include "hw/net/lan9118.h"
33#include "hw/i2c/i2c.h"
34#include "net/net.h"
35#include "sysemu/sysemu.h"
36#include "hw/boards.h"
37#include "hw/loader.h"
38#include "exec/address-spaces.h"
39#include "hw/block/flash.h"
40#include "sysemu/device_tree.h"
41#include "qemu/error-report.h"
42#include <libfdt.h>
43#include "hw/char/pl011.h"
44#include "hw/cpu/a9mpcore.h"
45#include "hw/cpu/a15mpcore.h"
46#include "hw/i2c/arm_sbcon_i2c.h"
47#include "hw/sd/sd.h"
48#include "qom/object.h"
49
50#define VEXPRESS_BOARD_ID 0x8e0
51#define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
52#define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
53
54
55
56
57#define NUM_VIRTIO_TRANSPORTS 4
58
59
60
61
62
63
64
65
66
67enum {
68 VE_SYSREGS,
69 VE_SP810,
70 VE_SERIALPCI,
71 VE_PL041,
72 VE_MMCI,
73 VE_KMI0,
74 VE_KMI1,
75 VE_UART0,
76 VE_UART1,
77 VE_UART2,
78 VE_UART3,
79 VE_WDT,
80 VE_TIMER01,
81 VE_TIMER23,
82 VE_SERIALDVI,
83 VE_RTC,
84 VE_COMPACTFLASH,
85 VE_CLCD,
86 VE_NORFLASH0,
87 VE_NORFLASH1,
88 VE_NORFLASHALIAS,
89 VE_SRAM,
90 VE_VIDEORAM,
91 VE_ETHERNET,
92 VE_USB,
93 VE_DAPROM,
94 VE_VIRTIO,
95};
96
97static hwaddr motherboard_legacy_map[] = {
98 [VE_NORFLASHALIAS] = 0,
99
100 [VE_SYSREGS] = 0x10000000,
101 [VE_SP810] = 0x10001000,
102 [VE_SERIALPCI] = 0x10002000,
103 [VE_PL041] = 0x10004000,
104 [VE_MMCI] = 0x10005000,
105 [VE_KMI0] = 0x10006000,
106 [VE_KMI1] = 0x10007000,
107 [VE_UART0] = 0x10009000,
108 [VE_UART1] = 0x1000a000,
109 [VE_UART2] = 0x1000b000,
110 [VE_UART3] = 0x1000c000,
111 [VE_WDT] = 0x1000f000,
112 [VE_TIMER01] = 0x10011000,
113 [VE_TIMER23] = 0x10012000,
114 [VE_VIRTIO] = 0x10013000,
115 [VE_SERIALDVI] = 0x10016000,
116 [VE_RTC] = 0x10017000,
117 [VE_COMPACTFLASH] = 0x1001a000,
118 [VE_CLCD] = 0x1001f000,
119
120 [VE_NORFLASH0] = 0x40000000,
121
122 [VE_NORFLASH1] = 0x44000000,
123
124 [VE_SRAM] = 0x48000000,
125
126 [VE_VIDEORAM] = 0x4c000000,
127 [VE_ETHERNET] = 0x4e000000,
128 [VE_USB] = 0x4f000000,
129};
130
131static hwaddr motherboard_aseries_map[] = {
132 [VE_NORFLASHALIAS] = 0,
133
134 [VE_NORFLASH0] = 0x08000000,
135
136 [VE_NORFLASH1] = 0x0c000000,
137
138
139 [VE_SRAM] = 0x14000000,
140
141 [VE_VIDEORAM] = 0x18000000,
142 [VE_ETHERNET] = 0x1a000000,
143 [VE_USB] = 0x1b000000,
144
145 [VE_DAPROM] = 0x1c000000,
146 [VE_SYSREGS] = 0x1c010000,
147 [VE_SP810] = 0x1c020000,
148 [VE_SERIALPCI] = 0x1c030000,
149 [VE_PL041] = 0x1c040000,
150 [VE_MMCI] = 0x1c050000,
151 [VE_KMI0] = 0x1c060000,
152 [VE_KMI1] = 0x1c070000,
153 [VE_UART0] = 0x1c090000,
154 [VE_UART1] = 0x1c0a0000,
155 [VE_UART2] = 0x1c0b0000,
156 [VE_UART3] = 0x1c0c0000,
157 [VE_WDT] = 0x1c0f0000,
158 [VE_TIMER01] = 0x1c110000,
159 [VE_TIMER23] = 0x1c120000,
160 [VE_VIRTIO] = 0x1c130000,
161 [VE_SERIALDVI] = 0x1c160000,
162 [VE_RTC] = 0x1c170000,
163 [VE_COMPACTFLASH] = 0x1c1a0000,
164 [VE_CLCD] = 0x1c1f0000,
165};
166
167
168
169typedef struct VEDBoardInfo VEDBoardInfo;
170
171struct VexpressMachineClass {
172 MachineClass parent;
173 VEDBoardInfo *daughterboard;
174};
175
176struct VexpressMachineState {
177 MachineState parent;
178 bool secure;
179 bool virt;
180};
181
182#define TYPE_VEXPRESS_MACHINE "vexpress"
183#define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9")
184#define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15")
185OBJECT_DECLARE_TYPE(VexpressMachineState, VexpressMachineClass, VEXPRESS_MACHINE)
186
187typedef void DBoardInitFn(const VexpressMachineState *machine,
188 ram_addr_t ram_size,
189 const char *cpu_type,
190 qemu_irq *pic);
191
192struct VEDBoardInfo {
193 struct arm_boot_info bootinfo;
194 const hwaddr *motherboard_map;
195 hwaddr loader_start;
196 const hwaddr gic_cpu_if_addr;
197 uint32_t proc_id;
198 uint32_t num_voltage_sensors;
199 const uint32_t *voltages;
200 uint32_t num_clocks;
201 const uint32_t *clocks;
202 DBoardInitFn *init;
203};
204
205static void init_cpus(MachineState *ms, const char *cpu_type,
206 const char *privdev, hwaddr periphbase,
207 qemu_irq *pic, bool secure, bool virt)
208{
209 DeviceState *dev;
210 SysBusDevice *busdev;
211 int n;
212 unsigned int smp_cpus = ms->smp.cpus;
213
214
215 for (n = 0; n < smp_cpus; n++) {
216 Object *cpuobj = object_new(cpu_type);
217
218 if (!secure) {
219 object_property_set_bool(cpuobj, "has_el3", false, NULL);
220 }
221 if (!virt) {
222 if (object_property_find(cpuobj, "has_el2")) {
223 object_property_set_bool(cpuobj, "has_el2", false, NULL);
224 }
225 }
226
227 if (object_property_find(cpuobj, "reset-cbar")) {
228 object_property_set_int(cpuobj, "reset-cbar", periphbase,
229 &error_abort);
230 }
231 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
232 }
233
234
235
236
237
238 dev = qdev_new(privdev);
239 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
240 busdev = SYS_BUS_DEVICE(dev);
241 sysbus_realize_and_unref(busdev, &error_fatal);
242 sysbus_mmio_map(busdev, 0, periphbase);
243
244
245
246
247
248
249
250 for (n = 0; n < 64; n++) {
251 pic[n] = qdev_get_gpio_in(dev, n);
252 }
253
254
255 for (n = 0; n < smp_cpus; n++) {
256 DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
257
258 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
259 sysbus_connect_irq(busdev, n + smp_cpus,
260 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
261 sysbus_connect_irq(busdev, n + 2 * smp_cpus,
262 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
263 sysbus_connect_irq(busdev, n + 3 * smp_cpus,
264 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
265 }
266}
267
268static void a9_daughterboard_init(const VexpressMachineState *vms,
269 ram_addr_t ram_size,
270 const char *cpu_type,
271 qemu_irq *pic)
272{
273 MachineState *machine = MACHINE(vms);
274 MemoryRegion *sysmem = get_system_memory();
275 MemoryRegion *lowram = g_new(MemoryRegion, 1);
276 ram_addr_t low_ram_size;
277
278 if (ram_size > 0x40000000) {
279
280 error_report("vexpress-a9: cannot model more than 1GB RAM");
281 exit(1);
282 }
283
284 low_ram_size = ram_size;
285 if (low_ram_size > 0x4000000) {
286 low_ram_size = 0x4000000;
287 }
288
289
290
291
292 memory_region_init_alias(lowram, NULL, "vexpress.lowmem", machine->ram,
293 0, low_ram_size);
294 memory_region_add_subregion(sysmem, 0x0, lowram);
295 memory_region_add_subregion(sysmem, 0x60000000, machine->ram);
296
297
298 init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic,
299 vms->secure, vms->virt);
300
301
302
303
304 sysbus_create_simple("pl111", 0x10020000, pic[44]);
305
306
307
308
309
310
311 sysbus_create_simple("sp804", 0x100e4000, pic[48]);
312
313
314
315
316
317
318
319 sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
320}
321
322
323
324
325static const uint32_t a9_voltages[] = {
326 1000000,
327 1000000,
328 1000000,
329 1800000,
330 900000,
331 3300000,
332};
333
334
335static const uint32_t a9_clocks[] = {
336 45000000,
337 23750000,
338 66670000,
339};
340
341static VEDBoardInfo a9_daughterboard = {
342 .motherboard_map = motherboard_legacy_map,
343 .loader_start = 0x60000000,
344 .gic_cpu_if_addr = 0x1e000100,
345 .proc_id = 0x0c000191,
346 .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
347 .voltages = a9_voltages,
348 .num_clocks = ARRAY_SIZE(a9_clocks),
349 .clocks = a9_clocks,
350 .init = a9_daughterboard_init,
351};
352
353static void a15_daughterboard_init(const VexpressMachineState *vms,
354 ram_addr_t ram_size,
355 const char *cpu_type,
356 qemu_irq *pic)
357{
358 MachineState *machine = MACHINE(vms);
359 MemoryRegion *sysmem = get_system_memory();
360 MemoryRegion *sram = g_new(MemoryRegion, 1);
361
362 {
363
364
365
366
367 uint64_t rsz = ram_size;
368 if (rsz > (30ULL * 1024 * 1024 * 1024)) {
369 error_report("vexpress-a15: cannot model more than 30GB RAM");
370 exit(1);
371 }
372 }
373
374
375 memory_region_add_subregion(sysmem, 0x80000000, machine->ram);
376
377
378 init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV,
379 0x2c000000, pic, vms->secure, vms->virt);
380
381
382
383
384
385
386
387
388
389
390
391 memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000,
392 &error_fatal);
393 memory_region_add_subregion(sysmem, 0x2e000000, sram);
394
395
396
397}
398
399static const uint32_t a15_voltages[] = {
400 900000,
401};
402
403static const uint32_t a15_clocks[] = {
404 60000000,
405 0,
406 0,
407 0,
408 40000000,
409 23750000,
410 50000000,
411 60000000,
412 40000000,
413};
414
415static VEDBoardInfo a15_daughterboard = {
416 .motherboard_map = motherboard_aseries_map,
417 .loader_start = 0x80000000,
418 .gic_cpu_if_addr = 0x2c002000,
419 .proc_id = 0x14000237,
420 .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
421 .voltages = a15_voltages,
422 .num_clocks = ARRAY_SIZE(a15_clocks),
423 .clocks = a15_clocks,
424 .init = a15_daughterboard_init,
425};
426
427static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
428 hwaddr addr, hwaddr size, uint32_t intc,
429 int irq)
430{
431
432
433
434
435
436
437
438
439
440
441
442 int rc;
443 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
444
445 rc = qemu_fdt_add_subnode(fdt, nodename);
446 rc |= qemu_fdt_setprop_string(fdt, nodename,
447 "compatible", "virtio,mmio");
448 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
449 acells, addr, scells, size);
450 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
451 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
452 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
453 g_free(nodename);
454 if (rc) {
455 return -1;
456 }
457 return 0;
458}
459
460static uint32_t find_int_controller(void *fdt)
461{
462
463
464
465
466
467
468 const char *compat = "arm,cortex-a9-gic";
469 int offset;
470
471 offset = fdt_node_offset_by_compatible(fdt, -1, compat);
472 if (offset >= 0) {
473 return fdt_get_phandle(fdt, offset);
474 }
475 return 0;
476}
477
478static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
479{
480 uint32_t acells, scells, intc;
481 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
482
483 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
484 NULL, &error_fatal);
485 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
486 NULL, &error_fatal);
487 intc = find_int_controller(fdt);
488 if (!intc) {
489
490
491
492 warn_report("couldn't find interrupt controller in "
493 "dtb; will not include virtio-mmio devices in the dtb");
494 } else {
495 int i;
496 const hwaddr *map = daughterboard->motherboard_map;
497
498
499
500
501 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
502 add_virtio_mmio_node(fdt, acells, scells,
503 map[VE_VIRTIO] + 0x200 * i,
504 0x200, intc, 40 + i);
505 }
506 }
507}
508
509
510
511
512
513static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name,
514 DriveInfo *di)
515{
516 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
517
518 if (di) {
519 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di));
520 }
521
522 qdev_prop_set_uint32(dev, "num-blocks",
523 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE);
524 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
525 qdev_prop_set_uint8(dev, "width", 4);
526 qdev_prop_set_uint8(dev, "device-width", 2);
527 qdev_prop_set_bit(dev, "big-endian", false);
528 qdev_prop_set_uint16(dev, "id0", 0x89);
529 qdev_prop_set_uint16(dev, "id1", 0x18);
530 qdev_prop_set_uint16(dev, "id2", 0x00);
531 qdev_prop_set_uint16(dev, "id3", 0x00);
532 qdev_prop_set_string(dev, "name", name);
533 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
534
535 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
536 return PFLASH_CFI01(dev);
537}
538
539static void vexpress_common_init(MachineState *machine)
540{
541 VexpressMachineState *vms = VEXPRESS_MACHINE(machine);
542 VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
543 VEDBoardInfo *daughterboard = vmc->daughterboard;
544 DeviceState *dev, *sysctl, *pl041;
545 qemu_irq pic[64];
546 uint32_t sys_id;
547 DriveInfo *dinfo;
548 PFlashCFI01 *pflash0;
549 I2CBus *i2c;
550 ram_addr_t vram_size, sram_size;
551 MemoryRegion *sysmem = get_system_memory();
552 MemoryRegion *vram = g_new(MemoryRegion, 1);
553 MemoryRegion *sram = g_new(MemoryRegion, 1);
554 MemoryRegion *flashalias = g_new(MemoryRegion, 1);
555 MemoryRegion *flash0mem;
556 const hwaddr *map = daughterboard->motherboard_map;
557 int i;
558
559 daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);
560
561
562
563
564 if (machine->firmware) {
565 char *fn;
566 int image_size;
567
568 if (drive_get(IF_PFLASH, 0, 0)) {
569 error_report("The contents of the first flash device may be "
570 "specified with -bios or with -drive if=pflash... "
571 "but you cannot use both options at once");
572 exit(1);
573 }
574 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
575 if (!fn) {
576 error_report("Could not find ROM image '%s'", machine->firmware);
577 exit(1);
578 }
579 image_size = load_image_targphys(fn, map[VE_NORFLASH0],
580 VEXPRESS_FLASH_SIZE);
581 g_free(fn);
582 if (image_size < 0) {
583 error_report("Could not load ROM image '%s'", machine->firmware);
584 exit(1);
585 }
586 }
587
588
589
590
591
592 sys_id = 0x1190f500;
593
594 sysctl = qdev_new("realview_sysctl");
595 qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
596 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
597 qdev_prop_set_uint32(sysctl, "len-db-voltage",
598 daughterboard->num_voltage_sensors);
599 for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
600 char *propname = g_strdup_printf("db-voltage[%d]", i);
601 qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
602 g_free(propname);
603 }
604 qdev_prop_set_uint32(sysctl, "len-db-clock",
605 daughterboard->num_clocks);
606 for (i = 0; i < daughterboard->num_clocks; i++) {
607 char *propname = g_strdup_printf("db-clock[%d]", i);
608 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
609 g_free(propname);
610 }
611 sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
612 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
613
614
615
616
617 pl041 = qdev_new("pl041");
618 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
619 sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
620 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
621 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
622
623 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
624
625 qdev_connect_gpio_out_named(dev, "card-read-only", 0,
626 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
627 qdev_connect_gpio_out_named(dev, "card-inserted", 0,
628 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
629 dinfo = drive_get_next(IF_SD);
630 if (dinfo) {
631 DeviceState *card;
632
633 card = qdev_new(TYPE_SD_CARD);
634 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
635 &error_fatal);
636 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"),
637 &error_fatal);
638 }
639
640 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
641 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
642
643 pl011_create(map[VE_UART0], pic[5], serial_hd(0));
644 pl011_create(map[VE_UART1], pic[6], serial_hd(1));
645 pl011_create(map[VE_UART2], pic[7], serial_hd(2));
646 pl011_create(map[VE_UART3], pic[8], serial_hd(3));
647
648 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
649 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
650
651 dev = sysbus_create_simple(TYPE_VERSATILE_I2C, map[VE_SERIALDVI], NULL);
652 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
653 i2c_slave_create_simple(i2c, "sii9022", 0x39);
654
655 sysbus_create_simple("pl031", map[VE_RTC], pic[4]);
656
657
658
659 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
660
661 dinfo = drive_get_next(IF_PFLASH);
662 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
663 dinfo);
664 if (!pflash0) {
665 error_report("vexpress: error registering flash 0");
666 exit(1);
667 }
668
669 if (map[VE_NORFLASHALIAS] != -1) {
670
671 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
672 memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
673 flash0mem, 0, VEXPRESS_FLASH_SIZE);
674 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
675 }
676
677 dinfo = drive_get_next(IF_PFLASH);
678 if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
679 dinfo)) {
680 error_report("vexpress: error registering flash 1");
681 exit(1);
682 }
683
684 sram_size = 0x2000000;
685 memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
686 &error_fatal);
687 memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
688
689 vram_size = 0x800000;
690 memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size,
691 &error_fatal);
692 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
693
694
695 if (nd_table[0].used) {
696 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
697 }
698
699
700
701
702
703
704
705
706
707 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
708 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
709 pic[40 + i]);
710 }
711
712 daughterboard->bootinfo.ram_size = machine->ram_size;
713 daughterboard->bootinfo.nb_cpus = machine->smp.cpus;
714 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
715 daughterboard->bootinfo.loader_start = daughterboard->loader_start;
716 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
717 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
718 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
719 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
720
721 daughterboard->bootinfo.secure_boot = vms->secure;
722 arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo);
723}
724
725static bool vexpress_get_secure(Object *obj, Error **errp)
726{
727 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
728
729 return vms->secure;
730}
731
732static void vexpress_set_secure(Object *obj, bool value, Error **errp)
733{
734 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
735
736 vms->secure = value;
737}
738
739static bool vexpress_get_virt(Object *obj, Error **errp)
740{
741 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
742
743 return vms->virt;
744}
745
746static void vexpress_set_virt(Object *obj, bool value, Error **errp)
747{
748 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
749
750 vms->virt = value;
751}
752
753static void vexpress_instance_init(Object *obj)
754{
755 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
756
757
758 vms->secure = true;
759}
760
761static void vexpress_a15_instance_init(Object *obj)
762{
763 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
764
765
766
767
768
769 vms->virt = true;
770}
771
772static void vexpress_a9_instance_init(Object *obj)
773{
774 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
775
776
777 vms->virt = false;
778}
779
780static void vexpress_class_init(ObjectClass *oc, void *data)
781{
782 MachineClass *mc = MACHINE_CLASS(oc);
783
784 mc->desc = "ARM Versatile Express";
785 mc->init = vexpress_common_init;
786 mc->max_cpus = 4;
787 mc->ignore_memory_transaction_failures = true;
788 mc->default_ram_id = "vexpress.highmem";
789
790 object_class_property_add_bool(oc, "secure", vexpress_get_secure,
791 vexpress_set_secure);
792 object_class_property_set_description(oc, "secure",
793 "Set on/off to enable/disable the ARM "
794 "Security Extensions (TrustZone)");
795}
796
797static void vexpress_a9_class_init(ObjectClass *oc, void *data)
798{
799 MachineClass *mc = MACHINE_CLASS(oc);
800 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
801
802 mc->desc = "ARM Versatile Express for Cortex-A9";
803 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
804
805 vmc->daughterboard = &a9_daughterboard;
806}
807
808static void vexpress_a15_class_init(ObjectClass *oc, void *data)
809{
810 MachineClass *mc = MACHINE_CLASS(oc);
811 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
812
813 mc->desc = "ARM Versatile Express for Cortex-A15";
814 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
815
816 vmc->daughterboard = &a15_daughterboard;
817
818 object_class_property_add_bool(oc, "virtualization", vexpress_get_virt,
819 vexpress_set_virt);
820 object_class_property_set_description(oc, "virtualization",
821 "Set on/off to enable/disable the ARM "
822 "Virtualization Extensions "
823 "(defaults to same as 'secure')");
824
825}
826
827static const TypeInfo vexpress_info = {
828 .name = TYPE_VEXPRESS_MACHINE,
829 .parent = TYPE_MACHINE,
830 .abstract = true,
831 .instance_size = sizeof(VexpressMachineState),
832 .instance_init = vexpress_instance_init,
833 .class_size = sizeof(VexpressMachineClass),
834 .class_init = vexpress_class_init,
835};
836
837static const TypeInfo vexpress_a9_info = {
838 .name = TYPE_VEXPRESS_A9_MACHINE,
839 .parent = TYPE_VEXPRESS_MACHINE,
840 .class_init = vexpress_a9_class_init,
841 .instance_init = vexpress_a9_instance_init,
842};
843
844static const TypeInfo vexpress_a15_info = {
845 .name = TYPE_VEXPRESS_A15_MACHINE,
846 .parent = TYPE_VEXPRESS_MACHINE,
847 .class_init = vexpress_a15_class_init,
848 .instance_init = vexpress_a15_instance_init,
849};
850
851static void vexpress_machine_init(void)
852{
853 type_register_static(&vexpress_info);
854 type_register_static(&vexpress_a9_info);
855 type_register_static(&vexpress_a15_info);
856}
857
858type_init(vexpress_machine_init);
859