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24#include "qemu/osdep.h"
25#include "hw/sysbus.h"
26#include "migration/vmstate.h"
27#include "chardev/char-fe.h"
28#include "chardev/char-serial.h"
29#include "qemu/timer.h"
30#include "qemu/log.h"
31#include "qemu/module.h"
32#include "hw/char/cadence_uart.h"
33#include "hw/irq.h"
34#include "hw/qdev-clock.h"
35#include "hw/qdev-properties-system.h"
36#include "trace.h"
37
38#ifdef CADENCE_UART_ERR_DEBUG
39#define DB_PRINT(...) do { \
40 fprintf(stderr, ": %s: ", __func__); \
41 fprintf(stderr, ## __VA_ARGS__); \
42 } while (0)
43#else
44 #define DB_PRINT(...)
45#endif
46
47#define UART_SR_INTR_RTRIG 0x00000001
48#define UART_SR_INTR_REMPTY 0x00000002
49#define UART_SR_INTR_RFUL 0x00000004
50#define UART_SR_INTR_TEMPTY 0x00000008
51#define UART_SR_INTR_TFUL 0x00000010
52
53#define UART_SR_TTRIG 0x00002000
54#define UART_INTR_TTRIG 0x00000400
55
56
57#define UART_SR_TO_CISR_MASK 0x0000001F
58
59#define UART_INTR_ROVR 0x00000020
60#define UART_INTR_FRAME 0x00000040
61#define UART_INTR_PARE 0x00000080
62#define UART_INTR_TIMEOUT 0x00000100
63#define UART_INTR_DMSI 0x00000200
64#define UART_INTR_TOVR 0x00001000
65
66#define UART_SR_RACTIVE 0x00000400
67#define UART_SR_TACTIVE 0x00000800
68#define UART_SR_FDELT 0x00001000
69
70#define UART_CR_RXRST 0x00000001
71#define UART_CR_TXRST 0x00000002
72#define UART_CR_RX_EN 0x00000004
73#define UART_CR_RX_DIS 0x00000008
74#define UART_CR_TX_EN 0x00000010
75#define UART_CR_TX_DIS 0x00000020
76#define UART_CR_RST_TO 0x00000040
77#define UART_CR_STARTBRK 0x00000080
78#define UART_CR_STOPBRK 0x00000100
79
80#define UART_MR_CLKS 0x00000001
81#define UART_MR_CHRL 0x00000006
82#define UART_MR_CHRL_SH 1
83#define UART_MR_PAR 0x00000038
84#define UART_MR_PAR_SH 3
85#define UART_MR_NBSTOP 0x000000C0
86#define UART_MR_NBSTOP_SH 6
87#define UART_MR_CHMODE 0x00000300
88#define UART_MR_CHMODE_SH 8
89#define UART_MR_UCLKEN 0x00000400
90#define UART_MR_IRMODE 0x00000800
91
92#define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH)
93#define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH)
94#define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH)
95#define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH)
96#define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH)
97#define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH)
98#define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH)
99#define ECHO_MODE (0x1 << UART_MR_CHMODE_SH)
100#define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
101#define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
102
103#define UART_DEFAULT_REF_CLK (50 * 1000 * 1000)
104
105#define R_CR (0x00/4)
106#define R_MR (0x04/4)
107#define R_IER (0x08/4)
108#define R_IDR (0x0C/4)
109#define R_IMR (0x10/4)
110#define R_CISR (0x14/4)
111#define R_BRGR (0x18/4)
112#define R_RTOR (0x1C/4)
113#define R_RTRIG (0x20/4)
114#define R_MCR (0x24/4)
115#define R_MSR (0x28/4)
116#define R_SR (0x2C/4)
117#define R_TX_RX (0x30/4)
118#define R_BDIV (0x34/4)
119#define R_FDEL (0x38/4)
120#define R_PMIN (0x3C/4)
121#define R_PWID (0x40/4)
122#define R_TTRIG (0x44/4)
123
124
125static void uart_update_status(CadenceUARTState *s)
126{
127 s->r[R_SR] = 0;
128
129 s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL
130 : 0;
131 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
132 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
133
134 s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL
135 : 0;
136 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
137 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;
138
139 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
140 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0;
141 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
142}
143
144static void fifo_trigger_update(void *opaque)
145{
146 CadenceUARTState *s = opaque;
147
148 if (s->r[R_RTOR]) {
149 s->r[R_CISR] |= UART_INTR_TIMEOUT;
150 uart_update_status(s);
151 }
152}
153
154static void uart_rx_reset(CadenceUARTState *s)
155{
156 s->rx_wpos = 0;
157 s->rx_count = 0;
158 qemu_chr_fe_accept_input(&s->chr);
159}
160
161static void uart_tx_reset(CadenceUARTState *s)
162{
163 s->tx_count = 0;
164}
165
166static void uart_send_breaks(CadenceUARTState *s)
167{
168 int break_enabled = 1;
169
170 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
171 &break_enabled);
172}
173
174static void uart_parameters_setup(CadenceUARTState *s)
175{
176 QEMUSerialSetParams ssp;
177 unsigned int baud_rate, packet_size, input_clk;
178 input_clk = clock_get_hz(s->refclk);
179
180 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? input_clk / 8 : input_clk;
181 baud_rate /= (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
182 trace_cadence_uart_baudrate(baud_rate);
183
184 ssp.speed = baud_rate;
185
186 packet_size = 1;
187
188 switch (s->r[R_MR] & UART_MR_PAR) {
189 case UART_PARITY_EVEN:
190 ssp.parity = 'E';
191 packet_size++;
192 break;
193 case UART_PARITY_ODD:
194 ssp.parity = 'O';
195 packet_size++;
196 break;
197 default:
198 ssp.parity = 'N';
199 break;
200 }
201
202 switch (s->r[R_MR] & UART_MR_CHRL) {
203 case UART_DATA_BITS_6:
204 ssp.data_bits = 6;
205 break;
206 case UART_DATA_BITS_7:
207 ssp.data_bits = 7;
208 break;
209 default:
210 ssp.data_bits = 8;
211 break;
212 }
213
214 switch (s->r[R_MR] & UART_MR_NBSTOP) {
215 case UART_STOP_BITS_1:
216 ssp.stop_bits = 1;
217 break;
218 default:
219 ssp.stop_bits = 2;
220 break;
221 }
222
223 packet_size += ssp.data_bits + ssp.stop_bits;
224 if (ssp.speed == 0) {
225
226
227
228
229 ssp.speed = 1;
230 }
231 s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
232 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
233}
234
235static int uart_can_receive(void *opaque)
236{
237 CadenceUARTState *s = opaque;
238 int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
239 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
240
241 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
242 ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);
243 }
244 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
245 ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count);
246 }
247 return ret;
248}
249
250static void uart_ctrl_update(CadenceUARTState *s)
251{
252 if (s->r[R_CR] & UART_CR_TXRST) {
253 uart_tx_reset(s);
254 }
255
256 if (s->r[R_CR] & UART_CR_RXRST) {
257 uart_rx_reset(s);
258 }
259
260 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
261
262 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
263 uart_send_breaks(s);
264 }
265}
266
267static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
268{
269 CadenceUARTState *s = opaque;
270 uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
271 int i;
272
273 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
274 return;
275 }
276
277 if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) {
278 s->r[R_CISR] |= UART_INTR_ROVR;
279 } else {
280 for (i = 0; i < size; i++) {
281 s->rx_fifo[s->rx_wpos] = buf[i];
282 s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE;
283 s->rx_count++;
284 }
285 timer_mod(s->fifo_trigger_handle, new_rx_time +
286 (s->char_tx_time * 4));
287 }
288 uart_update_status(s);
289}
290
291static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
292 void *opaque)
293{
294 CadenceUARTState *s = opaque;
295 int ret;
296
297
298 if (!qemu_chr_fe_backend_connected(&s->chr)) {
299 s->tx_count = 0;
300 return FALSE;
301 }
302
303 if (!s->tx_count) {
304 return FALSE;
305 }
306
307 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count);
308
309 if (ret >= 0) {
310 s->tx_count -= ret;
311 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count);
312 }
313
314 if (s->tx_count) {
315 guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
316 cadence_uart_xmit, s);
317 if (!r) {
318 s->tx_count = 0;
319 return FALSE;
320 }
321 }
322
323 uart_update_status(s);
324 return FALSE;
325}
326
327static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
328 int size)
329{
330 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
331 return;
332 }
333
334 if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) {
335 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count;
336
337
338
339
340
341 qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow");
342 s->r[R_CISR] |= UART_INTR_ROVR;
343 }
344
345 memcpy(s->tx_fifo + s->tx_count, buf, size);
346 s->tx_count += size;
347
348 cadence_uart_xmit(NULL, G_IO_OUT, s);
349}
350
351static void uart_receive(void *opaque, const uint8_t *buf, int size)
352{
353 CadenceUARTState *s = opaque;
354 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
355
356
357 if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
358 return;
359 }
360
361 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
362 uart_write_rx_fifo(opaque, buf, size);
363 }
364 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
365 uart_write_tx_fifo(s, buf, size);
366 }
367}
368
369static void uart_event(void *opaque, QEMUChrEvent event)
370{
371 CadenceUARTState *s = opaque;
372 uint8_t buf = '\0';
373
374
375 if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
376 return;
377 }
378
379 if (event == CHR_EVENT_BREAK) {
380 uart_write_rx_fifo(opaque, &buf, 1);
381 }
382
383 uart_update_status(s);
384}
385
386static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
387{
388 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
389 return;
390 }
391
392 if (s->rx_count) {
393 uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos -
394 s->rx_count) % CADENCE_UART_RX_FIFO_SIZE;
395 *c = s->rx_fifo[rx_rpos];
396 s->rx_count--;
397
398 qemu_chr_fe_accept_input(&s->chr);
399 } else {
400 *c = 0;
401 }
402
403 uart_update_status(s);
404}
405
406static void uart_write(void *opaque, hwaddr offset,
407 uint64_t value, unsigned size)
408{
409 CadenceUARTState *s = opaque;
410
411 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
412 offset >>= 2;
413 if (offset >= CADENCE_UART_R_MAX) {
414 return;
415 }
416 switch (offset) {
417 case R_IER:
418 s->r[R_IMR] |= value;
419 break;
420 case R_IDR:
421 s->r[R_IMR] &= ~value;
422 break;
423 case R_IMR:
424 break;
425 case R_CISR:
426 s->r[R_CISR] &= ~value;
427 break;
428 case R_TX_RX:
429 switch (s->r[R_MR] & UART_MR_CHMODE) {
430 case NORMAL_MODE:
431 uart_write_tx_fifo(s, (uint8_t *) &value, 1);
432 break;
433 case LOCAL_LOOPBACK:
434 uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
435 break;
436 }
437 break;
438 case R_BRGR:
439 if (value >= 0x01) {
440 s->r[offset] = value & 0xFFFF;
441 }
442 break;
443 case R_BDIV:
444 if (value >= 0x04) {
445 s->r[offset] = value & 0xFF;
446 }
447 break;
448 default:
449 s->r[offset] = value;
450 }
451
452 switch (offset) {
453 case R_CR:
454 uart_ctrl_update(s);
455 break;
456 case R_MR:
457 uart_parameters_setup(s);
458 break;
459 }
460 uart_update_status(s);
461}
462
463static uint64_t uart_read(void *opaque, hwaddr offset,
464 unsigned size)
465{
466 CadenceUARTState *s = opaque;
467 uint32_t c = 0;
468
469 offset >>= 2;
470 if (offset >= CADENCE_UART_R_MAX) {
471 c = 0;
472 } else if (offset == R_TX_RX) {
473 uart_read_rx_fifo(s, &c);
474 } else {
475 c = s->r[offset];
476 }
477
478 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
479 return c;
480}
481
482static const MemoryRegionOps uart_ops = {
483 .read = uart_read,
484 .write = uart_write,
485 .endianness = DEVICE_NATIVE_ENDIAN,
486};
487
488static void cadence_uart_reset_init(Object *obj, ResetType type)
489{
490 CadenceUARTState *s = CADENCE_UART(obj);
491
492 s->r[R_CR] = 0x00000128;
493 s->r[R_IMR] = 0;
494 s->r[R_CISR] = 0;
495 s->r[R_RTRIG] = 0x00000020;
496 s->r[R_BRGR] = 0x0000028B;
497 s->r[R_BDIV] = 0x0000000F;
498 s->r[R_TTRIG] = 0x00000020;
499}
500
501static void cadence_uart_reset_hold(Object *obj)
502{
503 CadenceUARTState *s = CADENCE_UART(obj);
504
505 uart_rx_reset(s);
506 uart_tx_reset(s);
507
508 uart_update_status(s);
509}
510
511static void cadence_uart_realize(DeviceState *dev, Error **errp)
512{
513 CadenceUARTState *s = CADENCE_UART(dev);
514
515 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
516 fifo_trigger_update, s);
517
518 qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
519 uart_event, NULL, s, NULL, true);
520}
521
522static void cadence_uart_refclk_update(void *opaque, ClockEvent event)
523{
524 CadenceUARTState *s = opaque;
525
526
527 uart_parameters_setup(s);
528}
529
530static void cadence_uart_init(Object *obj)
531{
532 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
533 CadenceUARTState *s = CADENCE_UART(obj);
534
535 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
536 sysbus_init_mmio(sbd, &s->iomem);
537 sysbus_init_irq(sbd, &s->irq);
538
539 s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk",
540 cadence_uart_refclk_update, s, ClockUpdate);
541
542 clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK);
543
544 s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
545}
546
547static int cadence_uart_pre_load(void *opaque)
548{
549 CadenceUARTState *s = opaque;
550
551
552 clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK);
553 return 0;
554}
555
556static int cadence_uart_post_load(void *opaque, int version_id)
557{
558 CadenceUARTState *s = opaque;
559
560
561 if (s->r[R_BRGR] < 1 || s->r[R_BRGR] & ~0xFFFF ||
562 s->r[R_BDIV] <= 3 || s->r[R_BDIV] & ~0xFF) {
563
564 return 1;
565 }
566
567 uart_parameters_setup(s);
568 uart_update_status(s);
569 return 0;
570}
571
572static const VMStateDescription vmstate_cadence_uart = {
573 .name = "cadence_uart",
574 .version_id = 3,
575 .minimum_version_id = 2,
576 .pre_load = cadence_uart_pre_load,
577 .post_load = cadence_uart_post_load,
578 .fields = (VMStateField[]) {
579 VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
580 VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState,
581 CADENCE_UART_RX_FIFO_SIZE),
582 VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState,
583 CADENCE_UART_TX_FIFO_SIZE),
584 VMSTATE_UINT32(rx_count, CadenceUARTState),
585 VMSTATE_UINT32(tx_count, CadenceUARTState),
586 VMSTATE_UINT32(rx_wpos, CadenceUARTState),
587 VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
588 VMSTATE_CLOCK_V(refclk, CadenceUARTState, 3),
589 VMSTATE_END_OF_LIST()
590 },
591};
592
593static Property cadence_uart_properties[] = {
594 DEFINE_PROP_CHR("chardev", CadenceUARTState, chr),
595 DEFINE_PROP_END_OF_LIST(),
596};
597
598static void cadence_uart_class_init(ObjectClass *klass, void *data)
599{
600 DeviceClass *dc = DEVICE_CLASS(klass);
601 ResettableClass *rc = RESETTABLE_CLASS(klass);
602
603 dc->realize = cadence_uart_realize;
604 dc->vmsd = &vmstate_cadence_uart;
605 rc->phases.enter = cadence_uart_reset_init;
606 rc->phases.hold = cadence_uart_reset_hold;
607 device_class_set_props(dc, cadence_uart_properties);
608 }
609
610static const TypeInfo cadence_uart_info = {
611 .name = TYPE_CADENCE_UART,
612 .parent = TYPE_SYS_BUS_DEVICE,
613 .instance_size = sizeof(CadenceUARTState),
614 .instance_init = cadence_uart_init,
615 .class_init = cadence_uart_class_init,
616};
617
618static void cadence_uart_register_types(void)
619{
620 type_register_static(&cadence_uart_info);
621}
622
623type_init(cadence_uart_register_types)
624
