LXR qemu/hw/char/digic-uart.c

   1/*
   2 * QEMU model of the Canon DIGIC UART block.
   3 *
   4 * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
   5 *
   6 * This model is based on reverse engineering efforts
   7 * made by CHDK (http://chdk.wikia.com) and
   8 * Magic Lantern (http://www.magiclantern.fm) projects
   9 * contributors.
  10 *
  11 * See "Serial terminal" docs here:
  12 *   http://magiclantern.wikia.com/wiki/Register_Map#Misc_Registers
  13 *
  14 * The QEMU model of the Milkymist UART block by Michael Walle
  15 * is used as a template.
  16 *
  17 * This program is free software; you can redistribute it and/or modify
  18 * it under the terms of the GNU General Public License as published by
  19 * the Free Software Foundation; either version 2 of the License, or
  20 * (at your option) any later version.
  21 *
  22 * This program is distributed in the hope that it will be useful,
  23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25 * GNU General Public License for more details.
  26 *
  27 */
  28
  29#include "qemu/osdep.h"
  30#include "hw/sysbus.h"
  31#include "migration/vmstate.h"
  32#include "chardev/char-fe.h"
  33#include "qemu/log.h"
  34#include "qemu/module.h"
  35
  36#include "hw/char/digic-uart.h"
  37#include "hw/qdev-properties.h"
  38#include "hw/qdev-properties-system.h"
  39
  40enum {
  41    ST_RX_RDY = (1 << 0),
  42    ST_TX_RDY = (1 << 1),
  43};
  44
  45static uint64_t digic_uart_read(void *opaque, hwaddr addr,
  46                                unsigned size)
  47{
  48    DigicUartState *s = opaque;
  49    uint64_t ret = 0;
  50
  51    addr >>= 2;
  52
  53    switch (addr) {
  54    case R_RX:
  55        s->reg_st &= ~(ST_RX_RDY);
  56        ret = s->reg_rx;
  57        break;
  58
  59    case R_ST:
  60        ret = s->reg_st;
  61        break;
  62
  63    default:
  64        qemu_log_mask(LOG_UNIMP,
  65                      "digic-uart: read access to unknown register 0x"
  66                      TARGET_FMT_plx "\n", addr << 2);
  67    }
  68
  69    return ret;
  70}
  71
  72static void digic_uart_write(void *opaque, hwaddr addr, uint64_t value,
  73                             unsigned size)
  74{
  75    DigicUartState *s = opaque;
  76    unsigned char ch = value;
  77
  78    addr >>= 2;
  79
  80    switch (addr) {
  81    case R_TX:
  82        /* XXX this blocks entire thread. Rewrite to use
  83         * qemu_chr_fe_write and background I/O callbacks */
  84        qemu_chr_fe_write_all(&s->chr, &ch, 1);
  85        break;
  86
  87    case R_ST:
  88        /*
  89         * Ignore write to R_ST.
  90         *
  91         * The point is that this register is actively used
  92         * during receiving and transmitting symbols,
  93         * but we don't know the function of most of bits.
  94         *
  95         * Ignoring writes to R_ST is only a simplification
  96         * of the model. It has no perceptible side effects
  97         * for existing guests.
  98         */
  99        break;
 100
 101    default:
 102        qemu_log_mask(LOG_UNIMP,
 103                      "digic-uart: write access to unknown register 0x"
 104                      TARGET_FMT_plx "\n", addr << 2);
 105    }
 106}
 107
 108static const MemoryRegionOps uart_mmio_ops = {
 109    .read = digic_uart_read,
 110    .write = digic_uart_write,
 111    .valid = {
 112        .min_access_size = 4,
 113        .max_access_size = 4,
 114    },
 115    .endianness = DEVICE_NATIVE_ENDIAN,
 116};
 117
 118static int uart_can_rx(void *opaque)
 119{
 120    DigicUartState *s = opaque;
 121
 122    return !(s->reg_st & ST_RX_RDY);
 123}
 124
 125static void uart_rx(void *opaque, const uint8_t *buf, int size)
 126{
 127    DigicUartState *s = opaque;
 128
 129    assert(uart_can_rx(opaque));
 130
 131    s->reg_st |= ST_RX_RDY;
 132    s->reg_rx = *buf;
 133}
 134
 135static void uart_event(void *opaque, QEMUChrEvent event)
 136{
 137}
 138
 139static void digic_uart_reset(DeviceState *d)
 140{
 141    DigicUartState *s = DIGIC_UART(d);
 142
 143    s->reg_rx = 0;
 144    s->reg_st = ST_TX_RDY;
 145}
 146
 147static void digic_uart_realize(DeviceState *dev, Error **errp)
 148{
 149    DigicUartState *s = DIGIC_UART(dev);
 150
 151    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
 152                             uart_event, NULL, s, NULL, true);
 153}
 154
 155static void digic_uart_init(Object *obj)
 156{
 157    DigicUartState *s = DIGIC_UART(obj);
 158
 159    memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
 160                          TYPE_DIGIC_UART, 0x18);
 161    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->regs_region);
 162}
 163
 164static const VMStateDescription vmstate_digic_uart = {
 165    .name = "digic-uart",
 166    .version_id = 1,
 167    .minimum_version_id = 1,
 168    .fields = (VMStateField[]) {
 169        VMSTATE_UINT32(reg_rx, DigicUartState),
 170        VMSTATE_UINT32(reg_st, DigicUartState),
 171        VMSTATE_END_OF_LIST()
 172    }
 173};
 174
 175static Property digic_uart_properties[] = {
 176    DEFINE_PROP_CHR("chardev", DigicUartState, chr),
 177    DEFINE_PROP_END_OF_LIST(),
 178};
 179
 180static void digic_uart_class_init(ObjectClass *klass, void *data)
 181{
 182    DeviceClass *dc = DEVICE_CLASS(klass);
 183
 184    dc->realize = digic_uart_realize;
 185    dc->reset = digic_uart_reset;
 186    dc->vmsd = &vmstate_digic_uart;
 187    device_class_set_props(dc, digic_uart_properties);
 188}
 189
 190static const TypeInfo digic_uart_info = {
 191    .name = TYPE_DIGIC_UART,
 192    .parent = TYPE_SYS_BUS_DEVICE,
 193    .instance_size = sizeof(DigicUartState),
 194    .instance_init = digic_uart_init,
 195    .class_init = digic_uart_class_init,
 196};
 197
 198static void digic_uart_register_types(void)
 199{
 200    type_register_static(&digic_uart_info);
 201}
 202
 203type_init(digic_uart_register_types)
 204