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20#include "qemu/osdep.h"
21#include "qemu/units.h"
22#include "hw/hw.h"
23#include "hw/irq.h"
24#include "hw/qdev-properties.h"
25#include "qemu/error-report.h"
26#include "qemu/module.h"
27#include "ui/console.h"
28#include "ui/pixel_ops.h"
29#include "trace.h"
30#include "hw/sysbus.h"
31#include "migration/vmstate.h"
32#include "qom/object.h"
33
34typedef struct G364State {
35
36 uint8_t *vram;
37 uint32_t vram_size;
38 qemu_irq irq;
39 MemoryRegion mem_vram;
40 MemoryRegion mem_ctrl;
41
42 uint8_t color_palette[256][3];
43 uint8_t cursor_palette[3][3];
44 uint16_t cursor[512];
45 uint32_t cursor_position;
46 uint32_t ctla;
47 uint32_t top_of_screen;
48 uint32_t width, height;
49
50 QemuConsole *con;
51 int depth;
52 int blanked;
53} G364State;
54
55#define REG_BOOT 0x000000
56#define REG_DISPLAY 0x000118
57#define REG_VDISPLAY 0x000150
58#define REG_CTLA 0x000300
59#define REG_TOP 0x000400
60#define REG_CURS_PAL 0x000508
61#define REG_CURS_POS 0x000638
62#define REG_CLR_PAL 0x000800
63#define REG_CURS_PAT 0x001000
64#define REG_RESET 0x100000
65
66#define CTLA_FORCE_BLANK 0x00000400
67#define CTLA_NO_CURSOR 0x00800000
68
69#define G364_PAGE_SIZE 4096
70
71static inline int check_dirty(G364State *s, DirtyBitmapSnapshot *snap, ram_addr_t page)
72{
73 return memory_region_snapshot_get_dirty(&s->mem_vram, snap, page, G364_PAGE_SIZE);
74}
75
76static void g364fb_draw_graphic8(G364State *s)
77{
78 DisplaySurface *surface = qemu_console_surface(s->con);
79 DirtyBitmapSnapshot *snap;
80 int i, w;
81 uint8_t *vram;
82 uint8_t *data_display, *dd;
83 ram_addr_t page;
84 int x, y;
85 int xmin, xmax;
86 int ymin, ymax;
87 int xcursor, ycursor;
88 unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b);
89
90 switch (surface_bits_per_pixel(surface)) {
91 case 8:
92 rgb_to_pixel = rgb_to_pixel8;
93 w = 1;
94 break;
95 case 15:
96 rgb_to_pixel = rgb_to_pixel15;
97 w = 2;
98 break;
99 case 16:
100 rgb_to_pixel = rgb_to_pixel16;
101 w = 2;
102 break;
103 case 32:
104 rgb_to_pixel = rgb_to_pixel32;
105 w = 4;
106 break;
107 default:
108 hw_error("g364: unknown host depth %d",
109 surface_bits_per_pixel(surface));
110 return;
111 }
112
113 page = 0;
114
115 x = y = 0;
116 xmin = s->width;
117 xmax = 0;
118 ymin = s->height;
119 ymax = 0;
120
121 if (!(s->ctla & CTLA_NO_CURSOR)) {
122 xcursor = s->cursor_position >> 12;
123 ycursor = s->cursor_position & 0xfff;
124 } else {
125 xcursor = ycursor = -65;
126 }
127
128 vram = s->vram + s->top_of_screen;
129
130 data_display = dd = surface_data(surface);
131 snap = memory_region_snapshot_and_clear_dirty(&s->mem_vram, 0, s->vram_size,
132 DIRTY_MEMORY_VGA);
133 while (y < s->height) {
134 if (check_dirty(s, snap, page)) {
135 if (y < ymin)
136 ymin = ymax = y;
137 if (x < xmin)
138 xmin = x;
139 for (i = 0; i < G364_PAGE_SIZE; i++) {
140 uint8_t index;
141 unsigned int color;
142 if (unlikely((y >= ycursor && y < ycursor + 64) &&
143 (x >= xcursor && x < xcursor + 64))) {
144
145 int xdiff = x - xcursor;
146 uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8];
147 int op = (curs >> ((xdiff & 7) * 2)) & 3;
148 if (likely(op == 0)) {
149
150 index = *vram;
151 color = (*rgb_to_pixel)(
152 s->color_palette[index][0],
153 s->color_palette[index][1],
154 s->color_palette[index][2]);
155 } else {
156
157 index = op - 1;
158 color = (*rgb_to_pixel)(
159 s->cursor_palette[index][0],
160 s->cursor_palette[index][1],
161 s->cursor_palette[index][2]);
162 }
163 } else {
164
165 index = *vram;
166 color = (*rgb_to_pixel)(
167 s->color_palette[index][0],
168 s->color_palette[index][1],
169 s->color_palette[index][2]);
170 }
171 memcpy(dd, &color, w);
172 dd += w;
173 x++;
174 vram++;
175 if (x == s->width) {
176 xmax = s->width - 1;
177 y++;
178 if (y == s->height) {
179 ymax = s->height - 1;
180 goto done;
181 }
182 data_display = dd = data_display + surface_stride(surface);
183 xmin = 0;
184 x = 0;
185 }
186 }
187 if (x > xmax)
188 xmax = x;
189 if (y > ymax)
190 ymax = y;
191 } else {
192 int dy;
193 if (xmax || ymax) {
194 dpy_gfx_update(s->con, xmin, ymin,
195 xmax - xmin + 1, ymax - ymin + 1);
196 xmin = s->width;
197 xmax = 0;
198 ymin = s->height;
199 ymax = 0;
200 }
201 x += G364_PAGE_SIZE;
202 dy = x / s->width;
203 x = x % s->width;
204 y += dy;
205 vram += G364_PAGE_SIZE;
206 data_display += dy * surface_stride(surface);
207 dd = data_display + x * w;
208 }
209 page += G364_PAGE_SIZE;
210 }
211
212done:
213 if (xmax || ymax) {
214 dpy_gfx_update(s->con, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
215 }
216 g_free(snap);
217}
218
219static void g364fb_draw_blank(G364State *s)
220{
221 DisplaySurface *surface = qemu_console_surface(s->con);
222 int i, w;
223 uint8_t *d;
224
225 if (s->blanked) {
226
227 return;
228 }
229
230 w = s->width * surface_bytes_per_pixel(surface);
231 d = surface_data(surface);
232 for (i = 0; i < s->height; i++) {
233 memset(d, 0, w);
234 d += surface_stride(surface);
235 }
236
237 dpy_gfx_update_full(s->con);
238 s->blanked = 1;
239}
240
241static void g364fb_update_display(void *opaque)
242{
243 G364State *s = opaque;
244 DisplaySurface *surface = qemu_console_surface(s->con);
245
246 qemu_flush_coalesced_mmio_buffer();
247
248 if (s->width == 0 || s->height == 0)
249 return;
250
251 if (s->width != surface_width(surface) ||
252 s->height != surface_height(surface)) {
253 qemu_console_resize(s->con, s->width, s->height);
254 }
255
256 if (s->ctla & CTLA_FORCE_BLANK) {
257 g364fb_draw_blank(s);
258 } else if (s->depth == 8) {
259 g364fb_draw_graphic8(s);
260 } else {
261 error_report("g364: unknown guest depth %d", s->depth);
262 }
263
264 qemu_irq_raise(s->irq);
265}
266
267static inline void g364fb_invalidate_display(void *opaque)
268{
269 G364State *s = opaque;
270
271 s->blanked = 0;
272 memory_region_set_dirty(&s->mem_vram, 0, s->vram_size);
273}
274
275static void g364fb_reset(G364State *s)
276{
277 qemu_irq_lower(s->irq);
278
279 memset(s->color_palette, 0, sizeof(s->color_palette));
280 memset(s->cursor_palette, 0, sizeof(s->cursor_palette));
281 memset(s->cursor, 0, sizeof(s->cursor));
282 s->cursor_position = 0;
283 s->ctla = 0;
284 s->top_of_screen = 0;
285 s->width = s->height = 0;
286 memset(s->vram, 0, s->vram_size);
287 g364fb_invalidate_display(s);
288}
289
290
291static uint64_t g364fb_ctrl_read(void *opaque,
292 hwaddr addr,
293 unsigned int size)
294{
295 G364State *s = opaque;
296 uint32_t val;
297
298 if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
299
300 int idx = (addr - REG_CURS_PAT) >> 3;
301 val = s->cursor[idx];
302 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
303
304 int idx = (addr - REG_CURS_PAL) >> 3;
305 val = ((uint32_t)s->cursor_palette[idx][0] << 16);
306 val |= ((uint32_t)s->cursor_palette[idx][1] << 8);
307 val |= ((uint32_t)s->cursor_palette[idx][2] << 0);
308 } else {
309 switch (addr) {
310 case REG_DISPLAY:
311 val = s->width / 4;
312 break;
313 case REG_VDISPLAY:
314 val = s->height * 2;
315 break;
316 case REG_CTLA:
317 val = s->ctla;
318 break;
319 default:
320 {
321 error_report("g364: invalid read at [" TARGET_FMT_plx "]",
322 addr);
323 val = 0;
324 break;
325 }
326 }
327 }
328
329 trace_g364fb_read(addr, val);
330
331 return val;
332}
333
334static void g364fb_update_depth(G364State *s)
335{
336 static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 };
337 s->depth = depths[(s->ctla & 0x00700000) >> 20];
338}
339
340static void g364_invalidate_cursor_position(G364State *s)
341{
342 DisplaySurface *surface = qemu_console_surface(s->con);
343 int ymin, ymax, start, end;
344
345
346 ymin = s->cursor_position & 0xfff;
347 ymax = MIN(s->height, ymin + 64);
348 start = ymin * surface_stride(surface);
349 end = (ymax + 1) * surface_stride(surface);
350
351 memory_region_set_dirty(&s->mem_vram, start, end - start);
352}
353
354static void g364fb_ctrl_write(void *opaque,
355 hwaddr addr,
356 uint64_t val,
357 unsigned int size)
358{
359 G364State *s = opaque;
360
361 trace_g364fb_write(addr, val);
362
363 if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) {
364
365 int idx = (addr - REG_CLR_PAL) >> 3;
366 s->color_palette[idx][0] = (val >> 16) & 0xff;
367 s->color_palette[idx][1] = (val >> 8) & 0xff;
368 s->color_palette[idx][2] = val & 0xff;
369 g364fb_invalidate_display(s);
370 } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
371
372 int idx = (addr - REG_CURS_PAT) >> 3;
373 s->cursor[idx] = val;
374 g364fb_invalidate_display(s);
375 } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
376
377 int idx = (addr - REG_CURS_PAL) >> 3;
378 s->cursor_palette[idx][0] = (val >> 16) & 0xff;
379 s->cursor_palette[idx][1] = (val >> 8) & 0xff;
380 s->cursor_palette[idx][2] = val & 0xff;
381 g364fb_invalidate_display(s);
382 } else {
383 switch (addr) {
384 case REG_BOOT:
385 case 0x00108:
386 case 0x00110:
387 case 0x00120:
388 case 0x00128:
389 case 0x00130:
390 case 0x00138:
391 case 0x00140:
392 case 0x00148:
393 case 0x00158:
394 case 0x00160:
395 case 0x00168:
396 case 0x00170:
397 case 0x00200:
398
399 break;
400 case REG_TOP:
401 s->top_of_screen = val;
402 g364fb_invalidate_display(s);
403 break;
404 case REG_DISPLAY:
405 s->width = val * 4;
406 break;
407 case REG_VDISPLAY:
408 s->height = val / 2;
409 break;
410 case REG_CTLA:
411 s->ctla = val;
412 g364fb_update_depth(s);
413 g364fb_invalidate_display(s);
414 break;
415 case REG_CURS_POS:
416 g364_invalidate_cursor_position(s);
417 s->cursor_position = val;
418 g364_invalidate_cursor_position(s);
419 break;
420 case REG_RESET:
421 g364fb_reset(s);
422 break;
423 default:
424 error_report("g364: invalid write of 0x%" PRIx64
425 " at [" TARGET_FMT_plx "]", val, addr);
426 break;
427 }
428 }
429 qemu_irq_lower(s->irq);
430}
431
432static const MemoryRegionOps g364fb_ctrl_ops = {
433 .read = g364fb_ctrl_read,
434 .write = g364fb_ctrl_write,
435 .endianness = DEVICE_LITTLE_ENDIAN,
436 .impl.min_access_size = 4,
437 .impl.max_access_size = 4,
438};
439
440static int g364fb_post_load(void *opaque, int version_id)
441{
442 G364State *s = opaque;
443
444
445 g364fb_update_depth(s);
446 g364fb_invalidate_display(s);
447
448 return 0;
449}
450
451static const VMStateDescription vmstate_g364fb = {
452 .name = "g364fb",
453 .version_id = 1,
454 .minimum_version_id = 1,
455 .post_load = g364fb_post_load,
456 .fields = (VMStateField[]) {
457 VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, vram_size),
458 VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3),
459 VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9),
460 VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
461 VMSTATE_UINT32(cursor_position, G364State),
462 VMSTATE_UINT32(ctla, G364State),
463 VMSTATE_UINT32(top_of_screen, G364State),
464 VMSTATE_UINT32(width, G364State),
465 VMSTATE_UINT32(height, G364State),
466 VMSTATE_END_OF_LIST()
467 }
468};
469
470static const GraphicHwOps g364fb_ops = {
471 .invalidate = g364fb_invalidate_display,
472 .gfx_update = g364fb_update_display,
473};
474
475static void g364fb_init(DeviceState *dev, G364State *s)
476{
477 s->vram = g_malloc0(s->vram_size);
478
479 s->con = graphic_console_init(dev, 0, &g364fb_ops, s);
480
481 memory_region_init_io(&s->mem_ctrl, OBJECT(dev), &g364fb_ctrl_ops, s,
482 "ctrl", 0x180000);
483 memory_region_init_ram_ptr(&s->mem_vram, NULL, "vram",
484 s->vram_size, s->vram);
485 vmstate_register_ram(&s->mem_vram, dev);
486 memory_region_set_log(&s->mem_vram, true, DIRTY_MEMORY_VGA);
487}
488
489#define TYPE_G364 "sysbus-g364"
490OBJECT_DECLARE_SIMPLE_TYPE(G364SysBusState, G364)
491
492struct G364SysBusState {
493 SysBusDevice parent_obj;
494
495 G364State g364;
496};
497
498static void g364fb_sysbus_realize(DeviceState *dev, Error **errp)
499{
500 G364SysBusState *sbs = G364(dev);
501 G364State *s = &sbs->g364;
502 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
503
504 g364fb_init(dev, s);
505 sysbus_init_irq(sbd, &s->irq);
506 sysbus_init_mmio(sbd, &s->mem_ctrl);
507 sysbus_init_mmio(sbd, &s->mem_vram);
508}
509
510static void g364fb_sysbus_reset(DeviceState *d)
511{
512 G364SysBusState *s = G364(d);
513
514 g364fb_reset(&s->g364);
515}
516
517static Property g364fb_sysbus_properties[] = {
518 DEFINE_PROP_UINT32("vram_size", G364SysBusState, g364.vram_size, 8 * MiB),
519 DEFINE_PROP_END_OF_LIST(),
520};
521
522static void g364fb_sysbus_class_init(ObjectClass *klass, void *data)
523{
524 DeviceClass *dc = DEVICE_CLASS(klass);
525
526 dc->realize = g364fb_sysbus_realize;
527 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
528 dc->desc = "G364 framebuffer";
529 dc->reset = g364fb_sysbus_reset;
530 dc->vmsd = &vmstate_g364fb;
531 device_class_set_props(dc, g364fb_sysbus_properties);
532}
533
534static const TypeInfo g364fb_sysbus_info = {
535 .name = TYPE_G364,
536 .parent = TYPE_SYS_BUS_DEVICE,
537 .instance_size = sizeof(G364SysBusState),
538 .class_init = g364fb_sysbus_class_init,
539};
540
541static void g364fb_register_types(void)
542{
543 type_register_static(&g364fb_sysbus_info);
544}
545
546type_init(g364fb_register_types)
547
