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13#include "qemu/osdep.h"
14#include "qemu/module.h"
15#include "qemu/units.h"
16#include "qapi/error.h"
17#include "cpu.h"
18#include "hw/irq.h"
19#include "hw/pci/pci.h"
20#include "hw/pci/pci_bus.h"
21#include "migration/vmstate.h"
22#include "hppa_sys.h"
23#include "exec/address-spaces.h"
24#include "trace.h"
25#include "qom/object.h"
26
27
28#define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost"
29
30#define DINO_IAR0 0x004
31#define DINO_IODC 0x008
32#define DINO_IRR0 0x00C
33#define DINO_IAR1 0x010
34#define DINO_IRR1 0x014
35#define DINO_IMR 0x018
36#define DINO_IPR 0x01C
37#define DINO_TOC_ADDR 0x020
38#define DINO_ICR 0x024
39#define DINO_ILR 0x028
40#define DINO_IO_COMMAND 0x030
41#define DINO_IO_STATUS 0x034
42#define DINO_IO_CONTROL 0x038
43#define DINO_IO_GSC_ERR_RESP 0x040
44#define DINO_IO_ERR_INFO 0x044
45#define DINO_IO_PCI_ERR_RESP 0x048
46#define DINO_IO_FBB_EN 0x05c
47#define DINO_IO_ADDR_EN 0x060
48#define DINO_PCI_CONFIG_ADDR 0x064
49#define DINO_PCI_CONFIG_DATA 0x068
50#define DINO_PCI_IO_DATA 0x06c
51#define DINO_PCI_MEM_DATA 0x070
52#define DINO_GSC2X_CONFIG 0x7b4
53#define DINO_GMASK 0x800
54#define DINO_PAMR 0x804
55#define DINO_PAPR 0x808
56#define DINO_DAMODE 0x80c
57#define DINO_PCICMD 0x810
58#define DINO_PCISTS 0x814
59#define DINO_MLTIM 0x81c
60#define DINO_BRDG_FEAT 0x820
61#define DINO_PCIROR 0x824
62#define DINO_PCIWOR 0x828
63#define DINO_TLTIM 0x830
64
65#define DINO_IRQS 11
66#define DINO_IRR_MASK 0x5ff
67#define DINO_LOCAL_IRQS (DINO_IRQS + 1)
68#define DINO_MASK_IRQ(x) (1 << (x))
69
70#define PCIINTA 0x001
71#define PCIINTB 0x002
72#define PCIINTC 0x004
73#define PCIINTD 0x008
74#define PCIINTE 0x010
75#define PCIINTF 0x020
76#define GSCEXTINT 0x040
77
78
79
80#define RS232INT 0x400
81
82#define DINO_MEM_CHUNK_SIZE (8 * MiB)
83
84OBJECT_DECLARE_SIMPLE_TYPE(DinoState, DINO_PCI_HOST_BRIDGE)
85
86#define DINO800_REGS (1 + (DINO_TLTIM - DINO_GMASK) / 4)
87static const uint32_t reg800_keep_bits[DINO800_REGS] = {
88 MAKE_64BIT_MASK(0, 1),
89 MAKE_64BIT_MASK(0, 7),
90 MAKE_64BIT_MASK(0, 7),
91 MAKE_64BIT_MASK(0, 8),
92 MAKE_64BIT_MASK(0, 7),
93 MAKE_64BIT_MASK(0, 9),
94 MAKE_64BIT_MASK(0, 32),
95 MAKE_64BIT_MASK(0, 8),
96 MAKE_64BIT_MASK(0, 30),
97 MAKE_64BIT_MASK(0, 24),
98 MAKE_64BIT_MASK(0, 22),
99 MAKE_64BIT_MASK(0, 32),
100 MAKE_64BIT_MASK(0, 9),
101};
102
103struct DinoState {
104 PCIHostState parent_obj;
105
106
107
108 uint32_t config_reg_dino;
109
110 uint32_t iar0;
111 uint32_t iar1;
112 uint32_t imr;
113 uint32_t ipr;
114 uint32_t icr;
115 uint32_t ilr;
116 uint32_t io_fbb_en;
117 uint32_t io_addr_en;
118 uint32_t io_control;
119 uint32_t toc_addr;
120
121 uint32_t reg800[DINO800_REGS];
122
123 MemoryRegion this_mem;
124 MemoryRegion pci_mem;
125 MemoryRegion pci_mem_alias[32];
126
127 AddressSpace bm_as;
128 MemoryRegion bm;
129 MemoryRegion bm_ram_alias;
130 MemoryRegion bm_pci_alias;
131 MemoryRegion bm_cpu_alias;
132};
133
134
135
136
137
138static void gsc_to_pci_forwarding(DinoState *s)
139{
140 uint32_t io_addr_en, tmp;
141 int enabled, i;
142
143 tmp = extract32(s->io_control, 7, 2);
144 enabled = (tmp == 0x01);
145 io_addr_en = s->io_addr_en;
146
147 io_addr_en &= ~(BIT(31) | BIT(0));
148
149 memory_region_transaction_begin();
150 for (i = 1; i < 31; i++) {
151 MemoryRegion *mem = &s->pci_mem_alias[i];
152 if (enabled && (io_addr_en & (1U << i))) {
153 if (!memory_region_is_mapped(mem)) {
154 uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
155 memory_region_add_subregion(get_system_memory(), addr, mem);
156 }
157 } else if (memory_region_is_mapped(mem)) {
158 memory_region_del_subregion(get_system_memory(), mem);
159 }
160 }
161 memory_region_transaction_commit();
162}
163
164static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
165 unsigned size, bool is_write,
166 MemTxAttrs attrs)
167{
168 bool ret = false;
169
170 switch (addr) {
171 case DINO_IAR0:
172 case DINO_IAR1:
173 case DINO_IRR0:
174 case DINO_IRR1:
175 case DINO_IMR:
176 case DINO_IPR:
177 case DINO_ICR:
178 case DINO_ILR:
179 case DINO_IO_CONTROL:
180 case DINO_IO_FBB_EN:
181 case DINO_IO_ADDR_EN:
182 case DINO_PCI_IO_DATA:
183 case DINO_TOC_ADDR:
184 case DINO_GMASK ... DINO_PCISTS:
185 case DINO_MLTIM ... DINO_PCIWOR:
186 case DINO_TLTIM:
187 ret = true;
188 break;
189 case DINO_PCI_IO_DATA + 2:
190 ret = (size <= 2);
191 break;
192 case DINO_PCI_IO_DATA + 1:
193 case DINO_PCI_IO_DATA + 3:
194 ret = (size == 1);
195 }
196 trace_dino_chip_mem_valid(addr, ret);
197 return ret;
198}
199
200static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr,
201 uint64_t *data, unsigned size,
202 MemTxAttrs attrs)
203{
204 DinoState *s = opaque;
205 MemTxResult ret = MEMTX_OK;
206 AddressSpace *io;
207 uint16_t ioaddr;
208 uint32_t val;
209
210 switch (addr) {
211 case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3:
212
213 io = &address_space_io;
214 ioaddr = s->parent_obj.config_reg + (addr & 3);
215 switch (size) {
216 case 1:
217 val = address_space_ldub(io, ioaddr, attrs, &ret);
218 break;
219 case 2:
220 val = address_space_lduw_be(io, ioaddr, attrs, &ret);
221 break;
222 case 4:
223 val = address_space_ldl_be(io, ioaddr, attrs, &ret);
224 break;
225 default:
226 g_assert_not_reached();
227 }
228 break;
229
230 case DINO_IO_FBB_EN:
231 val = s->io_fbb_en;
232 break;
233 case DINO_IO_ADDR_EN:
234 val = s->io_addr_en;
235 break;
236 case DINO_IO_CONTROL:
237 val = s->io_control;
238 break;
239
240 case DINO_IAR0:
241 val = s->iar0;
242 break;
243 case DINO_IAR1:
244 val = s->iar1;
245 break;
246 case DINO_IMR:
247 val = s->imr;
248 break;
249 case DINO_ICR:
250 val = s->icr;
251 break;
252 case DINO_IPR:
253 val = s->ipr;
254
255 s->ipr = 0;
256 break;
257 case DINO_ILR:
258 val = s->ilr;
259 break;
260 case DINO_IRR0:
261 val = s->ilr & s->imr & ~s->icr;
262 break;
263 case DINO_IRR1:
264 val = s->ilr & s->imr & s->icr;
265 break;
266 case DINO_TOC_ADDR:
267 val = s->toc_addr;
268 break;
269 case DINO_GMASK ... DINO_TLTIM:
270 val = s->reg800[(addr - DINO_GMASK) / 4];
271 if (addr == DINO_PAMR) {
272 val &= ~0x01;
273 }
274 if (addr == DINO_MLTIM) {
275 val &= ~0x07;
276 }
277 if (addr == DINO_BRDG_FEAT) {
278 val &= ~(0x10710E0ul | 8);
279 }
280 break;
281
282 default:
283
284 g_assert_not_reached();
285 }
286
287 trace_dino_chip_read(addr, val);
288 *data = val;
289 return ret;
290}
291
292static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr,
293 uint64_t val, unsigned size,
294 MemTxAttrs attrs)
295{
296 DinoState *s = opaque;
297 AddressSpace *io;
298 MemTxResult ret;
299 uint16_t ioaddr;
300 int i;
301
302 trace_dino_chip_write(addr, val);
303
304 switch (addr) {
305 case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3:
306
307 io = &address_space_io;
308 ioaddr = s->parent_obj.config_reg + (addr & 3);
309 switch (size) {
310 case 1:
311 address_space_stb(io, ioaddr, val, attrs, &ret);
312 break;
313 case 2:
314 address_space_stw_be(io, ioaddr, val, attrs, &ret);
315 break;
316 case 4:
317 address_space_stl_be(io, ioaddr, val, attrs, &ret);
318 break;
319 default:
320 g_assert_not_reached();
321 }
322 return ret;
323
324 case DINO_IO_FBB_EN:
325 s->io_fbb_en = val & 0x03;
326 break;
327 case DINO_IO_ADDR_EN:
328 s->io_addr_en = val;
329 gsc_to_pci_forwarding(s);
330 break;
331 case DINO_IO_CONTROL:
332 s->io_control = val;
333 gsc_to_pci_forwarding(s);
334 break;
335
336 case DINO_IAR0:
337 s->iar0 = val;
338 break;
339 case DINO_IAR1:
340 s->iar1 = val;
341 break;
342 case DINO_IMR:
343 s->imr = val;
344 break;
345 case DINO_ICR:
346 s->icr = val;
347 break;
348 case DINO_IPR:
349
350 s->ipr = 0;
351 break;
352 case DINO_TOC_ADDR:
353
354 s->toc_addr = 0xFFFA0030 | (val & 0x1e000);
355 break;
356
357 case DINO_ILR:
358 case DINO_IRR0:
359 case DINO_IRR1:
360
361 break;
362
363 case DINO_GMASK ... DINO_TLTIM:
364 i = (addr - DINO_GMASK) / 4;
365 val &= reg800_keep_bits[i];
366 s->reg800[i] = val;
367 break;
368
369 default:
370
371 g_assert_not_reached();
372 }
373 return MEMTX_OK;
374}
375
376static const MemoryRegionOps dino_chip_ops = {
377 .read_with_attrs = dino_chip_read_with_attrs,
378 .write_with_attrs = dino_chip_write_with_attrs,
379 .endianness = DEVICE_BIG_ENDIAN,
380 .valid = {
381 .min_access_size = 1,
382 .max_access_size = 4,
383 .accepts = dino_chip_mem_valid,
384 },
385 .impl = {
386 .min_access_size = 1,
387 .max_access_size = 4,
388 },
389};
390
391static const VMStateDescription vmstate_dino = {
392 .name = "Dino",
393 .version_id = 2,
394 .minimum_version_id = 1,
395 .fields = (VMStateField[]) {
396 VMSTATE_UINT32(iar0, DinoState),
397 VMSTATE_UINT32(iar1, DinoState),
398 VMSTATE_UINT32(imr, DinoState),
399 VMSTATE_UINT32(ipr, DinoState),
400 VMSTATE_UINT32(icr, DinoState),
401 VMSTATE_UINT32(ilr, DinoState),
402 VMSTATE_UINT32(io_fbb_en, DinoState),
403 VMSTATE_UINT32(io_addr_en, DinoState),
404 VMSTATE_UINT32(io_control, DinoState),
405 VMSTATE_UINT32(toc_addr, DinoState),
406 VMSTATE_END_OF_LIST()
407 }
408};
409
410
411
412static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len)
413{
414 PCIHostState *s = opaque;
415 return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
416}
417
418static void dino_config_data_write(void *opaque, hwaddr addr,
419 uint64_t val, unsigned len)
420{
421 PCIHostState *s = opaque;
422 pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
423}
424
425static const MemoryRegionOps dino_config_data_ops = {
426 .read = dino_config_data_read,
427 .write = dino_config_data_write,
428 .endianness = DEVICE_LITTLE_ENDIAN,
429};
430
431static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned len)
432{
433 DinoState *s = opaque;
434 return s->config_reg_dino;
435}
436
437static void dino_config_addr_write(void *opaque, hwaddr addr,
438 uint64_t val, unsigned len)
439{
440 PCIHostState *s = opaque;
441 DinoState *ds = opaque;
442 ds->config_reg_dino = val;
443 s->config_reg = val & ~3U;
444}
445
446static const MemoryRegionOps dino_config_addr_ops = {
447 .read = dino_config_addr_read,
448 .write = dino_config_addr_write,
449 .valid.min_access_size = 4,
450 .valid.max_access_size = 4,
451 .endianness = DEVICE_BIG_ENDIAN,
452};
453
454static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque,
455 int devfn)
456{
457 DinoState *s = opaque;
458
459 return &s->bm_as;
460}
461
462
463
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468
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471
472
473
474
475
476
477
478static void dino_set_irq(void *opaque, int irq, int level)
479{
480 DinoState *s = opaque;
481 uint32_t bit = 1u << irq;
482 uint32_t old_ilr = s->ilr;
483
484 if (level) {
485 uint32_t ena = bit & ~old_ilr;
486 s->ipr |= ena;
487 s->ilr = old_ilr | bit;
488 if (ena & s->imr) {
489 uint32_t iar = (ena & s->icr ? s->iar1 : s->iar0);
490 stl_be_phys(&address_space_memory, iar & -32, iar & 31);
491 }
492 } else {
493 s->ilr = old_ilr & ~bit;
494 }
495}
496
497static int dino_pci_map_irq(PCIDevice *d, int irq_num)
498{
499 int slot = PCI_SLOT(d->devfn);
500
501 assert(irq_num >= 0 && irq_num <= 3);
502
503 return slot & 0x03;
504}
505
506static void dino_set_timer_irq(void *opaque, int irq, int level)
507{
508
509}
510
511static void dino_set_serial_irq(void *opaque, int irq, int level)
512{
513 dino_set_irq(opaque, 10, level);
514}
515
516PCIBus *dino_init(MemoryRegion *addr_space,
517 qemu_irq *p_rtc_irq, qemu_irq *p_ser_irq)
518{
519 DeviceState *dev;
520 DinoState *s;
521 PCIBus *b;
522 int i;
523
524 dev = qdev_new(TYPE_DINO_PCI_HOST_BRIDGE);
525 s = DINO_PCI_HOST_BRIDGE(dev);
526 s->iar0 = s->iar1 = CPU_HPA + 3;
527 s->toc_addr = 0xFFFA0030;
528
529
530 memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops,
531 s, "dino", 4096);
532 memory_region_add_subregion(addr_space, DINO_HPA, &s->this_mem);
533
534
535 memory_region_init_io(&s->parent_obj.conf_mem, OBJECT(&s->parent_obj),
536 &dino_config_addr_ops, dev, "pci-conf-idx", 4);
537 memory_region_init_io(&s->parent_obj.data_mem, OBJECT(&s->parent_obj),
538 &dino_config_data_ops, dev, "pci-conf-data", 4);
539 memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR,
540 &s->parent_obj.conf_mem);
541 memory_region_add_subregion(&s->this_mem, DINO_CONFIG_DATA,
542 &s->parent_obj.data_mem);
543
544
545 memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 4 * GiB);
546
547 b = pci_register_root_bus(dev, "pci", dino_set_irq, dino_pci_map_irq, s,
548 &s->pci_mem, get_system_io(),
549 PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS);
550 s->parent_obj.bus = b;
551 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
552
553
554 for (i = 1; i < 31; i++) {
555 uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
556 char *name = g_strdup_printf("PCI Outbound Window %d", i);
557 memory_region_init_alias(&s->pci_mem_alias[i], OBJECT(s),
558 name, &s->pci_mem, addr,
559 DINO_MEM_CHUNK_SIZE);
560 g_free(name);
561 }
562
563
564 memory_region_init(&s->bm, OBJECT(s), "bm-dino", 4 * GiB);
565 memory_region_init_alias(&s->bm_ram_alias, OBJECT(s),
566 "bm-system", addr_space, 0,
567 0xf0000000 + DINO_MEM_CHUNK_SIZE);
568 memory_region_init_alias(&s->bm_pci_alias, OBJECT(s),
569 "bm-pci", &s->pci_mem,
570 0xf0000000 + DINO_MEM_CHUNK_SIZE,
571 30 * DINO_MEM_CHUNK_SIZE);
572 memory_region_init_alias(&s->bm_cpu_alias, OBJECT(s),
573 "bm-cpu", addr_space, 0xfff00000,
574 0xfffff);
575 memory_region_add_subregion(&s->bm, 0,
576 &s->bm_ram_alias);
577 memory_region_add_subregion(&s->bm,
578 0xf0000000 + DINO_MEM_CHUNK_SIZE,
579 &s->bm_pci_alias);
580 memory_region_add_subregion(&s->bm, 0xfff00000,
581 &s->bm_cpu_alias);
582 address_space_init(&s->bm_as, &s->bm, "pci-bm");
583 pci_setup_iommu(b, dino_pcihost_set_iommu, s);
584
585 *p_rtc_irq = qemu_allocate_irq(dino_set_timer_irq, s, 0);
586 *p_ser_irq = qemu_allocate_irq(dino_set_serial_irq, s, 0);
587
588 return b;
589}
590
591static void dino_pcihost_class_init(ObjectClass *klass, void *data)
592{
593 DeviceClass *dc = DEVICE_CLASS(klass);
594
595 dc->vmsd = &vmstate_dino;
596}
597
598static const TypeInfo dino_pcihost_info = {
599 .name = TYPE_DINO_PCI_HOST_BRIDGE,
600 .parent = TYPE_PCI_HOST_BRIDGE,
601 .instance_size = sizeof(DinoState),
602 .class_init = dino_pcihost_class_init,
603};
604
605static void dino_register_types(void)
606{
607 type_register_static(&dino_pcihost_info);
608}
609
610type_init(dino_register_types)
611
