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21#include "qemu/osdep.h"
22#include "qemu/error-report.h"
23#include "qemu/module.h"
24#include "qapi/error.h"
25#include "cpu.h"
26#include "qapi/visitor.h"
27#include "hw/i386/apic.h"
28#include "hw/i386/apic_internal.h"
29#include "trace.h"
30#include "hw/boards.h"
31#include "sysemu/hax.h"
32#include "sysemu/kvm.h"
33#include "hw/qdev-properties.h"
34#include "hw/sysbus.h"
35#include "migration/vmstate.h"
36
37static int apic_irq_delivered;
38bool apic_report_tpr_access;
39
40void cpu_set_apic_base(DeviceState *dev, uint64_t val)
41{
42 trace_cpu_set_apic_base(val);
43
44 if (dev) {
45 APICCommonState *s = APIC_COMMON(dev);
46 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
47
48 if (!(s->apicbase & MSR_IA32_APICBASE_EXTD) &&
49 (val & MSR_IA32_APICBASE_EXTD)) {
50 s->id = s->initial_apic_id;
51 }
52 info->set_base(s, val);
53 }
54}
55
56uint64_t cpu_get_apic_base(DeviceState *dev)
57{
58 if (dev) {
59 APICCommonState *s = APIC_COMMON(dev);
60 trace_cpu_get_apic_base((uint64_t)s->apicbase);
61 return s->apicbase;
62 } else {
63 trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);
64 return MSR_IA32_APICBASE_BSP;
65 }
66}
67
68void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
69{
70 APICCommonState *s;
71 APICCommonClass *info;
72
73 if (!dev) {
74 return;
75 }
76
77 s = APIC_COMMON(dev);
78 info = APIC_COMMON_GET_CLASS(s);
79
80 info->set_tpr(s, val);
81}
82
83uint8_t cpu_get_apic_tpr(DeviceState *dev)
84{
85 APICCommonState *s;
86 APICCommonClass *info;
87
88 if (!dev) {
89 return 0;
90 }
91
92 s = APIC_COMMON(dev);
93 info = APIC_COMMON_GET_CLASS(s);
94
95 return info->get_tpr(s);
96}
97
98void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable)
99{
100 APICCommonState *s = APIC_COMMON(dev);
101 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
102
103 apic_report_tpr_access = enable;
104 if (info->enable_tpr_reporting) {
105 info->enable_tpr_reporting(s, enable);
106 }
107}
108
109void apic_enable_vapic(DeviceState *dev, hwaddr paddr)
110{
111 APICCommonState *s = APIC_COMMON(dev);
112 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
113
114 s->vapic_paddr = paddr;
115 info->vapic_base_update(s);
116}
117
118void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
119 TPRAccess access)
120{
121 APICCommonState *s = APIC_COMMON(dev);
122
123 vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
124}
125
126void apic_report_irq_delivered(int delivered)
127{
128 apic_irq_delivered += delivered;
129
130 trace_apic_report_irq_delivered(apic_irq_delivered);
131}
132
133void apic_reset_irq_delivered(void)
134{
135
136
137
138
139 volatile int a_i_d = apic_irq_delivered;
140 trace_apic_reset_irq_delivered(a_i_d);
141
142 apic_irq_delivered = 0;
143}
144
145int apic_get_irq_delivered(void)
146{
147 trace_apic_get_irq_delivered(apic_irq_delivered);
148
149 return apic_irq_delivered;
150}
151
152void apic_deliver_nmi(DeviceState *dev)
153{
154 APICCommonState *s = APIC_COMMON(dev);
155 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
156
157 info->external_nmi(s);
158}
159
160bool apic_next_timer(APICCommonState *s, int64_t current_time)
161{
162 int64_t d;
163
164
165
166
167
168 s->timer_expiry = -1;
169
170 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
171 return false;
172 }
173
174 d = (current_time - s->initial_count_load_time) >> s->count_shift;
175
176 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
177 if (!s->initial_count) {
178 return false;
179 }
180 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
181 ((uint64_t)s->initial_count + 1);
182 } else {
183 if (d >= s->initial_count) {
184 return false;
185 }
186 d = (uint64_t)s->initial_count + 1;
187 }
188 s->next_time = s->initial_count_load_time + (d << s->count_shift);
189 s->timer_expiry = s->next_time;
190 return true;
191}
192
193uint32_t apic_get_current_count(APICCommonState *s)
194{
195 int64_t d;
196 uint32_t val;
197 d = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->initial_count_load_time) >>
198 s->count_shift;
199 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
200
201 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
202 } else {
203 if (d >= s->initial_count) {
204 val = 0;
205 } else {
206 val = s->initial_count - d;
207 }
208 }
209 return val;
210}
211
212void apic_init_reset(DeviceState *dev)
213{
214 APICCommonState *s;
215 APICCommonClass *info;
216 int i;
217
218 if (!dev) {
219 return;
220 }
221 s = APIC_COMMON(dev);
222 s->tpr = 0;
223 s->spurious_vec = 0xff;
224 s->log_dest = 0;
225 s->dest_mode = 0xf;
226 memset(s->isr, 0, sizeof(s->isr));
227 memset(s->tmr, 0, sizeof(s->tmr));
228 memset(s->irr, 0, sizeof(s->irr));
229 for (i = 0; i < APIC_LVT_NB; i++) {
230 s->lvt[i] = APIC_LVT_MASKED;
231 }
232 s->esr = 0;
233 memset(s->icr, 0, sizeof(s->icr));
234 s->divide_conf = 0;
235 s->count_shift = 0;
236 s->initial_count = 0;
237 s->initial_count_load_time = 0;
238 s->next_time = 0;
239 s->wait_for_sipi = !cpu_is_bsp(s->cpu);
240
241 if (s->timer) {
242 timer_del(s->timer);
243 }
244 s->timer_expiry = -1;
245
246 info = APIC_COMMON_GET_CLASS(s);
247 if (info->reset) {
248 info->reset(s);
249 }
250}
251
252void apic_designate_bsp(DeviceState *dev, bool bsp)
253{
254 if (dev == NULL) {
255 return;
256 }
257
258 APICCommonState *s = APIC_COMMON(dev);
259 if (bsp) {
260 s->apicbase |= MSR_IA32_APICBASE_BSP;
261 } else {
262 s->apicbase &= ~MSR_IA32_APICBASE_BSP;
263 }
264}
265
266static void apic_reset_common(DeviceState *dev)
267{
268 APICCommonState *s = APIC_COMMON(dev);
269 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
270 uint32_t bsp;
271
272 bsp = s->apicbase & MSR_IA32_APICBASE_BSP;
273 s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;
274 s->id = s->initial_apic_id;
275
276 apic_reset_irq_delivered();
277
278 s->vapic_paddr = 0;
279 info->vapic_base_update(s);
280
281 apic_init_reset(dev);
282}
283
284static const VMStateDescription vmstate_apic_common;
285
286static void apic_common_realize(DeviceState *dev, Error **errp)
287{
288 APICCommonState *s = APIC_COMMON(dev);
289 APICCommonClass *info;
290 static DeviceState *vapic;
291 uint32_t instance_id = s->initial_apic_id;
292
293
294 assert(instance_id != VMSTATE_INSTANCE_ID_ANY);
295
296 info = APIC_COMMON_GET_CLASS(s);
297 info->realize(dev, errp);
298
299
300 if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
301 !hax_enabled() && current_machine->ram_size >= 1024 * 1024) {
302 vapic = sysbus_create_simple("kvmvapic", -1, NULL);
303 }
304 s->vapic = vapic;
305 if (apic_report_tpr_access && info->enable_tpr_reporting) {
306 info->enable_tpr_reporting(s, true);
307 }
308
309 if (s->legacy_instance_id) {
310 instance_id = VMSTATE_INSTANCE_ID_ANY;
311 }
312 vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common,
313 s, -1, 0, NULL);
314}
315
316static void apic_common_unrealize(DeviceState *dev)
317{
318 APICCommonState *s = APIC_COMMON(dev);
319 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
320
321 vmstate_unregister(NULL, &vmstate_apic_common, s);
322 info->unrealize(dev);
323
324 if (apic_report_tpr_access && info->enable_tpr_reporting) {
325 info->enable_tpr_reporting(s, false);
326 }
327}
328
329static int apic_pre_load(void *opaque)
330{
331 APICCommonState *s = APIC_COMMON(opaque);
332
333
334
335
336
337
338 s->wait_for_sipi = 0;
339 return 0;
340}
341
342static int apic_dispatch_pre_save(void *opaque)
343{
344 APICCommonState *s = APIC_COMMON(opaque);
345 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
346
347 if (info->pre_save) {
348 info->pre_save(s);
349 }
350
351 return 0;
352}
353
354static int apic_dispatch_post_load(void *opaque, int version_id)
355{
356 APICCommonState *s = APIC_COMMON(opaque);
357 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
358
359 if (info->post_load) {
360 info->post_load(s);
361 }
362 return 0;
363}
364
365static bool apic_common_sipi_needed(void *opaque)
366{
367 APICCommonState *s = APIC_COMMON(opaque);
368 return s->wait_for_sipi != 0;
369}
370
371static const VMStateDescription vmstate_apic_common_sipi = {
372 .name = "apic_sipi",
373 .version_id = 1,
374 .minimum_version_id = 1,
375 .needed = apic_common_sipi_needed,
376 .fields = (VMStateField[]) {
377 VMSTATE_INT32(sipi_vector, APICCommonState),
378 VMSTATE_INT32(wait_for_sipi, APICCommonState),
379 VMSTATE_END_OF_LIST()
380 }
381};
382
383static const VMStateDescription vmstate_apic_common = {
384 .name = "apic",
385 .version_id = 3,
386 .minimum_version_id = 3,
387 .pre_load = apic_pre_load,
388 .pre_save = apic_dispatch_pre_save,
389 .post_load = apic_dispatch_post_load,
390 .fields = (VMStateField[]) {
391 VMSTATE_UINT32(apicbase, APICCommonState),
392 VMSTATE_UINT8(id, APICCommonState),
393 VMSTATE_UINT8(arb_id, APICCommonState),
394 VMSTATE_UINT8(tpr, APICCommonState),
395 VMSTATE_UINT32(spurious_vec, APICCommonState),
396 VMSTATE_UINT8(log_dest, APICCommonState),
397 VMSTATE_UINT8(dest_mode, APICCommonState),
398 VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
399 VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
400 VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
401 VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
402 VMSTATE_UINT32(esr, APICCommonState),
403 VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
404 VMSTATE_UINT32(divide_conf, APICCommonState),
405 VMSTATE_INT32(count_shift, APICCommonState),
406 VMSTATE_UINT32(initial_count, APICCommonState),
407 VMSTATE_INT64(initial_count_load_time, APICCommonState),
408 VMSTATE_INT64(next_time, APICCommonState),
409 VMSTATE_INT64(timer_expiry,
410 APICCommonState),
411 VMSTATE_END_OF_LIST()
412 },
413 .subsections = (const VMStateDescription*[]) {
414 &vmstate_apic_common_sipi,
415 NULL
416 }
417};
418
419static Property apic_properties_common[] = {
420 DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
421 DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
422 true),
423 DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id,
424 false),
425 DEFINE_PROP_END_OF_LIST(),
426};
427
428static void apic_common_get_id(Object *obj, Visitor *v, const char *name,
429 void *opaque, Error **errp)
430{
431 APICCommonState *s = APIC_COMMON(obj);
432 uint32_t value;
433
434 value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id;
435 visit_type_uint32(v, name, &value, errp);
436}
437
438static void apic_common_set_id(Object *obj, Visitor *v, const char *name,
439 void *opaque, Error **errp)
440{
441 APICCommonState *s = APIC_COMMON(obj);
442 DeviceState *dev = DEVICE(obj);
443 uint32_t value;
444
445 if (dev->realized) {
446 qdev_prop_set_after_realize(dev, name, errp);
447 return;
448 }
449
450 if (!visit_type_uint32(v, name, &value, errp)) {
451 return;
452 }
453
454 s->initial_apic_id = value;
455 s->id = (uint8_t)value;
456}
457
458static void apic_common_initfn(Object *obj)
459{
460 APICCommonState *s = APIC_COMMON(obj);
461
462 s->id = s->initial_apic_id = -1;
463 object_property_add(obj, "id", "uint32",
464 apic_common_get_id,
465 apic_common_set_id, NULL, NULL);
466}
467
468static void apic_common_class_init(ObjectClass *klass, void *data)
469{
470 DeviceClass *dc = DEVICE_CLASS(klass);
471
472 dc->reset = apic_reset_common;
473 device_class_set_props(dc, apic_properties_common);
474 dc->realize = apic_common_realize;
475 dc->unrealize = apic_common_unrealize;
476
477
478
479
480 dc->user_creatable = false;
481}
482
483static const TypeInfo apic_common_type = {
484 .name = TYPE_APIC_COMMON,
485 .parent = TYPE_DEVICE,
486 .instance_size = sizeof(APICCommonState),
487 .instance_init = apic_common_initfn,
488 .class_size = sizeof(APICCommonClass),
489 .class_init = apic_common_class_init,
490 .abstract = true,
491};
492
493static void apic_common_register_types(void)
494{
495 type_register_static(&apic_common_type);
496}
497
498type_init(apic_common_register_types)
499