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22#include "qemu/osdep.h"
23#include "qapi/error.h"
24#include "hw/intc/arm_gicv3_common.h"
25#include "hw/sysbus.h"
26#include "qemu/error-report.h"
27#include "qemu/module.h"
28#include "sysemu/kvm.h"
29#include "sysemu/runstate.h"
30#include "kvm_arm.h"
31#include "gicv3_internal.h"
32#include "vgic_common.h"
33#include "migration/blocker.h"
34#include "qom/object.h"
35
36#ifdef DEBUG_GICV3_KVM
37#define DPRINTF(fmt, ...) \
38 do { fprintf(stderr, "kvm_gicv3: " fmt, ## __VA_ARGS__); } while (0)
39#else
40#define DPRINTF(fmt, ...) \
41 do { } while (0)
42#endif
43
44#define TYPE_KVM_ARM_GICV3 "kvm-arm-gicv3"
45typedef struct KVMARMGICv3Class KVMARMGICv3Class;
46
47DECLARE_OBJ_CHECKERS(GICv3State, KVMARMGICv3Class,
48 KVM_ARM_GICV3, TYPE_KVM_ARM_GICV3)
49
50#define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \
51 (ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
52 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
53 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
54 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
55 ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
56
57#define ICC_PMR_EL1 \
58 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0)
59#define ICC_BPR0_EL1 \
60 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3)
61#define ICC_AP0R_EL1(n) \
62 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n)
63#define ICC_AP1R_EL1(n) \
64 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n)
65#define ICC_BPR1_EL1 \
66 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3)
67#define ICC_CTLR_EL1 \
68 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4)
69#define ICC_SRE_EL1 \
70 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5)
71#define ICC_IGRPEN0_EL1 \
72 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6)
73#define ICC_IGRPEN1_EL1 \
74 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7)
75
76struct KVMARMGICv3Class {
77 ARMGICv3CommonClass parent_class;
78 DeviceRealize parent_realize;
79 void (*parent_reset)(DeviceState *dev);
80};
81
82static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level)
83{
84 GICv3State *s = (GICv3State *)opaque;
85
86 kvm_arm_gic_set_irq(s->num_irq, irq, level);
87}
88
89#define KVM_VGIC_ATTR(reg, typer) \
90 ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg))
91
92static inline void kvm_gicd_access(GICv3State *s, int offset,
93 uint32_t *val, bool write)
94{
95 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
96 KVM_VGIC_ATTR(offset, 0),
97 val, write, &error_abort);
98}
99
100static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu,
101 uint32_t *val, bool write)
102{
103 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS,
104 KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer),
105 val, write, &error_abort);
106}
107
108static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu,
109 uint64_t *val, bool write)
110{
111 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
112 KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer),
113 val, write, &error_abort);
114}
115
116static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu,
117 uint32_t *val, bool write)
118{
119 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO,
120 KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) |
121 (VGIC_LEVEL_INFO_LINE_LEVEL <<
122 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT),
123 val, write, &error_abort);
124}
125
126
127
128
129
130#define for_each_dist_irq_reg(_irq, _max, _field_width) \
131 for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width))
132
133static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp)
134{
135 uint32_t reg, *field;
136 int irq;
137
138
139
140
141
142
143
144 field = (uint32_t *)(bmp + GIC_INTERNAL);
145 offset += (GIC_INTERNAL * 8) / 8;
146 for_each_dist_irq_reg(irq, s->num_irq, 8) {
147 kvm_gicd_access(s, offset, ®, false);
148 *field = reg;
149 offset += 4;
150 field++;
151 }
152}
153
154static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp)
155{
156 uint32_t reg, *field;
157 int irq;
158
159
160
161
162
163
164
165 field = (uint32_t *)(bmp + GIC_INTERNAL);
166 offset += (GIC_INTERNAL * 8) / 8;
167 for_each_dist_irq_reg(irq, s->num_irq, 8) {
168 reg = *field;
169 kvm_gicd_access(s, offset, ®, true);
170 offset += 4;
171 field++;
172 }
173}
174
175static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset,
176 uint32_t *bmp)
177{
178 uint32_t reg;
179 int irq;
180
181
182
183
184
185
186
187
188 offset += (GIC_INTERNAL * 2) / 8;
189 for_each_dist_irq_reg(irq, s->num_irq, 2) {
190 kvm_gicd_access(s, offset, ®, false);
191 reg = half_unshuffle32(reg >> 1);
192 if (irq % 32 != 0) {
193 reg = (reg << 16);
194 }
195 *gic_bmp_ptr32(bmp, irq) |= reg;
196 offset += 4;
197 }
198}
199
200static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset,
201 uint32_t *bmp)
202{
203 uint32_t reg;
204 int irq;
205
206
207
208
209
210
211
212
213 offset += (GIC_INTERNAL * 2) / 8;
214 for_each_dist_irq_reg(irq, s->num_irq, 2) {
215 reg = *gic_bmp_ptr32(bmp, irq);
216 if (irq % 32 != 0) {
217 reg = (reg & 0xffff0000) >> 16;
218 } else {
219 reg = reg & 0xffff;
220 }
221 reg = half_shuffle32(reg) << 1;
222 kvm_gicd_access(s, offset, ®, true);
223 offset += 4;
224 }
225}
226
227static void kvm_gic_get_line_level_bmp(GICv3State *s, uint32_t *bmp)
228{
229 uint32_t reg;
230 int irq;
231
232 for_each_dist_irq_reg(irq, s->num_irq, 1) {
233 kvm_gic_line_level_access(s, irq, 0, ®, false);
234 *gic_bmp_ptr32(bmp, irq) = reg;
235 }
236}
237
238static void kvm_gic_put_line_level_bmp(GICv3State *s, uint32_t *bmp)
239{
240 uint32_t reg;
241 int irq;
242
243 for_each_dist_irq_reg(irq, s->num_irq, 1) {
244 reg = *gic_bmp_ptr32(bmp, irq);
245 kvm_gic_line_level_access(s, irq, 0, ®, true);
246 }
247}
248
249
250static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp)
251{
252 uint32_t reg;
253 int irq;
254
255
256
257
258
259
260
261
262
263 offset += (GIC_INTERNAL * 1) / 8;
264 for_each_dist_irq_reg(irq, s->num_irq, 1) {
265 kvm_gicd_access(s, offset, ®, false);
266 *gic_bmp_ptr32(bmp, irq) = reg;
267 offset += 4;
268 }
269}
270
271static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
272 uint32_t clroffset, uint32_t *bmp)
273{
274 uint32_t reg;
275 int irq;
276
277
278
279
280
281
282
283
284
285 offset += (GIC_INTERNAL * 1) / 8;
286 if (clroffset != 0) {
287 clroffset += (GIC_INTERNAL * 1) / 8;
288 }
289
290 for_each_dist_irq_reg(irq, s->num_irq, 1) {
291
292
293
294
295 if (clroffset != 0) {
296 reg = 0;
297 kvm_gicd_access(s, clroffset, ®, true);
298 clroffset += 4;
299 }
300 reg = *gic_bmp_ptr32(bmp, irq);
301 kvm_gicd_access(s, offset, ®, true);
302 offset += 4;
303 }
304}
305
306static void kvm_arm_gicv3_check(GICv3State *s)
307{
308 uint32_t reg;
309 uint32_t num_irq;
310
311
312 kvm_gicd_access(s, GICD_TYPER, ®, false);
313 num_irq = ((reg & 0x1f) + 1) * 32;
314
315 if (num_irq < s->num_irq) {
316 error_report("Model requests %u IRQs, but kernel supports max %u",
317 s->num_irq, num_irq);
318 abort();
319 }
320}
321
322static void kvm_arm_gicv3_put(GICv3State *s)
323{
324 uint32_t regl, regh, reg;
325 uint64_t reg64, redist_typer;
326 int ncpu, i;
327
328 kvm_arm_gicv3_check(s);
329
330 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false);
331 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false);
332 redist_typer = ((uint64_t)regh << 32) | regl;
333
334 reg = s->gicd_ctlr;
335 kvm_gicd_access(s, GICD_CTLR, ®, true);
336
337 if (redist_typer & GICR_TYPER_PLPIS) {
338
339
340
341
342 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
343 GICv3CPUState *c = &s->cpu[ncpu];
344
345 reg64 = c->gicr_propbaser;
346 regl = (uint32_t)reg64;
347 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, true);
348 regh = (uint32_t)(reg64 >> 32);
349 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true);
350
351 reg64 = c->gicr_pendbaser;
352 regl = (uint32_t)reg64;
353 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, true);
354 regh = (uint32_t)(reg64 >> 32);
355 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, true);
356 }
357 }
358
359
360
361 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
362 GICv3CPUState *c = &s->cpu[ncpu];
363
364 reg = c->gicr_ctlr;
365 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, true);
366
367 reg = c->gicr_statusr[GICV3_NS];
368 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, true);
369
370 reg = c->gicr_waker;
371 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, true);
372
373 reg = c->gicr_igroupr0;
374 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, true);
375
376 reg = ~0;
377 kvm_gicr_access(s, GICR_ICENABLER0, ncpu, ®, true);
378 reg = c->gicr_ienabler0;
379 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, true);
380
381
382 reg = half_shuffle32(c->edge_trigger >> 16) << 1;
383 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, true);
384
385 reg = c->level;
386 kvm_gic_line_level_access(s, 0, ncpu, ®, true);
387
388 reg = ~0;
389 kvm_gicr_access(s, GICR_ICPENDR0, ncpu, ®, true);
390 reg = c->gicr_ipendr0;
391 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, true);
392
393 reg = ~0;
394 kvm_gicr_access(s, GICR_ICACTIVER0, ncpu, ®, true);
395 reg = c->gicr_iactiver0;
396 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, true);
397
398 for (i = 0; i < GIC_INTERNAL; i += 4) {
399 reg = c->gicr_ipriorityr[i] |
400 (c->gicr_ipriorityr[i + 1] << 8) |
401 (c->gicr_ipriorityr[i + 2] << 16) |
402 (c->gicr_ipriorityr[i + 3] << 24);
403 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, true);
404 }
405 }
406
407
408 reg = s->gicd_statusr[GICV3_NS];
409 kvm_gicd_access(s, GICD_STATUSR, ®, true);
410
411
412 kvm_dist_putbmp(s, GICD_ISENABLER, GICD_ICENABLER, s->enabled);
413
414
415 kvm_dist_putbmp(s, GICD_IGROUPR, 0, s->group);
416
417
418
419
420
421
422
423
424 for (i = GIC_INTERNAL; i < s->num_irq; i++) {
425 uint32_t offset;
426
427 offset = GICD_IROUTER + (sizeof(uint32_t) * i);
428 reg = (uint32_t)s->gicd_irouter[i];
429 kvm_gicd_access(s, offset, ®, true);
430
431 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4;
432 reg = (uint32_t)(s->gicd_irouter[i] >> 32);
433 kvm_gicd_access(s, offset, ®, true);
434 }
435
436
437
438
439
440 kvm_dist_put_edge_trigger(s, GICD_ICFGR, s->edge_trigger);
441
442
443 kvm_gic_put_line_level_bmp(s, s->level);
444
445
446 kvm_dist_putbmp(s, GICD_ISPENDR, GICD_ICPENDR, s->pending);
447
448
449 kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active);
450
451
452 kvm_dist_put_priority(s, GICD_IPRIORITYR, s->gicd_ipriority);
453
454
455
456 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
457 GICv3CPUState *c = &s->cpu[ncpu];
458 int num_pri_bits;
459
460 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true);
461 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu,
462 &c->icc_ctlr_el1[GICV3_NS], true);
463 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu,
464 &c->icc_igrpen[GICV3_G0], true);
465 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu,
466 &c->icc_igrpen[GICV3_G1NS], true);
467 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, true);
468 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], true);
469 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], true);
470
471 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
472 ICC_CTLR_EL1_PRIBITS_MASK) >>
473 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
474
475 switch (num_pri_bits) {
476 case 7:
477 reg64 = c->icc_apr[GICV3_G0][3];
478 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, true);
479 reg64 = c->icc_apr[GICV3_G0][2];
480 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, true);
481
482 case 6:
483 reg64 = c->icc_apr[GICV3_G0][1];
484 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, true);
485
486 default:
487 reg64 = c->icc_apr[GICV3_G0][0];
488 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, true);
489 }
490
491 switch (num_pri_bits) {
492 case 7:
493 reg64 = c->icc_apr[GICV3_G1NS][3];
494 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, true);
495 reg64 = c->icc_apr[GICV3_G1NS][2];
496 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, true);
497
498 case 6:
499 reg64 = c->icc_apr[GICV3_G1NS][1];
500 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, true);
501
502 default:
503 reg64 = c->icc_apr[GICV3_G1NS][0];
504 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, true);
505 }
506 }
507}
508
509static void kvm_arm_gicv3_get(GICv3State *s)
510{
511 uint32_t regl, regh, reg;
512 uint64_t reg64, redist_typer;
513 int ncpu, i;
514
515 kvm_arm_gicv3_check(s);
516
517 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false);
518 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false);
519 redist_typer = ((uint64_t)regh << 32) | regl;
520
521 kvm_gicd_access(s, GICD_CTLR, ®, false);
522 s->gicd_ctlr = reg;
523
524
525
526 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
527 GICv3CPUState *c = &s->cpu[ncpu];
528
529 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, false);
530 c->gicr_ctlr = reg;
531
532 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, false);
533 c->gicr_statusr[GICV3_NS] = reg;
534
535 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, false);
536 c->gicr_waker = reg;
537
538 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, false);
539 c->gicr_igroupr0 = reg;
540 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, false);
541 c->gicr_ienabler0 = reg;
542 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, false);
543 c->edge_trigger = half_unshuffle32(reg >> 1) << 16;
544 kvm_gic_line_level_access(s, 0, ncpu, ®, false);
545 c->level = reg;
546 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, false);
547 c->gicr_ipendr0 = reg;
548 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, false);
549 c->gicr_iactiver0 = reg;
550
551 for (i = 0; i < GIC_INTERNAL; i += 4) {
552 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, false);
553 c->gicr_ipriorityr[i] = extract32(reg, 0, 8);
554 c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8);
555 c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8);
556 c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8);
557 }
558 }
559
560 if (redist_typer & GICR_TYPER_PLPIS) {
561 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
562 GICv3CPUState *c = &s->cpu[ncpu];
563
564 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, false);
565 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, false);
566 c->gicr_propbaser = ((uint64_t)regh << 32) | regl;
567
568 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, false);
569 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, false);
570 c->gicr_pendbaser = ((uint64_t)regh << 32) | regl;
571 }
572 }
573
574
575
576 kvm_gicd_access(s, GICD_STATUSR, ®, false);
577 s->gicd_statusr[GICV3_NS] = reg;
578
579
580 kvm_dist_getbmp(s, GICD_IGROUPR, s->group);
581
582
583 kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled);
584
585
586 kvm_gic_get_line_level_bmp(s, s->level);
587
588 kvm_dist_getbmp(s, GICD_ISPENDR, s->pending);
589
590
591 kvm_dist_getbmp(s, GICD_ISACTIVER, s->active);
592
593
594 kvm_dist_get_edge_trigger(s, GICD_ICFGR, s->edge_trigger);
595
596
597 kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority);
598
599
600 for (i = GIC_INTERNAL; i < s->num_irq; i++) {
601 uint32_t offset;
602
603 offset = GICD_IROUTER + (sizeof(uint32_t) * i);
604 kvm_gicd_access(s, offset, ®l, false);
605 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4;
606 kvm_gicd_access(s, offset, ®h, false);
607 s->gicd_irouter[i] = ((uint64_t)regh << 32) | regl;
608 }
609
610
611
612
613
614 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
615 GICv3CPUState *c = &s->cpu[ncpu];
616 int num_pri_bits;
617
618 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false);
619 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu,
620 &c->icc_ctlr_el1[GICV3_NS], false);
621 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu,
622 &c->icc_igrpen[GICV3_G0], false);
623 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu,
624 &c->icc_igrpen[GICV3_G1NS], false);
625 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, false);
626 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], false);
627 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], false);
628 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
629 ICC_CTLR_EL1_PRIBITS_MASK) >>
630 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
631
632 switch (num_pri_bits) {
633 case 7:
634 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, false);
635 c->icc_apr[GICV3_G0][3] = reg64;
636 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, false);
637 c->icc_apr[GICV3_G0][2] = reg64;
638
639 case 6:
640 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, false);
641 c->icc_apr[GICV3_G0][1] = reg64;
642
643 default:
644 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, false);
645 c->icc_apr[GICV3_G0][0] = reg64;
646 }
647
648 switch (num_pri_bits) {
649 case 7:
650 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, false);
651 c->icc_apr[GICV3_G1NS][3] = reg64;
652 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, false);
653 c->icc_apr[GICV3_G1NS][2] = reg64;
654
655 case 6:
656 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, false);
657 c->icc_apr[GICV3_G1NS][1] = reg64;
658
659 default:
660 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, false);
661 c->icc_apr[GICV3_G1NS][0] = reg64;
662 }
663 }
664}
665
666static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
667{
668 GICv3State *s;
669 GICv3CPUState *c;
670
671 c = (GICv3CPUState *)env->gicv3state;
672 s = c->gic;
673
674 c->icc_pmr_el1 = 0;
675 c->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
676 c->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
677 c->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR;
678
679 c->icc_sre_el1 = 0x7;
680 memset(c->icc_apr, 0, sizeof(c->icc_apr));
681 memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen));
682
683 if (s->migration_blocker) {
684 return;
685 }
686
687
688 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
689 KVM_VGIC_ATTR(ICC_CTLR_EL1, c->gicr_typer),
690 &c->icc_ctlr_el1[GICV3_NS], false, &error_abort);
691
692 c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
693}
694
695static void kvm_arm_gicv3_reset(DeviceState *dev)
696{
697 GICv3State *s = ARM_GICV3_COMMON(dev);
698 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s);
699
700 DPRINTF("Reset\n");
701
702 kgc->parent_reset(dev);
703
704 if (s->migration_blocker) {
705 DPRINTF("Cannot put kernel gic state, no kernel interface\n");
706 return;
707 }
708
709 kvm_arm_gicv3_put(s);
710}
711
712
713
714
715
716
717
718
719static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
720 { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH,
721 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
722
723
724
725
726 .type = ARM_CP_NO_RAW,
727 .access = PL1_RW,
728 .readfn = arm_cp_read_zero,
729 .writefn = arm_cp_write_ignore,
730
731
732
733
734
735 .resetfn = arm_gicv3_icc_reset,
736 },
737 REGINFO_SENTINEL
738};
739
740
741
742
743
744
745
746static void vm_change_state_handler(void *opaque, bool running,
747 RunState state)
748{
749 GICv3State *s = (GICv3State *)opaque;
750 Error *err = NULL;
751 int ret;
752
753 if (running) {
754 return;
755 }
756
757 ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
758 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES,
759 NULL, true, &err);
760 if (err) {
761 error_report_err(err);
762 }
763 if (ret < 0 && ret != -EFAULT) {
764 abort();
765 }
766}
767
768
769static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
770{
771 GICv3State *s = KVM_ARM_GICV3(dev);
772 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s);
773 bool multiple_redist_region_allowed;
774 Error *local_err = NULL;
775 int i;
776
777 DPRINTF("kvm_arm_gicv3_realize\n");
778
779 kgc->parent_realize(dev, &local_err);
780 if (local_err) {
781 error_propagate(errp, local_err);
782 return;
783 }
784
785 if (s->security_extn) {
786 error_setg(errp, "the in-kernel VGICv3 does not implement the "
787 "security extensions");
788 return;
789 }
790
791 gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL, &local_err);
792 if (local_err) {
793 error_propagate(errp, local_err);
794 return;
795 }
796
797 for (i = 0; i < s->num_cpu; i++) {
798 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
799
800 define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
801 }
802
803
804 s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false);
805 if (s->dev_fd < 0) {
806 error_setg_errno(errp, -s->dev_fd, "error creating in-kernel VGIC");
807 return;
808 }
809
810 multiple_redist_region_allowed =
811 kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
812 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION);
813
814 if (!multiple_redist_region_allowed && s->nb_redist_regions > 1) {
815 error_setg(errp, "Multiple VGICv3 redistributor regions are not "
816 "supported by this host kernel");
817 error_append_hint(errp, "A maximum of %d VCPUs can be used",
818 s->redist_region_count[0]);
819 return;
820 }
821
822 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
823 0, &s->num_irq, true, &error_abort);
824
825
826 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
827 KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort);
828
829 kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
830 KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0);
831
832 if (!multiple_redist_region_allowed) {
833 kvm_arm_register_device(&s->iomem_redist[0], -1,
834 KVM_DEV_ARM_VGIC_GRP_ADDR,
835 KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0);
836 } else {
837
838
839
840
841 for (i = s->nb_redist_regions - 1; i >= 0; i--) {
842
843 uint64_t addr_ormask =
844 i | ((uint64_t)s->redist_region_count[i] << 52);
845
846 kvm_arm_register_device(&s->iomem_redist[i], -1,
847 KVM_DEV_ARM_VGIC_GRP_ADDR,
848 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION,
849 s->dev_fd, addr_ormask);
850 }
851 }
852
853 if (kvm_has_gsi_routing()) {
854
855 for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
856 kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
857 }
858
859 kvm_gsi_routing_allowed = true;
860
861 kvm_irqchip_commit_routes(kvm_state);
862 }
863
864 if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
865 GICD_CTLR)) {
866 error_setg(&s->migration_blocker, "This operating system kernel does "
867 "not support vGICv3 migration");
868 if (migrate_add_blocker(s->migration_blocker, errp) < 0) {
869 error_free(s->migration_blocker);
870 return;
871 }
872 }
873 if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
874 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) {
875 qemu_add_vm_change_state_handler(vm_change_state_handler, s);
876 }
877}
878
879static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
880{
881 DeviceClass *dc = DEVICE_CLASS(klass);
882 ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);
883 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass);
884
885 agcc->pre_save = kvm_arm_gicv3_get;
886 agcc->post_load = kvm_arm_gicv3_put;
887 device_class_set_parent_realize(dc, kvm_arm_gicv3_realize,
888 &kgc->parent_realize);
889 device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_reset);
890}
891
892static const TypeInfo kvm_arm_gicv3_info = {
893 .name = TYPE_KVM_ARM_GICV3,
894 .parent = TYPE_ARM_GICV3_COMMON,
895 .instance_size = sizeof(GICv3State),
896 .class_init = kvm_arm_gicv3_class_init,
897 .class_size = sizeof(KVMARMGICv3Class),
898};
899
900static void kvm_arm_gicv3_register_types(void)
901{
902 type_register_static(&kvm_arm_gicv3_info);
903}
904
905type_init(kvm_arm_gicv3_register_types)
906