1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#include "qemu/osdep.h"
27#include "qapi/error.h"
28#include "hw/irq.h"
29#include "hw/southbridge/piix.h"
30#include "hw/pci/pci.h"
31#include "hw/isa/isa.h"
32#include "hw/sysbus.h"
33#include "hw/intc/i8259.h"
34#include "hw/dma/i8257.h"
35#include "hw/timer/i8254.h"
36#include "hw/rtc/mc146818rtc.h"
37#include "hw/ide/pci.h"
38#include "migration/vmstate.h"
39#include "sysemu/reset.h"
40#include "sysemu/runstate.h"
41#include "qom/object.h"
42
43PCIDevice *piix4_dev;
44
45struct PIIX4State {
46 PCIDevice dev;
47 qemu_irq cpu_intr;
48 qemu_irq *isa;
49
50 RTCState rtc;
51
52 MemoryRegion rcr_mem;
53 uint8_t rcr;
54};
55
56OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
57
58static void piix4_isa_reset(DeviceState *dev)
59{
60 PIIX4State *d = PIIX4_PCI_DEVICE(dev);
61 uint8_t *pci_conf = d->dev.config;
62
63 pci_conf[0x04] = 0x07;
64 pci_conf[0x05] = 0x00;
65 pci_conf[0x06] = 0x00;
66 pci_conf[0x07] = 0x02;
67 pci_conf[0x4c] = 0x4d;
68 pci_conf[0x4e] = 0x03;
69 pci_conf[0x4f] = 0x00;
70 pci_conf[0x60] = 0x0a;
71 pci_conf[0x61] = 0x0a;
72 pci_conf[0x62] = 0x0b;
73 pci_conf[0x63] = 0x0b;
74 pci_conf[0x69] = 0x02;
75 pci_conf[0x70] = 0x80;
76 pci_conf[0x76] = 0x0c;
77 pci_conf[0x77] = 0x0c;
78 pci_conf[0x78] = 0x02;
79 pci_conf[0x79] = 0x00;
80 pci_conf[0x80] = 0x00;
81 pci_conf[0x82] = 0x00;
82 pci_conf[0xa0] = 0x08;
83 pci_conf[0xa2] = 0x00;
84 pci_conf[0xa3] = 0x00;
85 pci_conf[0xa4] = 0x00;
86 pci_conf[0xa5] = 0x00;
87 pci_conf[0xa6] = 0x00;
88 pci_conf[0xa7] = 0x00;
89 pci_conf[0xa8] = 0x0f;
90 pci_conf[0xaa] = 0x00;
91 pci_conf[0xab] = 0x00;
92 pci_conf[0xac] = 0x00;
93 pci_conf[0xae] = 0x00;
94}
95
96static int piix4_ide_post_load(void *opaque, int version_id)
97{
98 PIIX4State *s = opaque;
99
100 if (version_id == 2) {
101 s->rcr = 0;
102 }
103
104 return 0;
105}
106
107static const VMStateDescription vmstate_piix4 = {
108 .name = "PIIX4",
109 .version_id = 3,
110 .minimum_version_id = 2,
111 .post_load = piix4_ide_post_load,
112 .fields = (VMStateField[]) {
113 VMSTATE_PCI_DEVICE(dev, PIIX4State),
114 VMSTATE_UINT8_V(rcr, PIIX4State, 3),
115 VMSTATE_END_OF_LIST()
116 }
117};
118
119static void piix4_request_i8259_irq(void *opaque, int irq, int level)
120{
121 PIIX4State *s = opaque;
122 qemu_set_irq(s->cpu_intr, level);
123}
124
125static void piix4_set_i8259_irq(void *opaque, int irq, int level)
126{
127 PIIX4State *s = opaque;
128 qemu_set_irq(s->isa[irq], level);
129}
130
131static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
132 unsigned int len)
133{
134 PIIX4State *s = opaque;
135
136 if (val & 4) {
137 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
138 return;
139 }
140
141 s->rcr = val & 2;
142}
143
144static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
145{
146 PIIX4State *s = opaque;
147
148 return s->rcr;
149}
150
151static const MemoryRegionOps piix4_rcr_ops = {
152 .read = piix4_rcr_read,
153 .write = piix4_rcr_write,
154 .endianness = DEVICE_LITTLE_ENDIAN,
155 .impl = {
156 .min_access_size = 1,
157 .max_access_size = 1,
158 },
159};
160
161static void piix4_realize(PCIDevice *dev, Error **errp)
162{
163 PIIX4State *s = PIIX4_PCI_DEVICE(dev);
164 ISABus *isa_bus;
165 qemu_irq *i8259_out_irq;
166
167 isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
168 pci_address_space_io(dev), errp);
169 if (!isa_bus) {
170 return;
171 }
172
173 qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
174 "isa", ISA_NUM_IRQS);
175 qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
176 "intr", 1);
177
178 memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
179 "reset-control", 1);
180 memory_region_add_subregion_overlap(pci_address_space_io(dev),
181 PIIX_RCR_IOPORT, &s->rcr_mem, 1);
182
183
184 i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
185 s->isa = i8259_init(isa_bus, *i8259_out_irq);
186
187
188 isa_bus_irqs(isa_bus, s->isa);
189
190
191 i8254_pit_init(isa_bus, 0x40, 0, NULL);
192
193
194 i8257_dma_init(isa_bus, 0);
195
196
197 qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
198 if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
199 return;
200 }
201 isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
202
203 piix4_dev = dev;
204}
205
206static void piix4_init(Object *obj)
207{
208 PIIX4State *s = PIIX4_PCI_DEVICE(obj);
209
210 object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC);
211}
212
213static void piix4_class_init(ObjectClass *klass, void *data)
214{
215 DeviceClass *dc = DEVICE_CLASS(klass);
216 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
217
218 k->realize = piix4_realize;
219 k->vendor_id = PCI_VENDOR_ID_INTEL;
220 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
221 k->class_id = PCI_CLASS_BRIDGE_ISA;
222 dc->reset = piix4_isa_reset;
223 dc->desc = "ISA bridge";
224 dc->vmsd = &vmstate_piix4;
225
226
227
228
229 dc->user_creatable = false;
230 dc->hotpluggable = false;
231}
232
233static const TypeInfo piix4_info = {
234 .name = TYPE_PIIX4_PCI_DEVICE,
235 .parent = TYPE_PCI_DEVICE,
236 .instance_size = sizeof(PIIX4State),
237 .instance_init = piix4_init,
238 .class_init = piix4_class_init,
239 .interfaces = (InterfaceInfo[]) {
240 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
241 { },
242 },
243};
244
245static void piix4_register_types(void)
246{
247 type_register_static(&piix4_info);
248}
249
250type_init(piix4_register_types)
251
252DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
253{
254 PCIDevice *pci;
255 DeviceState *dev;
256 int devfn = PCI_DEVFN(10, 0);
257
258 pci = pci_create_simple_multifunction(pci_bus, devfn, true,
259 TYPE_PIIX4_PCI_DEVICE);
260 dev = DEVICE(pci);
261 if (isa_bus) {
262 *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
263 }
264
265 pci = pci_create_simple(pci_bus, devfn + 1, "piix4-ide");
266 pci_ide_create_devs(pci);
267
268 pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci");
269 if (smbus) {
270 *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
271 isa_get_irq(NULL, 9), NULL, 0, NULL);
272 }
273
274 return dev;
275}
276
