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24
25#include "qemu/osdep.h"
26#include "qemu/units.h"
27#include "qemu/bitops.h"
28#include "qemu-common.h"
29#include "qemu/datadir.h"
30#include "cpu.h"
31#include "hw/clock.h"
32#include "hw/southbridge/piix.h"
33#include "hw/isa/superio.h"
34#include "hw/char/serial.h"
35#include "net/net.h"
36#include "hw/boards.h"
37#include "hw/i2c/smbus_eeprom.h"
38#include "hw/block/flash.h"
39#include "hw/mips/mips.h"
40#include "hw/mips/cpudevs.h"
41#include "hw/pci/pci.h"
42#include "sysemu/sysemu.h"
43#include "sysemu/arch_init.h"
44#include "qemu/log.h"
45#include "hw/mips/bios.h"
46#include "hw/ide.h"
47#include "hw/irq.h"
48#include "hw/loader.h"
49#include "elf.h"
50#include "exec/address-spaces.h"
51#include "qom/object.h"
52#include "hw/sysbus.h"
53#include "qemu/host-utils.h"
54#include "sysemu/qtest.h"
55#include "sysemu/reset.h"
56#include "sysemu/runstate.h"
57#include "qapi/error.h"
58#include "qemu/error-report.h"
59#include "hw/misc/empty_slot.h"
60#include "sysemu/kvm.h"
61#include "semihosting/semihost.h"
62#include "hw/mips/cps.h"
63#include "hw/qdev-clock.h"
64
65#define ENVP_PADDR 0x2000
66#define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
67#define ENVP_NB_ENTRIES 16
68#define ENVP_ENTRY_SIZE 256
69
70
71#define FLASH_ADDRESS 0x1e000000ULL
72#define FPGA_ADDRESS 0x1f000000ULL
73#define RESET_ADDRESS 0x1fc00000ULL
74
75#define FLASH_SIZE 0x400000
76
77#define MAX_IDE_BUS 2
78
79typedef struct {
80 MemoryRegion iomem;
81 MemoryRegion iomem_lo;
82 MemoryRegion iomem_hi;
83 uint32_t leds;
84 uint32_t brk;
85 uint32_t gpout;
86 uint32_t i2cin;
87 uint32_t i2coe;
88 uint32_t i2cout;
89 uint32_t i2csel;
90 CharBackend display;
91 char display_text[9];
92 SerialMM *uart;
93 bool display_inited;
94} MaltaFPGAState;
95
96#define TYPE_MIPS_MALTA "mips-malta"
97OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA)
98
99struct MaltaState {
100 SysBusDevice parent_obj;
101
102 Clock *cpuclk;
103 MIPSCPSState cps;
104 qemu_irq i8259[ISA_NUM_IRQS];
105};
106
107static struct _loaderparams {
108 int ram_size, ram_low_size;
109 const char *kernel_filename;
110 const char *kernel_cmdline;
111 const char *initrd_filename;
112} loaderparams;
113
114
115static void malta_fpga_update_display(void *opaque)
116{
117 char leds_text[9];
118 int i;
119 MaltaFPGAState *s = opaque;
120
121 for (i = 7 ; i >= 0 ; i--) {
122 if (s->leds & (1 << i)) {
123 leds_text[i] = '#';
124 } else {
125 leds_text[i] = ' ';
126 }
127 }
128 leds_text[8] = '\0';
129
130 qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
131 leds_text);
132 qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
133 s->display_text);
134}
135
136
137
138
139
140
141
142
143
144
145
146#if defined(DEBUG)
147# define logout(fmt, ...) \
148 fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
149#else
150# define logout(fmt, ...) ((void)0)
151#endif
152
153struct _eeprom24c0x_t {
154 uint8_t tick;
155 uint8_t address;
156 uint8_t command;
157 uint8_t ack;
158 uint8_t scl;
159 uint8_t sda;
160 uint8_t data;
161
162 uint8_t contents[256];
163};
164
165typedef struct _eeprom24c0x_t eeprom24c0x_t;
166
167static eeprom24c0x_t spd_eeprom = {
168 .contents = {
169
170 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
171
172 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
173
174 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
175
176 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
177
178 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
179
180 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
181
182 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
183
184 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
185
186 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
187
188 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
189
190 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
191
192 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
193
194 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
195
196 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
197
198 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
199
200 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
201 },
202};
203
204static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
205{
206 enum { SDR = 0x4, DDR2 = 0x8 } type;
207 uint8_t *spd = spd_eeprom.contents;
208 uint8_t nbanks = 0;
209 uint16_t density = 0;
210 int i;
211
212
213 ram_size /= MiB;
214
215 while ((ram_size >= 4) && (nbanks <= 2)) {
216 int sz_log2 = MIN(31 - clz32(ram_size), 14);
217 nbanks++;
218 density |= 1 << (sz_log2 - 2);
219 ram_size -= 1 << sz_log2;
220 }
221
222
223 if ((nbanks == 1) && (density > 1)) {
224 nbanks++;
225 density >>= 1;
226 }
227
228 if (density & 0xff00) {
229 density = (density & 0xe0) | ((density >> 8) & 0x1f);
230 type = DDR2;
231 } else if (!(density & 0x1f)) {
232 type = DDR2;
233 } else {
234 type = SDR;
235 }
236
237 if (ram_size) {
238 warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB"
239 " of SDRAM", ram_size);
240 }
241
242
243 spd[2] = type;
244 spd[5] = nbanks;
245 spd[31] = density;
246
247
248 spd[63] = 0;
249 for (i = 0; i < 63; i++) {
250 spd[63] += spd[i];
251 }
252
253
254 memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
255}
256
257static void generate_eeprom_serial(uint8_t *eeprom)
258{
259 int i, pos = 0;
260 uint8_t mac[6] = { 0x00 };
261 uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
262
263
264 eeprom[pos++] = 0x01;
265
266
267 eeprom[pos++] = 0x02;
268
269
270 eeprom[pos++] = 0x01;
271 eeprom[pos++] = 0x06;
272 memcpy(&eeprom[pos], mac, sizeof(mac));
273 pos += sizeof(mac);
274
275
276 eeprom[pos++] = 0x02;
277 eeprom[pos++] = 0x05;
278 memcpy(&eeprom[pos], sn, sizeof(sn));
279 pos += sizeof(sn);
280
281
282 eeprom[pos] = 0;
283 for (i = 0; i < pos; i++) {
284 eeprom[pos] += eeprom[i];
285 }
286}
287
288static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom)
289{
290 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
291 eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data);
292 return eeprom->sda;
293}
294
295static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda)
296{
297 if (eeprom->scl && scl && (eeprom->sda != sda)) {
298 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
299 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda,
300 sda ? "stop" : "start");
301 if (!sda) {
302 eeprom->tick = 1;
303 eeprom->command = 0;
304 }
305 } else if (eeprom->tick == 0 && !eeprom->ack) {
306
307 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
308 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
309 } else if (!eeprom->scl && scl) {
310 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
311 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
312 if (eeprom->ack) {
313 logout("\ti2c ack bit = 0\n");
314 sda = 0;
315 eeprom->ack = 0;
316 } else if (eeprom->sda == sda) {
317 uint8_t bit = (sda != 0);
318 logout("\ti2c bit = %d\n", bit);
319 if (eeprom->tick < 9) {
320 eeprom->command <<= 1;
321 eeprom->command += bit;
322 eeprom->tick++;
323 if (eeprom->tick == 9) {
324 logout("\tcommand 0x%04x, %s\n", eeprom->command,
325 bit ? "read" : "write");
326 eeprom->ack = 1;
327 }
328 } else if (eeprom->tick < 17) {
329 if (eeprom->command & 1) {
330 sda = ((eeprom->data & 0x80) != 0);
331 }
332 eeprom->address <<= 1;
333 eeprom->address += bit;
334 eeprom->tick++;
335 eeprom->data <<= 1;
336 if (eeprom->tick == 17) {
337 eeprom->data = eeprom->contents[eeprom->address];
338 logout("\taddress 0x%04x, data 0x%02x\n",
339 eeprom->address, eeprom->data);
340 eeprom->ack = 1;
341 eeprom->tick = 0;
342 }
343 } else if (eeprom->tick >= 17) {
344 sda = 0;
345 }
346 } else {
347 logout("\tsda changed with raising scl\n");
348 }
349 } else {
350 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl,
351 scl, eeprom->sda, sda);
352 }
353 eeprom->scl = scl;
354 eeprom->sda = sda;
355}
356
357static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
358 unsigned size)
359{
360 MaltaFPGAState *s = opaque;
361 uint32_t val = 0;
362 uint32_t saddr;
363
364 saddr = (addr & 0xfffff);
365
366 switch (saddr) {
367
368
369 case 0x00200:
370 val = 0x00000000;
371 break;
372
373
374 case 0x00208:
375#ifdef TARGET_WORDS_BIGENDIAN
376 val = 0x00000012;
377#else
378 val = 0x00000010;
379#endif
380 break;
381
382
383 case 0x00210:
384 val = 0x00;
385 break;
386
387
388 case 0x00408:
389 val = s->leds;
390 break;
391
392
393 case 0x00508:
394 val = s->brk;
395 break;
396
397
398
399
400 case 0x00a00:
401 val = s->gpout;
402 break;
403
404
405
406
407 case 0x00a08:
408
409 if (s->i2csel) {
410 val = s->i2cout;
411 } else {
412 val = 0x00;
413 }
414 break;
415
416
417 case 0x00b00:
418 val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom));
419 break;
420
421
422 case 0x00b08:
423 val = s->i2coe;
424 break;
425
426
427 case 0x00b10:
428 val = s->i2cout;
429 break;
430
431
432 case 0x00b18:
433 val = s->i2csel;
434 break;
435
436 default:
437 qemu_log_mask(LOG_GUEST_ERROR,
438 "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n",
439 addr);
440 break;
441 }
442 return val;
443}
444
445static void malta_fpga_write(void *opaque, hwaddr addr,
446 uint64_t val, unsigned size)
447{
448 MaltaFPGAState *s = opaque;
449 uint32_t saddr;
450
451 saddr = (addr & 0xfffff);
452
453 switch (saddr) {
454
455
456 case 0x00200:
457 break;
458
459
460 case 0x00210:
461 break;
462
463
464 case 0x00408:
465 s->leds = val & 0xff;
466 malta_fpga_update_display(s);
467 break;
468
469
470 case 0x00410:
471 snprintf(s->display_text, 9, "%08X", (uint32_t)val);
472 malta_fpga_update_display(s);
473 break;
474
475
476 case 0x00418:
477 case 0x00420:
478 case 0x00428:
479 case 0x00430:
480 case 0x00438:
481 case 0x00440:
482 case 0x00448:
483 case 0x00450:
484 s->display_text[(saddr - 0x00418) >> 3] = (char) val;
485 malta_fpga_update_display(s);
486 break;
487
488
489 case 0x00500:
490 if (val == 0x42) {
491 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
492 }
493 break;
494
495
496 case 0x00508:
497 s->brk = val & 0xff;
498 break;
499
500
501
502
503 case 0x00a00:
504 s->gpout = val & 0xff;
505 break;
506
507
508 case 0x00b08:
509 s->i2coe = val & 0x03;
510 break;
511
512
513 case 0x00b10:
514 eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01);
515 s->i2cout = val;
516 break;
517
518
519 case 0x00b18:
520 s->i2csel = val & 0x01;
521 break;
522
523 default:
524 qemu_log_mask(LOG_GUEST_ERROR,
525 "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n",
526 addr);
527 break;
528 }
529}
530
531static const MemoryRegionOps malta_fpga_ops = {
532 .read = malta_fpga_read,
533 .write = malta_fpga_write,
534 .endianness = DEVICE_NATIVE_ENDIAN,
535};
536
537static void malta_fpga_reset(void *opaque)
538{
539 MaltaFPGAState *s = opaque;
540
541 s->leds = 0x00;
542 s->brk = 0x0a;
543 s->gpout = 0x00;
544 s->i2cin = 0x3;
545 s->i2coe = 0x0;
546 s->i2cout = 0x3;
547 s->i2csel = 0x1;
548
549 s->display_text[8] = '\0';
550 snprintf(s->display_text, 9, " ");
551}
552
553static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event)
554{
555 MaltaFPGAState *s = opaque;
556
557 if (event == CHR_EVENT_OPENED && !s->display_inited) {
558 qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n");
559 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
560 qemu_chr_fe_printf(&s->display, "+ +\r\n");
561 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
562 qemu_chr_fe_printf(&s->display, "\n");
563 qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n");
564 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
565 qemu_chr_fe_printf(&s->display, "+ +\r\n");
566 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
567 s->display_inited = true;
568 }
569}
570
571static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
572 hwaddr base, qemu_irq uart_irq, Chardev *uart_chr)
573{
574 MaltaFPGAState *s;
575 Chardev *chr;
576
577 s = g_new0(MaltaFPGAState, 1);
578
579 memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s,
580 "malta-fpga", 0x100000);
581 memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
582 &s->iomem, 0, 0x900);
583 memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
584 &s->iomem, 0xa00, 0x100000 - 0xa00);
585
586 memory_region_add_subregion(address_space, base, &s->iomem_lo);
587 memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
588
589 chr = qemu_chr_new("fpga", "vc:320x200", NULL);
590 qemu_chr_fe_init(&s->display, chr, NULL);
591 qemu_chr_fe_set_handlers(&s->display, NULL, NULL,
592 malta_fgpa_display_event, NULL, s, NULL, true);
593
594 s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq,
595 230400, uart_chr, DEVICE_NATIVE_ENDIAN);
596
597 malta_fpga_reset(s);
598 qemu_register_reset(malta_fpga_reset, s);
599
600 return s;
601}
602
603
604static void network_init(PCIBus *pci_bus)
605{
606 int i;
607
608 for (i = 0; i < nb_nics; i++) {
609 NICInfo *nd = &nd_table[i];
610 const char *default_devaddr = NULL;
611
612 if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0))
613
614 default_devaddr = "0b";
615
616 pci_nic_init_nofail(nd, pci_bus, "pcnet", default_devaddr);
617 }
618}
619
620static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
621 uint64_t kernel_entry)
622{
623 uint16_t *p;
624
625
626 p = (uint16_t *)base;
627
628#define NM_HI1(VAL) (((VAL) >> 16) & 0x1f)
629#define NM_HI2(VAL) \
630 (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
631#define NM_LO(VAL) ((VAL) & 0xfff)
632
633 stw_p(p++, 0x2800); stw_p(p++, 0x001c);
634
635 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
636
637 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
638
639 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
640
641 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
642
643 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
644
645 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
646
647 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
648
649
650
651 if (semihosting_get_argc()) {
652
653 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
654
655 } else {
656 stw_p(p++, 0x0080); stw_p(p++, 0x0002);
657
658 }
659
660 stw_p(p++, 0xe3a0 | NM_HI1(ENVP_VADDR - 64));
661
662 stw_p(p++, NM_HI2(ENVP_VADDR - 64));
663
664
665 stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_VADDR - 64));
666
667
668 stw_p(p++, 0xe0a0 | NM_HI1(ENVP_VADDR));
669
670 stw_p(p++, NM_HI2(ENVP_VADDR));
671
672
673 stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_VADDR));
674
675
676 stw_p(p++, 0xe0c0 | NM_HI1(ENVP_VADDR + 8));
677
678 stw_p(p++, NM_HI2(ENVP_VADDR + 8));
679
680
681 stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_VADDR + 8));
682
683
684 stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size));
685
686 stw_p(p++, NM_HI2(loaderparams.ram_low_size));
687
688
689 stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
690
691
692
693
694
695
696
697
698
699
700 stw_p(p++, 0xe040); stw_p(p++, 0x0681);
701
702
703#ifdef TARGET_WORDS_BIGENDIAN
704
705 stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
706
707
708
709 stw_p(p++, 0x8422); stw_p(p++, 0x9068);
710
711
712 stw_p(p++, 0xe040); stw_p(p++, 0x077d);
713
714
715 stw_p(p++, 0xe020); stw_p(p++, 0x0801);
716
717
718
719 stw_p(p++, 0x8422); stw_p(p++, 0x9048);
720
721
722 stw_p(p++, 0xe020); stw_p(p++, 0x0800);
723
724
725
726 stw_p(p++, 0x8422); stw_p(p++, 0x9050);
727
728
729 stw_p(p++, 0xe020); stw_p(p++, 0x0001);
730
731
732
733 stw_p(p++, 0x8422); stw_p(p++, 0x9058);
734
735
736 stw_p(p++, 0xe020); stw_p(p++, 0x07e0);
737
738
739
740 stw_p(p++, 0x8422); stw_p(p++, 0x9060);
741
742
743 stw_p(p++, 0xe020); stw_p(p++, 0x0821);
744
745
746
747 stw_p(p++, 0x8422); stw_p(p++, 0x9080);
748
749
750 stw_p(p++, 0xe020); stw_p(p++, 0x0bc0);
751
752
753#else
754
755 stw_p(p++, 0x0020); stw_p(p++, 0x00df);
756
757
758
759 stw_p(p++, 0x8422); stw_p(p++, 0x9068);
760
761
762
763 stw_p(p++, 0xe040); stw_p(p++, 0x077d);
764
765
766 stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
767
768
769
770 stw_p(p++, 0x8422); stw_p(p++, 0x9048);
771
772
773 stw_p(p++, 0x0020); stw_p(p++, 0x0040);
774
775
776
777 stw_p(p++, 0x8422); stw_p(p++, 0x9050);
778
779
780 stw_p(p++, 0x0020); stw_p(p++, 0x0080);
781
782
783
784 stw_p(p++, 0x8422); stw_p(p++, 0x9058);
785
786
787 stw_p(p++, 0x0020); stw_p(p++, 0x003f);
788
789
790
791 stw_p(p++, 0x8422); stw_p(p++, 0x9060);
792
793
794 stw_p(p++, 0x0020); stw_p(p++, 0x00c1);
795
796
797
798 stw_p(p++, 0x8422); stw_p(p++, 0x9080);
799
800
801 stw_p(p++, 0x0020); stw_p(p++, 0x005e);
802
803
804#endif
805
806
807 stw_p(p++, 0x8422); stw_p(p++, 0x9088);
808
809
810 stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
811
812 stw_p(p++, NM_HI2(kernel_entry));
813
814
815 stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry));
816
817
818 stw_p(p++, 0x4bf9); stw_p(p++, 0x0000);
819
820}
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844static void write_bootloader(uint8_t *base, uint64_t run_addr,
845 uint64_t kernel_entry)
846{
847 uint32_t *p;
848
849
850 p = (uint32_t *)base;
851
852 stl_p(p++, 0x08000000 |
853 ((run_addr + 0x580) & 0x0fffffff) >> 2);
854 stl_p(p++, 0x00000000);
855
856
857 stl_p(base + 0x500, run_addr + 0x0580);
858 stl_p(base + 0x504, run_addr + 0x083c);
859 stl_p(base + 0x520, run_addr + 0x0580);
860 stl_p(base + 0x52c, run_addr + 0x0800);
861 stl_p(base + 0x534, run_addr + 0x0808);
862 stl_p(base + 0x538, run_addr + 0x0800);
863 stl_p(base + 0x53c, run_addr + 0x0800);
864 stl_p(base + 0x540, run_addr + 0x0800);
865 stl_p(base + 0x544, run_addr + 0x0800);
866 stl_p(base + 0x548, run_addr + 0x0800);
867 stl_p(base + 0x54c, run_addr + 0x0800);
868 stl_p(base + 0x550, run_addr + 0x0800);
869 stl_p(base + 0x554, run_addr + 0x0800);
870
871
872
873 p = (uint32_t *) (base + 0x580);
874
875 if (semihosting_get_argc()) {
876
877 stl_p(p++, 0x00000000);
878 } else {
879 stl_p(p++, 0x24040002);
880 }
881
882
883 stl_p(p++, 0x3c1d0000 | (((ENVP_VADDR - 64) >> 16) & 0xffff));
884
885 stl_p(p++, 0x37bd0000 | ((ENVP_VADDR - 64) & 0xffff));
886
887 stl_p(p++, 0x3c050000 | ((ENVP_VADDR >> 16) & 0xffff));
888
889 stl_p(p++, 0x34a50000 | (ENVP_VADDR & 0xffff));
890
891 stl_p(p++, 0x3c060000 | (((ENVP_VADDR + 8) >> 16) & 0xffff));
892
893 stl_p(p++, 0x34c60000 | ((ENVP_VADDR + 8) & 0xffff));
894
895 stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
896
897 stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff));
898
899
900 stl_p(p++, 0x3c09b400);
901
902#ifdef TARGET_WORDS_BIGENDIAN
903 stl_p(p++, 0x3c08df00);
904#else
905 stl_p(p++, 0x340800df);
906#endif
907 stl_p(p++, 0xad280068);
908
909 stl_p(p++, 0x3c09bbe0);
910
911#ifdef TARGET_WORDS_BIGENDIAN
912 stl_p(p++, 0x3c08c000);
913#else
914 stl_p(p++, 0x340800c0);
915#endif
916 stl_p(p++, 0xad280048);
917#ifdef TARGET_WORDS_BIGENDIAN
918 stl_p(p++, 0x3c084000);
919#else
920 stl_p(p++, 0x34080040);
921#endif
922 stl_p(p++, 0xad280050);
923
924#ifdef TARGET_WORDS_BIGENDIAN
925 stl_p(p++, 0x3c088000);
926#else
927 stl_p(p++, 0x34080080);
928#endif
929 stl_p(p++, 0xad280058);
930#ifdef TARGET_WORDS_BIGENDIAN
931 stl_p(p++, 0x3c083f00);
932#else
933 stl_p(p++, 0x3408003f);
934#endif
935 stl_p(p++, 0xad280060);
936
937#ifdef TARGET_WORDS_BIGENDIAN
938 stl_p(p++, 0x3c08c100);
939#else
940 stl_p(p++, 0x340800c1);
941#endif
942 stl_p(p++, 0xad280080);
943#ifdef TARGET_WORDS_BIGENDIAN
944 stl_p(p++, 0x3c085e00);
945#else
946 stl_p(p++, 0x3408005e);
947#endif
948 stl_p(p++, 0xad280088);
949
950
951 stl_p(p++, 0x3c1f0000 |
952 ((kernel_entry >> 16) & 0xffff));
953 stl_p(p++, 0x37ff0000 |
954 (kernel_entry & 0xffff));
955 stl_p(p++, 0x03e00009);
956 stl_p(p++, 0x00000000);
957
958
959 p = (uint32_t *) (base + 0x800);
960 stl_p(p++, 0x03e00009);
961 stl_p(p++, 0x24020000);
962
963 stl_p(p++, 0x03e06821);
964 stl_p(p++, 0x00805821);
965 stl_p(p++, 0x00a05021);
966 stl_p(p++, 0x91440000);
967 stl_p(p++, 0x254a0001);
968 stl_p(p++, 0x10800005);
969 stl_p(p++, 0x00000000);
970 stl_p(p++, 0x0ff0021c);
971 stl_p(p++, 0x00000000);
972 stl_p(p++, 0x1000fff9);
973 stl_p(p++, 0x00000000);
974 stl_p(p++, 0x01a00009);
975 stl_p(p++, 0x01602021);
976
977 stl_p(p++, 0x03e06821);
978 stl_p(p++, 0x00805821);
979 stl_p(p++, 0x00a05021);
980 stl_p(p++, 0x00c06021);
981 stl_p(p++, 0x91440000);
982 stl_p(p++, 0x0ff0021c);
983 stl_p(p++, 0x00000000);
984 stl_p(p++, 0x254a0001);
985 stl_p(p++, 0x258cffff);
986 stl_p(p++, 0x1580fffa);
987 stl_p(p++, 0x00000000);
988 stl_p(p++, 0x01a00009);
989 stl_p(p++, 0x01602021);
990
991 stl_p(p++, 0x3c08b800);
992 stl_p(p++, 0x350803f8);
993 stl_p(p++, 0x91090005);
994 stl_p(p++, 0x00000000);
995 stl_p(p++, 0x31290040);
996 stl_p(p++, 0x1120fffc);
997 stl_p(p++, 0x00000000);
998 stl_p(p++, 0x03e00009);
999 stl_p(p++, 0xa1040000);
1000
1001}
1002
1003static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index,
1004 const char *string, ...)
1005{
1006 va_list ap;
1007 uint32_t table_addr;
1008
1009 if (index >= ENVP_NB_ENTRIES) {
1010 return;
1011 }
1012
1013 if (string == NULL) {
1014 prom_buf[index] = 0;
1015 return;
1016 }
1017
1018 table_addr = sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
1019 prom_buf[index] = tswap32(ENVP_VADDR + table_addr);
1020
1021 va_start(ap, string);
1022 vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
1023 va_end(ap);
1024}
1025
1026
1027static uint64_t load_kernel(void)
1028{
1029 uint64_t kernel_entry, kernel_high, initrd_size;
1030 long kernel_size;
1031 ram_addr_t initrd_offset;
1032 int big_endian;
1033 uint32_t *prom_buf;
1034 long prom_size;
1035 int prom_index = 0;
1036 uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr);
1037
1038#ifdef TARGET_WORDS_BIGENDIAN
1039 big_endian = 1;
1040#else
1041 big_endian = 0;
1042#endif
1043
1044 kernel_size = load_elf(loaderparams.kernel_filename, NULL,
1045 cpu_mips_kseg0_to_phys, NULL,
1046 &kernel_entry, NULL,
1047 &kernel_high, NULL, big_endian, EM_MIPS,
1048 1, 0);
1049 if (kernel_size < 0) {
1050 error_report("could not load kernel '%s': %s",
1051 loaderparams.kernel_filename,
1052 load_elf_strerror(kernel_size));
1053 exit(1);
1054 }
1055
1056
1057 if (kernel_entry & 0x80000000ll) {
1058 if (kvm_enabled()) {
1059 error_report("KVM guest kernels must be linked in useg. "
1060 "Did you forget to enable CONFIG_KVM_GUEST?");
1061 exit(1);
1062 }
1063
1064 xlate_to_kseg0 = cpu_mips_phys_to_kseg0;
1065 } else {
1066
1067 mips_um_ksegs_enable();
1068
1069 xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0;
1070 }
1071
1072
1073 initrd_size = 0;
1074 initrd_offset = 0;
1075 if (loaderparams.initrd_filename) {
1076 initrd_size = get_image_size(loaderparams.initrd_filename);
1077 if (initrd_size > 0) {
1078
1079
1080
1081
1082
1083 initrd_offset = ROUND_UP(loaderparams.ram_low_size
1084 - (initrd_size + 128 * KiB),
1085 INITRD_PAGE_SIZE);
1086 if (kernel_high >= initrd_offset) {
1087 error_report("memory too small for initial ram disk '%s'",
1088 loaderparams.initrd_filename);
1089 exit(1);
1090 }
1091 initrd_size = load_image_targphys(loaderparams.initrd_filename,
1092 initrd_offset,
1093 loaderparams.ram_size - initrd_offset);
1094 }
1095 if (initrd_size == (target_ulong) -1) {
1096 error_report("could not load initial ram disk '%s'",
1097 loaderparams.initrd_filename);
1098 exit(1);
1099 }
1100 }
1101
1102
1103 prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
1104 prom_buf = g_malloc(prom_size);
1105
1106 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
1107 if (initrd_size > 0) {
1108 prom_set(prom_buf, prom_index++,
1109 "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
1110 xlate_to_kseg0(NULL, initrd_offset),
1111 initrd_size, loaderparams.kernel_cmdline);
1112 } else {
1113 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
1114 }
1115
1116 prom_set(prom_buf, prom_index++, "memsize");
1117 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size);
1118
1119 prom_set(prom_buf, prom_index++, "ememsize");
1120 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size);
1121
1122 prom_set(prom_buf, prom_index++, "modetty0");
1123 prom_set(prom_buf, prom_index++, "38400n8r");
1124 prom_set(prom_buf, prom_index++, NULL);
1125
1126 rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR);
1127
1128 g_free(prom_buf);
1129 return kernel_entry;
1130}
1131
1132static void malta_mips_config(MIPSCPU *cpu)
1133{
1134 MachineState *ms = MACHINE(qdev_get_machine());
1135 unsigned int smp_cpus = ms->smp.cpus;
1136 CPUMIPSState *env = &cpu->env;
1137 CPUState *cs = CPU(cpu);
1138
1139 if (ase_mt_available(env)) {
1140 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
1141 CP0MVPC0_PTC, 8,
1142 smp_cpus * cs->nr_threads - 1);
1143 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
1144 CP0MVPC0_PVPE, 4, smp_cpus - 1);
1145 }
1146}
1147
1148static void main_cpu_reset(void *opaque)
1149{
1150 MIPSCPU *cpu = opaque;
1151 CPUMIPSState *env = &cpu->env;
1152
1153 cpu_reset(CPU(cpu));
1154
1155
1156
1157
1158
1159
1160 if (loaderparams.kernel_filename) {
1161 env->CP0_Status &= ~(1 << CP0St_ERL);
1162 }
1163
1164 malta_mips_config(cpu);
1165
1166 if (kvm_enabled()) {
1167
1168 env->active_tc.PC = 0x40000000 + loaderparams.ram_low_size;
1169 }
1170}
1171
1172static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
1173 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
1174{
1175 CPUMIPSState *env;
1176 MIPSCPU *cpu;
1177 int i;
1178
1179 for (i = 0; i < ms->smp.cpus; i++) {
1180 cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk);
1181
1182
1183 cpu_mips_irq_init_cpu(cpu);
1184 cpu_mips_clock_init(cpu);
1185 qemu_register_reset(main_cpu_reset, cpu);
1186 }
1187
1188 cpu = MIPS_CPU(first_cpu);
1189 env = &cpu->env;
1190 *i8259_irq = env->irq[2];
1191 *cbus_irq = env->irq[4];
1192}
1193
1194static void create_cps(MachineState *ms, MaltaState *s,
1195 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
1196{
1197 object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS);
1198 object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type,
1199 &error_fatal);
1200 object_property_set_int(OBJECT(&s->cps), "num-vp", ms->smp.cpus,
1201 &error_fatal);
1202 qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk);
1203 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
1204
1205 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
1206
1207 *i8259_irq = get_cps_irq(&s->cps, 3);
1208 *cbus_irq = NULL;
1209}
1210
1211static void mips_create_cpu(MachineState *ms, MaltaState *s,
1212 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
1213{
1214 if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) {
1215 create_cps(ms, s, cbus_irq, i8259_irq);
1216 } else {
1217 create_cpu_without_cps(ms, s, cbus_irq, i8259_irq);
1218 }
1219}
1220
1221static
1222void mips_malta_init(MachineState *machine)
1223{
1224 ram_addr_t ram_size = machine->ram_size;
1225 ram_addr_t ram_low_size;
1226 const char *kernel_filename = machine->kernel_filename;
1227 const char *kernel_cmdline = machine->kernel_cmdline;
1228 const char *initrd_filename = machine->initrd_filename;
1229 char *filename;
1230 PFlashCFI01 *fl;
1231 MemoryRegion *system_memory = get_system_memory();
1232 MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1);
1233 MemoryRegion *ram_low_postio;
1234 MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1);
1235 const size_t smbus_eeprom_size = 8 * 256;
1236 uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
1237 uint64_t kernel_entry, bootloader_run_addr;
1238 PCIBus *pci_bus;
1239 ISABus *isa_bus;
1240 qemu_irq cbus_irq, i8259_irq;
1241 I2CBus *smbus;
1242 DriveInfo *dinfo;
1243 int fl_idx = 0;
1244 int be;
1245 MaltaState *s;
1246 DeviceState *dev;
1247
1248 s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA));
1249 sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal);
1250
1251
1252 mips_create_cpu(machine, s, &cbus_irq, &i8259_irq);
1253
1254
1255 if (ram_size > 2 * GiB) {
1256 error_report("Too much memory for this machine: %" PRId64 "MB,"
1257 " maximum 2048MB", ram_size / MiB);
1258 exit(1);
1259 }
1260
1261
1262 memory_region_add_subregion(system_memory, 0x80000000, machine->ram);
1263
1264
1265 memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram",
1266 machine->ram, 0, MIN(ram_size, 256 * MiB));
1267 memory_region_add_subregion(system_memory, 0, ram_low_preio);
1268
1269
1270 if (ram_size > 512 * MiB) {
1271 ram_low_postio = g_new(MemoryRegion, 1);
1272 memory_region_init_alias(ram_low_postio, NULL,
1273 "mips_malta_low_postio.ram",
1274 machine->ram, 512 * MiB,
1275 ram_size - 512 * MiB);
1276 memory_region_add_subregion(system_memory, 512 * MiB,
1277 ram_low_postio);
1278 }
1279
1280#ifdef TARGET_WORDS_BIGENDIAN
1281 be = 1;
1282#else
1283 be = 0;
1284#endif
1285
1286
1287
1288
1289 malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2));
1290
1291
1292 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
1293 fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios",
1294 FLASH_SIZE,
1295 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
1296 65536,
1297 4, 0x0000, 0x0000, 0x0000, 0x0000, be);
1298 bios = pflash_cfi01_get_memory(fl);
1299 fl_idx++;
1300 if (kernel_filename) {
1301 ram_low_size = MIN(ram_size, 256 * MiB);
1302
1303 if (kvm_enabled()) {
1304 ram_low_size -= 0x100000;
1305 bootloader_run_addr = cpu_mips_kvm_um_phys_to_kseg0(NULL, ram_low_size);
1306 } else {
1307 bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS);
1308 }
1309
1310
1311 loaderparams.ram_size = ram_size;
1312 loaderparams.ram_low_size = ram_low_size;
1313 loaderparams.kernel_filename = kernel_filename;
1314 loaderparams.kernel_cmdline = kernel_cmdline;
1315 loaderparams.initrd_filename = initrd_filename;
1316 kernel_entry = load_kernel();
1317
1318 if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) {
1319 write_bootloader(memory_region_get_ram_ptr(bios),
1320 bootloader_run_addr, kernel_entry);
1321 } else {
1322 write_bootloader_nanomips(memory_region_get_ram_ptr(bios),
1323 bootloader_run_addr, kernel_entry);
1324 }
1325 if (kvm_enabled()) {
1326
1327 write_bootloader(memory_region_get_ram_ptr(ram_low_preio) +
1328 ram_low_size,
1329 bootloader_run_addr, kernel_entry);
1330 }
1331 } else {
1332 target_long bios_size = FLASH_SIZE;
1333
1334 if (kvm_enabled()) {
1335 error_report("KVM enabled but no -kernel argument was specified. "
1336 "Booting from flash is not supported with KVM.");
1337 exit(1);
1338 }
1339
1340 if (!dinfo) {
1341
1342 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
1343 machine->firmware ?: BIOS_FILENAME);
1344 if (filename) {
1345 bios_size = load_image_targphys(filename, FLASH_ADDRESS,
1346 BIOS_SIZE);
1347 g_free(filename);
1348 } else {
1349 bios_size = -1;
1350 }
1351 if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
1352 machine->firmware && !qtest_enabled()) {
1353 error_report("Could not load MIPS bios '%s'", machine->firmware);
1354 exit(1);
1355 }
1356 }
1357
1358
1359
1360
1361#ifndef TARGET_WORDS_BIGENDIAN
1362 {
1363 uint32_t *end, *addr;
1364 const size_t swapsize = MIN(bios_size, 0x3e0000);
1365 addr = rom_ptr(FLASH_ADDRESS, swapsize);
1366 if (!addr) {
1367 addr = memory_region_get_ram_ptr(bios);
1368 }
1369 end = (void *)addr + swapsize;
1370 while (addr < end) {
1371 bswap32s(addr);
1372 addr++;
1373 }
1374 }
1375#endif
1376 }
1377
1378
1379
1380
1381
1382
1383
1384 memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE,
1385 &error_fatal);
1386 if (!rom_copy(memory_region_get_ram_ptr(bios_copy),
1387 FLASH_ADDRESS, BIOS_SIZE)) {
1388 memcpy(memory_region_get_ram_ptr(bios_copy),
1389 memory_region_get_ram_ptr(bios), BIOS_SIZE);
1390 }
1391 memory_region_set_readonly(bios_copy, true);
1392 memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy);
1393
1394
1395 stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
1396
1397
1398 pci_bus = gt64120_register(s->i8259);
1399
1400
1401
1402
1403
1404 empty_slot_init("GT64120", 0, 0x20000000);
1405
1406
1407 dev = piix4_create(pci_bus, &isa_bus, &smbus);
1408
1409
1410 qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
1411 for (int i = 0; i < ISA_NUM_IRQS; i++) {
1412 s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
1413 }
1414
1415
1416 generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
1417 generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
1418 smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size);
1419 g_free(smbus_eeprom_buf);
1420
1421
1422 isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO);
1423
1424
1425 network_init(pci_bus);
1426
1427
1428 pci_vga_init(pci_bus);
1429}
1430
1431static void mips_malta_instance_init(Object *obj)
1432{
1433 MaltaState *s = MIPS_MALTA(obj);
1434
1435 s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk");
1436 clock_set_hz(s->cpuclk, 320000000);
1437}
1438
1439static const TypeInfo mips_malta_device = {
1440 .name = TYPE_MIPS_MALTA,
1441 .parent = TYPE_SYS_BUS_DEVICE,
1442 .instance_size = sizeof(MaltaState),
1443 .instance_init = mips_malta_instance_init,
1444};
1445
1446static void mips_malta_machine_init(MachineClass *mc)
1447{
1448 mc->desc = "MIPS Malta Core LV";
1449 mc->init = mips_malta_init;
1450 mc->block_default_type = IF_IDE;
1451 mc->max_cpus = 16;
1452 mc->is_default = true;
1453#ifdef TARGET_MIPS64
1454 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc");
1455#else
1456 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
1457#endif
1458 mc->default_ram_id = "mips_malta.ram";
1459}
1460
1461DEFINE_MACHINE("malta", mips_malta_machine_init)
1462
1463static void mips_malta_register_types(void)
1464{
1465 type_register_static(&mips_malta_device);
1466}
1467
1468type_init(mips_malta_register_types)
1469