LXR qemu/hw/mips/mipssim.c

   1/*
   2 * QEMU/mipssim emulation
   3 *
   4 * Emulates a very simple machine model similar to the one used by the
   5 * proprietary MIPS emulator.
   6 *
   7 * Copyright (c) 2007 Thiemo Seufer
   8 *
   9 * Permission is hereby granted, free of charge, to any person obtaining a copy
  10 * of this software and associated documentation files (the "Software"), to deal
  11 * in the Software without restriction, including without limitation the rights
  12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13 * copies of the Software, and to permit persons to whom the Software is
  14 * furnished to do so, subject to the following conditions:
  15 *
  16 * The above copyright notice and this permission notice shall be included in
  17 * all copies or substantial portions of the Software.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25 * THE SOFTWARE.
  26 */
  27
  28#include "qemu/osdep.h"
  29#include "qapi/error.h"
  30#include "qemu-common.h"
  31#include "qemu/datadir.h"
  32#include "cpu.h"
  33#include "hw/clock.h"
  34#include "hw/mips/mips.h"
  35#include "hw/mips/cpudevs.h"
  36#include "hw/char/serial.h"
  37#include "hw/isa/isa.h"
  38#include "net/net.h"
  39#include "sysemu/sysemu.h"
  40#include "hw/boards.h"
  41#include "hw/mips/bios.h"
  42#include "hw/loader.h"
  43#include "elf.h"
  44#include "hw/sysbus.h"
  45#include "hw/qdev-properties.h"
  46#include "exec/address-spaces.h"
  47#include "qemu/error-report.h"
  48#include "sysemu/qtest.h"
  49#include "sysemu/reset.h"
  50
  51static struct _loaderparams {
  52    int ram_size;
  53    const char *kernel_filename;
  54    const char *kernel_cmdline;
  55    const char *initrd_filename;
  56} loaderparams;
  57
  58typedef struct ResetData {
  59    MIPSCPU *cpu;
  60    uint64_t vector;
  61} ResetData;
  62
  63static uint64_t load_kernel(void)
  64{
  65    uint64_t entry, kernel_high, initrd_size;
  66    long kernel_size;
  67    ram_addr_t initrd_offset;
  68    int big_endian;
  69
  70#ifdef TARGET_WORDS_BIGENDIAN
  71    big_endian = 1;
  72#else
  73    big_endian = 0;
  74#endif
  75
  76    kernel_size = load_elf(loaderparams.kernel_filename, NULL,
  77                           cpu_mips_kseg0_to_phys, NULL,
  78                           &entry, NULL,
  79                           &kernel_high, NULL, big_endian,
  80                           EM_MIPS, 1, 0);
  81    if (kernel_size < 0) {
  82        error_report("could not load kernel '%s': %s",
  83                     loaderparams.kernel_filename,
  84                     load_elf_strerror(kernel_size));
  85        exit(1);
  86    }
  87
  88    /* load initrd */
  89    initrd_size = 0;
  90    initrd_offset = 0;
  91    if (loaderparams.initrd_filename) {
  92        initrd_size = get_image_size(loaderparams.initrd_filename);
  93        if (initrd_size > 0) {
  94            initrd_offset = ROUND_UP(kernel_high, INITRD_PAGE_SIZE);
  95            if (initrd_offset + initrd_size > loaderparams.ram_size) {
  96                error_report("memory too small for initial ram disk '%s'",
  97                             loaderparams.initrd_filename);
  98                exit(1);
  99            }
 100            initrd_size = load_image_targphys(loaderparams.initrd_filename,
 101                initrd_offset, loaderparams.ram_size - initrd_offset);
 102        }
 103        if (initrd_size == (target_ulong) -1) {
 104            error_report("could not load initial ram disk '%s'",
 105                         loaderparams.initrd_filename);
 106            exit(1);
 107        }
 108    }
 109    return entry;
 110}
 111
 112static void main_cpu_reset(void *opaque)
 113{
 114    ResetData *s = (ResetData *)opaque;
 115    CPUMIPSState *env = &s->cpu->env;
 116
 117    cpu_reset(CPU(s->cpu));
 118    env->active_tc.PC = s->vector & ~(target_ulong)1;
 119    if (s->vector & 1) {
 120        env->hflags |= MIPS_HFLAG_M16;
 121    }
 122}
 123
 124static void mipsnet_init(int base, qemu_irq irq, NICInfo *nd)
 125{
 126    DeviceState *dev;
 127    SysBusDevice *s;
 128
 129    dev = qdev_new("mipsnet");
 130    qdev_set_nic_properties(dev, nd);
 131
 132    s = SYS_BUS_DEVICE(dev);
 133    sysbus_realize_and_unref(s, &error_fatal);
 134    sysbus_connect_irq(s, 0, irq);
 135    memory_region_add_subregion(get_system_io(),
 136                                base,
 137                                sysbus_mmio_get_region(s, 0));
 138}
 139
 140static void
 141mips_mipssim_init(MachineState *machine)
 142{
 143    const char *kernel_filename = machine->kernel_filename;
 144    const char *kernel_cmdline = machine->kernel_cmdline;
 145    const char *initrd_filename = machine->initrd_filename;
 146    char *filename;
 147    MemoryRegion *address_space_mem = get_system_memory();
 148    MemoryRegion *isa = g_new(MemoryRegion, 1);
 149    MemoryRegion *bios = g_new(MemoryRegion, 1);
 150    Clock *cpuclk;
 151    MIPSCPU *cpu;
 152    CPUMIPSState *env;
 153    ResetData *reset_info;
 154    int bios_size;
 155
 156    cpuclk = clock_new(OBJECT(machine), "cpu-refclk");
 157#ifdef TARGET_MIPS64
 158    clock_set_hz(cpuclk, 6000000); /* 6 MHz */
 159#else
 160    clock_set_hz(cpuclk, 12000000); /* 12 MHz */
 161#endif
 162
 163    /* Init CPUs. */
 164    cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
 165    env = &cpu->env;
 166
 167    reset_info = g_malloc0(sizeof(ResetData));
 168    reset_info->cpu = cpu;
 169    reset_info->vector = env->active_tc.PC;
 170    qemu_register_reset(main_cpu_reset, reset_info);
 171
 172    /* Allocate RAM. */
 173    memory_region_init_rom(bios, NULL, "mips_mipssim.bios", BIOS_SIZE,
 174                           &error_fatal);
 175
 176    memory_region_add_subregion(address_space_mem, 0, machine->ram);
 177
 178    /* Map the BIOS / boot exception handler. */
 179    memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
 180    /* Load a BIOS / boot exception handler image. */
 181    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware ?: BIOS_FILENAME);
 182    if (filename) {
 183        bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE);
 184        g_free(filename);
 185    } else {
 186        bios_size = -1;
 187    }
 188    if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
 189        machine->firmware && !qtest_enabled()) {
 190        /* Bail out if we have neither a kernel image nor boot vector code. */
 191        error_report("Could not load MIPS bios '%s'", machine->firmware);
 192        exit(1);
 193    } else {
 194        /* We have a boot vector start address. */
 195        env->active_tc.PC = (target_long)(int32_t)0xbfc00000;
 196    }
 197
 198    if (kernel_filename) {
 199        loaderparams.ram_size = machine->ram_size;
 200        loaderparams.kernel_filename = kernel_filename;
 201        loaderparams.kernel_cmdline = kernel_cmdline;
 202        loaderparams.initrd_filename = initrd_filename;
 203        reset_info->vector = load_kernel();
 204    }
 205
 206    /* Init CPU internal devices. */
 207    cpu_mips_irq_init_cpu(cpu);
 208    cpu_mips_clock_init(cpu);
 209
 210    /* Register 64 KB of ISA IO space at 0x1fd00000. */
 211    memory_region_init_alias(isa, NULL, "isa_mmio",
 212                             get_system_io(), 0, 0x00010000);
 213    memory_region_add_subregion(get_system_memory(), 0x1fd00000, isa);
 214
 215    /*
 216     * A single 16450 sits at offset 0x3f8. It is attached to
 217     * MIPS CPU INT2, which is interrupt 4.
 218     */
 219    if (serial_hd(0)) {
 220        DeviceState *dev = qdev_new(TYPE_SERIAL_MM);
 221
 222        qdev_prop_set_chr(dev, "chardev", serial_hd(0));
 223        qdev_prop_set_uint8(dev, "regshift", 0);
 224        qdev_prop_set_uint8(dev, "endianness", DEVICE_LITTLE_ENDIAN);
 225        sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 226        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, env->irq[4]);
 227        sysbus_add_io(SYS_BUS_DEVICE(dev), 0x3f8,
 228                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
 229    }
 230
 231    if (nd_table[0].used)
 232        /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
 233        mipsnet_init(0x4200, env->irq[2], &nd_table[0]);
 234}
 235
 236static void mips_mipssim_machine_init(MachineClass *mc)
 237{
 238    mc->desc = "MIPS MIPSsim platform";
 239    mc->init = mips_mipssim_init;
 240#ifdef TARGET_MIPS64
 241    mc->default_cpu_type = MIPS_CPU_TYPE_NAME("5Kf");
 242#else
 243    mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
 244#endif
 245    mc->default_ram_id = "mips_mipssim.ram";
 246}
 247
 248DEFINE_MACHINE("mipssim", mips_mipssim_machine_init)
 249