qemu/hw/pci-host/i440fx.c
<<
>>
Prefs
   1/*
   2 * QEMU i440FX PCI Bridge Emulation
   3 *
   4 * Copyright (c) 2006 Fabrice Bellard
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "qemu/units.h"
  27#include "qemu/range.h"
  28#include "hw/i386/pc.h"
  29#include "hw/pci/pci.h"
  30#include "hw/pci/pci_host.h"
  31#include "hw/pci-host/i440fx.h"
  32#include "hw/qdev-properties.h"
  33#include "hw/sysbus.h"
  34#include "qapi/error.h"
  35#include "migration/vmstate.h"
  36#include "qapi/visitor.h"
  37#include "qemu/error-report.h"
  38#include "qom/object.h"
  39
  40/*
  41 * I440FX chipset data sheet.
  42 * https://wiki.qemu.org/File:29054901.pdf
  43 */
  44
  45OBJECT_DECLARE_SIMPLE_TYPE(I440FXState, I440FX_PCI_HOST_BRIDGE)
  46
  47struct I440FXState {
  48    PCIHostState parent_obj;
  49    Range pci_hole;
  50    uint64_t pci_hole64_size;
  51    bool pci_hole64_fix;
  52    uint32_t short_root_bus;
  53};
  54
  55#define I440FX_PAM      0x59
  56#define I440FX_PAM_SIZE 7
  57#define I440FX_SMRAM    0x72
  58
  59/* Keep it 2G to comply with older win32 guests */
  60#define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31)
  61
  62/* Older coreboot versions (4.0 and older) read a config register that doesn't
  63 * exist in real hardware, to get the RAM size from QEMU.
  64 */
  65#define I440FX_COREBOOT_RAM_SIZE 0x57
  66
  67static void i440fx_update_memory_mappings(PCII440FXState *d)
  68{
  69    int i;
  70    PCIDevice *pd = PCI_DEVICE(d);
  71
  72    memory_region_transaction_begin();
  73    for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) {
  74        pam_update(&d->pam_regions[i], i,
  75                   pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]);
  76    }
  77    memory_region_set_enabled(&d->smram_region,
  78                              !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
  79    memory_region_set_enabled(&d->smram,
  80                              pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
  81    memory_region_transaction_commit();
  82}
  83
  84
  85static void i440fx_write_config(PCIDevice *dev,
  86                                uint32_t address, uint32_t val, int len)
  87{
  88    PCII440FXState *d = I440FX_PCI_DEVICE(dev);
  89
  90    /* XXX: implement SMRAM.D_LOCK */
  91    pci_default_write_config(dev, address, val, len);
  92    if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
  93        range_covers_byte(address, len, I440FX_SMRAM)) {
  94        i440fx_update_memory_mappings(d);
  95    }
  96}
  97
  98static int i440fx_post_load(void *opaque, int version_id)
  99{
 100    PCII440FXState *d = opaque;
 101
 102    i440fx_update_memory_mappings(d);
 103    return 0;
 104}
 105
 106static const VMStateDescription vmstate_i440fx = {
 107    .name = "I440FX",
 108    .version_id = 3,
 109    .minimum_version_id = 3,
 110    .post_load = i440fx_post_load,
 111    .fields = (VMStateField[]) {
 112        VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
 113        /* Used to be smm_enabled, which was basically always zero because
 114         * SeaBIOS hardly uses SMM.  SMRAM is now handled by CPU code.
 115         */
 116        VMSTATE_UNUSED(1),
 117        VMSTATE_END_OF_LIST()
 118    }
 119};
 120
 121static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
 122                                              const char *name, void *opaque,
 123                                              Error **errp)
 124{
 125    I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 126    uint64_t val64;
 127    uint32_t value;
 128
 129    val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);
 130    value = val64;
 131    assert(value == val64);
 132    visit_type_uint32(v, name, &value, errp);
 133}
 134
 135static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
 136                                            const char *name, void *opaque,
 137                                            Error **errp)
 138{
 139    I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 140    uint64_t val64;
 141    uint32_t value;
 142
 143    val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1;
 144    value = val64;
 145    assert(value == val64);
 146    visit_type_uint32(v, name, &value, errp);
 147}
 148
 149/*
 150 * The 64bit PCI hole start is set by the Guest firmware
 151 * as the address of the first 64bit PCI MEM resource.
 152 * If no PCI device has resources on the 64bit area,
 153 * the 64bit PCI hole will start after "over 4G RAM" and the
 154 * reserved space for memory hotplug if any.
 155 */
 156static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj)
 157{
 158    PCIHostState *h = PCI_HOST_BRIDGE(obj);
 159    I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 160    Range w64;
 161    uint64_t value;
 162
 163    pci_bus_get_w64_range(h->bus, &w64);
 164    value = range_is_empty(&w64) ? 0 : range_lob(&w64);
 165    if (!value && s->pci_hole64_fix) {
 166        value = pc_pci_hole64_start();
 167    }
 168    return value;
 169}
 170
 171static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
 172                                                const char *name,
 173                                                void *opaque, Error **errp)
 174{
 175    uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
 176
 177    visit_type_uint64(v, name, &hole64_start, errp);
 178}
 179
 180/*
 181 * The 64bit PCI hole end is set by the Guest firmware
 182 * as the address of the last 64bit PCI MEM resource.
 183 * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE
 184 * that can be configured by the user.
 185 */
 186static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
 187                                              const char *name, void *opaque,
 188                                              Error **errp)
 189{
 190    PCIHostState *h = PCI_HOST_BRIDGE(obj);
 191    I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 192    uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
 193    Range w64;
 194    uint64_t value, hole64_end;
 195
 196    pci_bus_get_w64_range(h->bus, &w64);
 197    value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
 198    hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
 199    if (s->pci_hole64_fix && value < hole64_end) {
 200        value = hole64_end;
 201    }
 202    visit_type_uint64(v, name, &value, errp);
 203}
 204
 205static void i440fx_pcihost_initfn(Object *obj)
 206{
 207    PCIHostState *s = PCI_HOST_BRIDGE(obj);
 208
 209    memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
 210                          "pci-conf-idx", 4);
 211    memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
 212                          "pci-conf-data", 4);
 213}
 214
 215static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
 216{
 217    PCIHostState *s = PCI_HOST_BRIDGE(dev);
 218    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 219
 220    sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
 221    sysbus_init_ioports(sbd, 0xcf8, 4);
 222
 223    sysbus_add_io(sbd, 0xcfc, &s->data_mem);
 224    sysbus_init_ioports(sbd, 0xcfc, 4);
 225
 226    /* register i440fx 0xcf8 port as coalesced pio */
 227    memory_region_set_flush_coalesced(&s->data_mem);
 228    memory_region_add_coalescing(&s->conf_mem, 0, 4);
 229}
 230
 231static void i440fx_realize(PCIDevice *dev, Error **errp)
 232{
 233    dev->config[I440FX_SMRAM] = 0x02;
 234
 235    if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
 236        warn_report("i440fx doesn't support emulated iommu");
 237    }
 238}
 239
 240PCIBus *i440fx_init(const char *host_type, const char *pci_type,
 241                    PCII440FXState **pi440fx_state,
 242                    MemoryRegion *address_space_mem,
 243                    MemoryRegion *address_space_io,
 244                    ram_addr_t ram_size,
 245                    ram_addr_t below_4g_mem_size,
 246                    ram_addr_t above_4g_mem_size,
 247                    MemoryRegion *pci_address_space,
 248                    MemoryRegion *ram_memory)
 249{
 250    DeviceState *dev;
 251    PCIBus *b;
 252    PCIDevice *d;
 253    PCIHostState *s;
 254    PCII440FXState *f;
 255    unsigned i;
 256    I440FXState *i440fx;
 257
 258    dev = qdev_new(host_type);
 259    s = PCI_HOST_BRIDGE(dev);
 260    b = pci_root_bus_new(dev, NULL, pci_address_space,
 261                         address_space_io, 0, TYPE_PCI_BUS);
 262    s->bus = b;
 263    object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev));
 264    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 265
 266    d = pci_create_simple(b, 0, pci_type);
 267    *pi440fx_state = I440FX_PCI_DEVICE(d);
 268    f = *pi440fx_state;
 269    f->system_memory = address_space_mem;
 270    f->pci_address_space = pci_address_space;
 271    f->ram_memory = ram_memory;
 272
 273    i440fx = I440FX_PCI_HOST_BRIDGE(dev);
 274    range_set_bounds(&i440fx->pci_hole, below_4g_mem_size,
 275                     IO_APIC_DEFAULT_ADDRESS - 1);
 276
 277    /* setup pci memory mapping */
 278    pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
 279                           f->pci_address_space);
 280
 281    /* if *disabled* show SMRAM to all CPUs */
 282    memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
 283                             f->pci_address_space, 0xa0000, 0x20000);
 284    memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
 285                                        &f->smram_region, 1);
 286    memory_region_set_enabled(&f->smram_region, true);
 287
 288    /* smram, as seen by SMM CPUs */
 289    memory_region_init(&f->smram, OBJECT(d), "smram", 4 * GiB);
 290    memory_region_set_enabled(&f->smram, true);
 291    memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
 292                             f->ram_memory, 0xa0000, 0x20000);
 293    memory_region_set_enabled(&f->low_smram, true);
 294    memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
 295    object_property_add_const_link(qdev_get_machine(), "smram",
 296                                   OBJECT(&f->smram));
 297
 298    init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 299             &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 300    for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) {
 301        init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 302                 &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 303                 PAM_EXPAN_SIZE);
 304    }
 305
 306    ram_size = ram_size / 8 / 1024 / 1024;
 307    if (ram_size > 255) {
 308        ram_size = 255;
 309    }
 310    d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
 311
 312    i440fx_update_memory_mappings(f);
 313
 314    return b;
 315}
 316
 317PCIBus *find_i440fx(void)
 318{
 319    PCIHostState *s = OBJECT_CHECK(PCIHostState,
 320                                   object_resolve_path("/machine/i440fx", NULL),
 321                                   TYPE_PCI_HOST_BRIDGE);
 322    return s ? s->bus : NULL;
 323}
 324
 325static void i440fx_class_init(ObjectClass *klass, void *data)
 326{
 327    DeviceClass *dc = DEVICE_CLASS(klass);
 328    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 329
 330    k->realize = i440fx_realize;
 331    k->config_write = i440fx_write_config;
 332    k->vendor_id = PCI_VENDOR_ID_INTEL;
 333    k->device_id = PCI_DEVICE_ID_INTEL_82441;
 334    k->revision = 0x02;
 335    k->class_id = PCI_CLASS_BRIDGE_HOST;
 336    dc->desc = "Host bridge";
 337    dc->vmsd = &vmstate_i440fx;
 338    /*
 339     * PCI-facing part of the host bridge, not usable without the
 340     * host-facing part, which can't be device_add'ed, yet.
 341     */
 342    dc->user_creatable = false;
 343    dc->hotpluggable   = false;
 344}
 345
 346static const TypeInfo i440fx_info = {
 347    .name          = TYPE_I440FX_PCI_DEVICE,
 348    .parent        = TYPE_PCI_DEVICE,
 349    .instance_size = sizeof(PCII440FXState),
 350    .class_init    = i440fx_class_init,
 351    .interfaces = (InterfaceInfo[]) {
 352        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 353        { },
 354    },
 355};
 356
 357static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
 358                                                PCIBus *rootbus)
 359{
 360    I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
 361
 362    /* For backwards compat with old device paths */
 363    if (s->short_root_bus) {
 364        return "0000";
 365    }
 366    return "0000:00";
 367}
 368
 369static Property i440fx_props[] = {
 370    DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
 371                     pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),
 372    DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
 373    DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true),
 374    DEFINE_PROP_END_OF_LIST(),
 375};
 376
 377static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
 378{
 379    DeviceClass *dc = DEVICE_CLASS(klass);
 380    PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 381
 382    hc->root_bus_path = i440fx_pcihost_root_bus_path;
 383    dc->realize = i440fx_pcihost_realize;
 384    dc->fw_name = "pci";
 385    device_class_set_props(dc, i440fx_props);
 386    /* Reason: needs to be wired up by pc_init1 */
 387    dc->user_creatable = false;
 388
 389    object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
 390                              i440fx_pcihost_get_pci_hole_start,
 391                              NULL, NULL, NULL);
 392
 393    object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE_END, "uint32",
 394                              i440fx_pcihost_get_pci_hole_end,
 395                              NULL, NULL, NULL);
 396
 397    object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE64_START, "uint64",
 398                              i440fx_pcihost_get_pci_hole64_start,
 399                              NULL, NULL, NULL);
 400
 401    object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE64_END, "uint64",
 402                              i440fx_pcihost_get_pci_hole64_end,
 403                              NULL, NULL, NULL);
 404}
 405
 406static const TypeInfo i440fx_pcihost_info = {
 407    .name          = TYPE_I440FX_PCI_HOST_BRIDGE,
 408    .parent        = TYPE_PCI_HOST_BRIDGE,
 409    .instance_size = sizeof(I440FXState),
 410    .instance_init = i440fx_pcihost_initfn,
 411    .class_init    = i440fx_pcihost_class_init,
 412};
 413
 414static void i440fx_register_types(void)
 415{
 416    type_register_static(&i440fx_info);
 417    type_register_static(&i440fx_pcihost_info);
 418}
 419
 420type_init(i440fx_register_types)
 421