1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25#include "qemu/osdep.h"
26#include "qemu-common.h"
27#include "qemu/datadir.h"
28#include "qemu/units.h"
29#include "hw/irq.h"
30#include "hw/pci/pci.h"
31#include "hw/pci/pci_bridge.h"
32#include "hw/pci/pci_bus.h"
33#include "hw/pci/pci_host.h"
34#include "hw/qdev-properties.h"
35#include "hw/qdev-properties-system.h"
36#include "migration/qemu-file-types.h"
37#include "migration/vmstate.h"
38#include "monitor/monitor.h"
39#include "net/net.h"
40#include "sysemu/numa.h"
41#include "sysemu/sysemu.h"
42#include "hw/loader.h"
43#include "qemu/error-report.h"
44#include "qemu/range.h"
45#include "trace.h"
46#include "hw/pci/msi.h"
47#include "hw/pci/msix.h"
48#include "exec/address-spaces.h"
49#include "hw/hotplug.h"
50#include "hw/boards.h"
51#include "qapi/error.h"
52#include "qapi/qapi-commands-pci.h"
53#include "qemu/cutils.h"
54
55
56#ifdef DEBUG_PCI
57# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
58#else
59# define PCI_DPRINTF(format, ...) do { } while (0)
60#endif
61
62bool pci_available = true;
63
64static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
65static char *pcibus_get_dev_path(DeviceState *dev);
66static char *pcibus_get_fw_dev_path(DeviceState *dev);
67static void pcibus_reset(BusState *qbus);
68
69static Property pci_props[] = {
70 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
71 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
72 DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, -1),
73 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
74 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
75 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
76 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
77 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true),
78 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
79 QEMU_PCIE_EXTCAP_INIT_BITNR, true),
80 DEFINE_PROP_STRING("failover_pair_id", PCIDevice,
81 failover_pair_id),
82 DEFINE_PROP_UINT32("acpi-index", PCIDevice, acpi_index, 0),
83 DEFINE_PROP_END_OF_LIST()
84};
85
86static const VMStateDescription vmstate_pcibus = {
87 .name = "PCIBUS",
88 .version_id = 1,
89 .minimum_version_id = 1,
90 .fields = (VMStateField[]) {
91 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL),
92 VMSTATE_VARRAY_INT32(irq_count, PCIBus,
93 nirq, 0, vmstate_info_int32,
94 int32_t),
95 VMSTATE_END_OF_LIST()
96 }
97};
98
99static void pci_init_bus_master(PCIDevice *pci_dev)
100{
101 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev);
102
103 memory_region_init_alias(&pci_dev->bus_master_enable_region,
104 OBJECT(pci_dev), "bus master",
105 dma_as->root, 0, memory_region_size(dma_as->root));
106 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
107 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0,
108 &pci_dev->bus_master_enable_region);
109}
110
111static void pcibus_machine_done(Notifier *notifier, void *data)
112{
113 PCIBus *bus = container_of(notifier, PCIBus, machine_done);
114 int i;
115
116 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
117 if (bus->devices[i]) {
118 pci_init_bus_master(bus->devices[i]);
119 }
120 }
121}
122
123static void pci_bus_realize(BusState *qbus, Error **errp)
124{
125 PCIBus *bus = PCI_BUS(qbus);
126
127 bus->machine_done.notify = pcibus_machine_done;
128 qemu_add_machine_init_done_notifier(&bus->machine_done);
129
130 vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_pcibus, bus);
131}
132
133static void pcie_bus_realize(BusState *qbus, Error **errp)
134{
135 PCIBus *bus = PCI_BUS(qbus);
136 Error *local_err = NULL;
137
138 pci_bus_realize(qbus, &local_err);
139 if (local_err) {
140 error_propagate(errp, local_err);
141 return;
142 }
143
144
145
146
147
148 if (pci_bus_is_root(bus)) {
149 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
150 } else {
151 PCIBus *parent_bus = pci_get_bus(bus->parent_dev);
152
153 if (pci_bus_allows_extended_config_space(parent_bus)) {
154 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
155 }
156 }
157}
158
159static void pci_bus_unrealize(BusState *qbus)
160{
161 PCIBus *bus = PCI_BUS(qbus);
162
163 qemu_remove_machine_init_done_notifier(&bus->machine_done);
164
165 vmstate_unregister(NULL, &vmstate_pcibus, bus);
166}
167
168static int pcibus_num(PCIBus *bus)
169{
170 if (pci_bus_is_root(bus)) {
171 return 0;
172 }
173 return bus->parent_dev->config[PCI_SECONDARY_BUS];
174}
175
176static uint16_t pcibus_numa_node(PCIBus *bus)
177{
178 return NUMA_NODE_UNASSIGNED;
179}
180
181static void pci_bus_class_init(ObjectClass *klass, void *data)
182{
183 BusClass *k = BUS_CLASS(klass);
184 PCIBusClass *pbc = PCI_BUS_CLASS(klass);
185
186 k->print_dev = pcibus_dev_print;
187 k->get_dev_path = pcibus_get_dev_path;
188 k->get_fw_dev_path = pcibus_get_fw_dev_path;
189 k->realize = pci_bus_realize;
190 k->unrealize = pci_bus_unrealize;
191 k->reset = pcibus_reset;
192
193 pbc->bus_num = pcibus_num;
194 pbc->numa_node = pcibus_numa_node;
195}
196
197static const TypeInfo pci_bus_info = {
198 .name = TYPE_PCI_BUS,
199 .parent = TYPE_BUS,
200 .instance_size = sizeof(PCIBus),
201 .class_size = sizeof(PCIBusClass),
202 .class_init = pci_bus_class_init,
203};
204
205static const TypeInfo pcie_interface_info = {
206 .name = INTERFACE_PCIE_DEVICE,
207 .parent = TYPE_INTERFACE,
208};
209
210static const TypeInfo conventional_pci_interface_info = {
211 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE,
212 .parent = TYPE_INTERFACE,
213};
214
215static void pcie_bus_class_init(ObjectClass *klass, void *data)
216{
217 BusClass *k = BUS_CLASS(klass);
218
219 k->realize = pcie_bus_realize;
220}
221
222static const TypeInfo pcie_bus_info = {
223 .name = TYPE_PCIE_BUS,
224 .parent = TYPE_PCI_BUS,
225 .class_init = pcie_bus_class_init,
226};
227
228static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
229static void pci_update_mappings(PCIDevice *d);
230static void pci_irq_handler(void *opaque, int irq_num, int level);
231static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **);
232static void pci_del_option_rom(PCIDevice *pdev);
233
234static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
235static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
236
237static QLIST_HEAD(, PCIHostState) pci_host_bridges;
238
239int pci_bar(PCIDevice *d, int reg)
240{
241 uint8_t type;
242
243 if (reg != PCI_ROM_SLOT)
244 return PCI_BASE_ADDRESS_0 + reg * 4;
245
246 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
247 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
248}
249
250static inline int pci_irq_state(PCIDevice *d, int irq_num)
251{
252 return (d->irq_state >> irq_num) & 0x1;
253}
254
255static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
256{
257 d->irq_state &= ~(0x1 << irq_num);
258 d->irq_state |= level << irq_num;
259}
260
261static void pci_bus_change_irq_level(PCIBus *bus, int irq_num, int change)
262{
263 assert(irq_num >= 0);
264 assert(irq_num < bus->nirq);
265 bus->irq_count[irq_num] += change;
266 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
267}
268
269static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
270{
271 PCIBus *bus;
272 for (;;) {
273 bus = pci_get_bus(pci_dev);
274 irq_num = bus->map_irq(pci_dev, irq_num);
275 if (bus->set_irq)
276 break;
277 pci_dev = bus->parent_dev;
278 }
279 pci_bus_change_irq_level(bus, irq_num, change);
280}
281
282int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
283{
284 assert(irq_num >= 0);
285 assert(irq_num < bus->nirq);
286 return !!bus->irq_count[irq_num];
287}
288
289
290
291static void pci_update_irq_status(PCIDevice *dev)
292{
293 if (dev->irq_state) {
294 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
295 } else {
296 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
297 }
298}
299
300void pci_device_deassert_intx(PCIDevice *dev)
301{
302 int i;
303 for (i = 0; i < PCI_NUM_PINS; ++i) {
304 pci_irq_handler(dev, i, 0);
305 }
306}
307
308static void pci_do_device_reset(PCIDevice *dev)
309{
310 int r;
311
312 pci_device_deassert_intx(dev);
313 assert(dev->irq_state == 0);
314
315
316 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
317 pci_get_word(dev->wmask + PCI_COMMAND) |
318 pci_get_word(dev->w1cmask + PCI_COMMAND));
319 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
320 pci_get_word(dev->wmask + PCI_STATUS) |
321 pci_get_word(dev->w1cmask + PCI_STATUS));
322
323 pci_byte_test_and_clear_mask(dev->config + PCI_INTERRUPT_LINE,
324 pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) |
325 pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE));
326 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
327 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
328 PCIIORegion *region = &dev->io_regions[r];
329 if (!region->size) {
330 continue;
331 }
332
333 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
334 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
335 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
336 } else {
337 pci_set_long(dev->config + pci_bar(dev, r), region->type);
338 }
339 }
340 pci_update_mappings(dev);
341
342 msi_reset(dev);
343 msix_reset(dev);
344}
345
346
347
348
349
350void pci_device_reset(PCIDevice *dev)
351{
352 qdev_reset_all(&dev->qdev);
353 pci_do_device_reset(dev);
354}
355
356
357
358
359
360
361static void pcibus_reset(BusState *qbus)
362{
363 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
364 int i;
365
366 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
367 if (bus->devices[i]) {
368 pci_do_device_reset(bus->devices[i]);
369 }
370 }
371
372 for (i = 0; i < bus->nirq; i++) {
373 assert(bus->irq_count[i] == 0);
374 }
375}
376
377static void pci_host_bus_register(DeviceState *host)
378{
379 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
380
381 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
382}
383
384static void pci_host_bus_unregister(DeviceState *host)
385{
386 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
387
388 QLIST_REMOVE(host_bridge, next);
389}
390
391PCIBus *pci_device_root_bus(const PCIDevice *d)
392{
393 PCIBus *bus = pci_get_bus(d);
394
395 while (!pci_bus_is_root(bus)) {
396 d = bus->parent_dev;
397 assert(d != NULL);
398
399 bus = pci_get_bus(d);
400 }
401
402 return bus;
403}
404
405const char *pci_root_bus_path(PCIDevice *dev)
406{
407 PCIBus *rootbus = pci_device_root_bus(dev);
408 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
409 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
410
411 assert(host_bridge->bus == rootbus);
412
413 if (hc->root_bus_path) {
414 return (*hc->root_bus_path)(host_bridge, rootbus);
415 }
416
417 return rootbus->qbus.name;
418}
419
420static void pci_root_bus_init(PCIBus *bus, DeviceState *parent,
421 MemoryRegion *address_space_mem,
422 MemoryRegion *address_space_io,
423 uint8_t devfn_min)
424{
425 assert(PCI_FUNC(devfn_min) == 0);
426 bus->devfn_min = devfn_min;
427 bus->slot_reserved_mask = 0x0;
428 bus->address_space_mem = address_space_mem;
429 bus->address_space_io = address_space_io;
430 bus->flags |= PCI_BUS_IS_ROOT;
431
432
433 QLIST_INIT(&bus->child);
434
435 pci_host_bus_register(parent);
436}
437
438static void pci_bus_uninit(PCIBus *bus)
439{
440 pci_host_bus_unregister(BUS(bus)->parent);
441}
442
443bool pci_bus_is_express(PCIBus *bus)
444{
445 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
446}
447
448void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
449 const char *name,
450 MemoryRegion *address_space_mem,
451 MemoryRegion *address_space_io,
452 uint8_t devfn_min, const char *typename)
453{
454 qbus_create_inplace(bus, bus_size, typename, parent, name);
455 pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
456 devfn_min);
457}
458
459PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
460 MemoryRegion *address_space_mem,
461 MemoryRegion *address_space_io,
462 uint8_t devfn_min, const char *typename)
463{
464 PCIBus *bus;
465
466 bus = PCI_BUS(qbus_create(typename, parent, name));
467 pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
468 devfn_min);
469 return bus;
470}
471
472void pci_root_bus_cleanup(PCIBus *bus)
473{
474 pci_bus_uninit(bus);
475
476 qbus_unrealize(BUS(bus));
477}
478
479void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
480 void *irq_opaque, int nirq)
481{
482 bus->set_irq = set_irq;
483 bus->map_irq = map_irq;
484 bus->irq_opaque = irq_opaque;
485 bus->nirq = nirq;
486 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
487}
488
489void pci_bus_irqs_cleanup(PCIBus *bus)
490{
491 bus->set_irq = NULL;
492 bus->map_irq = NULL;
493 bus->irq_opaque = NULL;
494 bus->nirq = 0;
495 g_free(bus->irq_count);
496}
497
498PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
499 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
500 void *irq_opaque,
501 MemoryRegion *address_space_mem,
502 MemoryRegion *address_space_io,
503 uint8_t devfn_min, int nirq,
504 const char *typename)
505{
506 PCIBus *bus;
507
508 bus = pci_root_bus_new(parent, name, address_space_mem,
509 address_space_io, devfn_min, typename);
510 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
511 return bus;
512}
513
514void pci_unregister_root_bus(PCIBus *bus)
515{
516 pci_bus_irqs_cleanup(bus);
517 pci_root_bus_cleanup(bus);
518}
519
520int pci_bus_num(PCIBus *s)
521{
522 return PCI_BUS_GET_CLASS(s)->bus_num(s);
523}
524
525int pci_bus_numa_node(PCIBus *bus)
526{
527 return PCI_BUS_GET_CLASS(bus)->numa_node(bus);
528}
529
530static int get_pci_config_device(QEMUFile *f, void *pv, size_t size,
531 const VMStateField *field)
532{
533 PCIDevice *s = container_of(pv, PCIDevice, config);
534 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
535 uint8_t *config;
536 int i;
537
538 assert(size == pci_config_size(s));
539 config = g_malloc(size);
540
541 qemu_get_buffer(f, config, size);
542 for (i = 0; i < size; ++i) {
543 if ((config[i] ^ s->config[i]) &
544 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
545 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
546 "cmask: %x wmask: %x w1cmask:%x", __func__,
547 i, config[i], s->config[i],
548 s->cmask[i], s->wmask[i], s->w1cmask[i]);
549 g_free(config);
550 return -EINVAL;
551 }
552 }
553 memcpy(s->config, config, size);
554
555 pci_update_mappings(s);
556 if (pc->is_bridge) {
557 PCIBridge *b = PCI_BRIDGE(s);
558 pci_bridge_update_mappings(b);
559 }
560
561 memory_region_set_enabled(&s->bus_master_enable_region,
562 pci_get_word(s->config + PCI_COMMAND)
563 & PCI_COMMAND_MASTER);
564
565 g_free(config);
566 return 0;
567}
568
569
570static int put_pci_config_device(QEMUFile *f, void *pv, size_t size,
571 const VMStateField *field, JSONWriter *vmdesc)
572{
573 const uint8_t **v = pv;
574 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
575 qemu_put_buffer(f, *v, size);
576
577 return 0;
578}
579
580static VMStateInfo vmstate_info_pci_config = {
581 .name = "pci config",
582 .get = get_pci_config_device,
583 .put = put_pci_config_device,
584};
585
586static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size,
587 const VMStateField *field)
588{
589 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
590 uint32_t irq_state[PCI_NUM_PINS];
591 int i;
592 for (i = 0; i < PCI_NUM_PINS; ++i) {
593 irq_state[i] = qemu_get_be32(f);
594 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
595 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
596 irq_state[i]);
597 return -EINVAL;
598 }
599 }
600
601 for (i = 0; i < PCI_NUM_PINS; ++i) {
602 pci_set_irq_state(s, i, irq_state[i]);
603 }
604
605 return 0;
606}
607
608static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size,
609 const VMStateField *field, JSONWriter *vmdesc)
610{
611 int i;
612 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
613
614 for (i = 0; i < PCI_NUM_PINS; ++i) {
615 qemu_put_be32(f, pci_irq_state(s, i));
616 }
617
618 return 0;
619}
620
621static VMStateInfo vmstate_info_pci_irq_state = {
622 .name = "pci irq state",
623 .get = get_pci_irq_state,
624 .put = put_pci_irq_state,
625};
626
627static bool migrate_is_pcie(void *opaque, int version_id)
628{
629 return pci_is_express((PCIDevice *)opaque);
630}
631
632static bool migrate_is_not_pcie(void *opaque, int version_id)
633{
634 return !pci_is_express((PCIDevice *)opaque);
635}
636
637const VMStateDescription vmstate_pci_device = {
638 .name = "PCIDevice",
639 .version_id = 2,
640 .minimum_version_id = 1,
641 .fields = (VMStateField[]) {
642 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
643 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
644 migrate_is_not_pcie,
645 0, vmstate_info_pci_config,
646 PCI_CONFIG_SPACE_SIZE),
647 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
648 migrate_is_pcie,
649 0, vmstate_info_pci_config,
650 PCIE_CONFIG_SPACE_SIZE),
651 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
652 vmstate_info_pci_irq_state,
653 PCI_NUM_PINS * sizeof(int32_t)),
654 VMSTATE_END_OF_LIST()
655 }
656};
657
658
659void pci_device_save(PCIDevice *s, QEMUFile *f)
660{
661
662
663
664
665 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
666 vmstate_save_state(f, &vmstate_pci_device, s, NULL);
667
668 pci_update_irq_status(s);
669}
670
671int pci_device_load(PCIDevice *s, QEMUFile *f)
672{
673 int ret;
674 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
675
676 pci_update_irq_status(s);
677 return ret;
678}
679
680static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
681{
682 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
683 pci_default_sub_vendor_id);
684 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
685 pci_default_sub_device_id);
686}
687
688
689
690
691
692static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
693 unsigned int *slotp, unsigned int *funcp)
694{
695 const char *p;
696 char *e;
697 unsigned long val;
698 unsigned long dom = 0, bus = 0;
699 unsigned int slot = 0;
700 unsigned int func = 0;
701
702 p = addr;
703 val = strtoul(p, &e, 16);
704 if (e == p)
705 return -1;
706 if (*e == ':') {
707 bus = val;
708 p = e + 1;
709 val = strtoul(p, &e, 16);
710 if (e == p)
711 return -1;
712 if (*e == ':') {
713 dom = bus;
714 bus = val;
715 p = e + 1;
716 val = strtoul(p, &e, 16);
717 if (e == p)
718 return -1;
719 }
720 }
721
722 slot = val;
723
724 if (funcp != NULL) {
725 if (*e != '.')
726 return -1;
727
728 p = e + 1;
729 val = strtoul(p, &e, 16);
730 if (e == p)
731 return -1;
732
733 func = val;
734 }
735
736
737 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
738 return -1;
739
740 if (*e)
741 return -1;
742
743 *domp = dom;
744 *busp = bus;
745 *slotp = slot;
746 if (funcp != NULL)
747 *funcp = func;
748 return 0;
749}
750
751static void pci_init_cmask(PCIDevice *dev)
752{
753 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
754 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
755 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
756 dev->cmask[PCI_REVISION_ID] = 0xff;
757 dev->cmask[PCI_CLASS_PROG] = 0xff;
758 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
759 dev->cmask[PCI_HEADER_TYPE] = 0xff;
760 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
761}
762
763static void pci_init_wmask(PCIDevice *dev)
764{
765 int config_size = pci_config_size(dev);
766
767 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
768 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
769 pci_set_word(dev->wmask + PCI_COMMAND,
770 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
771 PCI_COMMAND_INTX_DISABLE);
772 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
773
774 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
775 config_size - PCI_CONFIG_HEADER_SIZE);
776}
777
778static void pci_init_w1cmask(PCIDevice *dev)
779{
780
781
782
783
784 pci_set_word(dev->w1cmask + PCI_STATUS,
785 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
786 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
787 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
788}
789
790static void pci_init_mask_bridge(PCIDevice *d)
791{
792
793
794 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
795
796
797 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
798 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
799 pci_set_word(d->wmask + PCI_MEMORY_BASE,
800 PCI_MEMORY_RANGE_MASK & 0xffff);
801 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
802 PCI_MEMORY_RANGE_MASK & 0xffff);
803 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
804 PCI_PREF_RANGE_MASK & 0xffff);
805 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
806 PCI_PREF_RANGE_MASK & 0xffff);
807
808
809 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
810
811
812 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
813 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
814 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
815 PCI_PREF_RANGE_TYPE_64);
816 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
817 PCI_PREF_RANGE_TYPE_64);
818
819
820
821
822
823 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
824 PCI_BRIDGE_CTL_PARITY |
825 PCI_BRIDGE_CTL_SERR |
826 PCI_BRIDGE_CTL_ISA |
827 PCI_BRIDGE_CTL_VGA |
828 PCI_BRIDGE_CTL_VGA_16BIT |
829 PCI_BRIDGE_CTL_MASTER_ABORT |
830 PCI_BRIDGE_CTL_BUS_RESET |
831 PCI_BRIDGE_CTL_FAST_BACK |
832 PCI_BRIDGE_CTL_DISCARD |
833 PCI_BRIDGE_CTL_SEC_DISCARD |
834 PCI_BRIDGE_CTL_DISCARD_SERR);
835
836
837 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
838 PCI_BRIDGE_CTL_DISCARD_STATUS);
839 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
840 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
841 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
842 PCI_PREF_RANGE_TYPE_MASK);
843 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
844 PCI_PREF_RANGE_TYPE_MASK);
845}
846
847static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp)
848{
849 uint8_t slot = PCI_SLOT(dev->devfn);
850 uint8_t func;
851
852 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
853 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
854 }
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869 if (PCI_FUNC(dev->devfn)) {
870 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
871 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
872
873 error_setg(errp, "PCI: single function device can't be populated "
874 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
875 return;
876 }
877 return;
878 }
879
880 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
881 return;
882 }
883
884 for (func = 1; func < PCI_FUNC_MAX; ++func) {
885 if (bus->devices[PCI_DEVFN(slot, func)]) {
886 error_setg(errp, "PCI: %x.0 indicates single function, "
887 "but %x.%x is already populated.",
888 slot, slot, func);
889 return;
890 }
891 }
892}
893
894static void pci_config_alloc(PCIDevice *pci_dev)
895{
896 int config_size = pci_config_size(pci_dev);
897
898 pci_dev->config = g_malloc0(config_size);
899 pci_dev->cmask = g_malloc0(config_size);
900 pci_dev->wmask = g_malloc0(config_size);
901 pci_dev->w1cmask = g_malloc0(config_size);
902 pci_dev->used = g_malloc0(config_size);
903}
904
905static void pci_config_free(PCIDevice *pci_dev)
906{
907 g_free(pci_dev->config);
908 g_free(pci_dev->cmask);
909 g_free(pci_dev->wmask);
910 g_free(pci_dev->w1cmask);
911 g_free(pci_dev->used);
912}
913
914static void do_pci_unregister_device(PCIDevice *pci_dev)
915{
916 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL;
917 pci_config_free(pci_dev);
918
919 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) {
920 memory_region_del_subregion(&pci_dev->bus_master_container_region,
921 &pci_dev->bus_master_enable_region);
922 }
923 address_space_destroy(&pci_dev->bus_master_as);
924}
925
926
927static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache)
928{
929 uint8_t bus_n;
930 uint16_t result;
931
932 switch (cache->type) {
933 case PCI_REQ_ID_BDF:
934 result = pci_get_bdf(cache->dev);
935 break;
936 case PCI_REQ_ID_SECONDARY_BUS:
937 bus_n = pci_dev_bus_num(cache->dev);
938 result = PCI_BUILD_BDF(bus_n, 0);
939 break;
940 default:
941 error_report("Invalid PCI requester ID cache type: %d",
942 cache->type);
943 exit(1);
944 break;
945 }
946
947 return result;
948}
949
950
951
952
953
954
955
956
957
958
959static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev)
960{
961 PCIDevice *parent;
962 PCIReqIDCache cache = {
963 .dev = dev,
964 .type = PCI_REQ_ID_BDF,
965 };
966
967 while (!pci_bus_is_root(pci_get_bus(dev))) {
968
969 parent = pci_get_bus(dev)->parent_dev;
970 if (pci_is_express(parent)) {
971 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
972
973
974
975
976 cache.type = PCI_REQ_ID_SECONDARY_BUS;
977 cache.dev = dev;
978 }
979 } else {
980
981
982
983
984
985
986
987 cache.type = PCI_REQ_ID_BDF;
988 cache.dev = parent;
989 }
990 dev = parent;
991 }
992
993 return cache;
994}
995
996uint16_t pci_requester_id(PCIDevice *dev)
997{
998 return pci_req_id_cache_extract(&dev->requester_id_cache);
999}
1000
1001static bool pci_bus_devfn_available(PCIBus *bus, int devfn)
1002{
1003 return !(bus->devices[devfn]);
1004}
1005
1006static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn)
1007{
1008 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn));
1009}
1010
1011
1012static PCIDevice *do_pci_register_device(PCIDevice *pci_dev,
1013 const char *name, int devfn,
1014 Error **errp)
1015{
1016 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1017 PCIConfigReadFunc *config_read = pc->config_read;
1018 PCIConfigWriteFunc *config_write = pc->config_write;
1019 Error *local_err = NULL;
1020 DeviceState *dev = DEVICE(pci_dev);
1021 PCIBus *bus = pci_get_bus(pci_dev);
1022
1023
1024 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) {
1025 error_setg(errp,
1026 "PCI: Only PCI/PCIe bridges can be plugged into %s",
1027 bus->parent_dev->name);
1028 return NULL;
1029 }
1030
1031 if (devfn < 0) {
1032 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
1033 devfn += PCI_FUNC_MAX) {
1034 if (pci_bus_devfn_available(bus, devfn) &&
1035 !pci_bus_devfn_reserved(bus, devfn)) {
1036 goto found;
1037 }
1038 }
1039 error_setg(errp, "PCI: no slot/function available for %s, all in use "
1040 "or reserved", name);
1041 return NULL;
1042 found: ;
1043 } else if (pci_bus_devfn_reserved(bus, devfn)) {
1044 error_setg(errp, "PCI: slot %d function %d not available for %s,"
1045 " reserved",
1046 PCI_SLOT(devfn), PCI_FUNC(devfn), name);
1047 return NULL;
1048 } else if (!pci_bus_devfn_available(bus, devfn)) {
1049 error_setg(errp, "PCI: slot %d function %d not available for %s,"
1050 " in use by %s",
1051 PCI_SLOT(devfn), PCI_FUNC(devfn), name,
1052 bus->devices[devfn]->name);
1053 return NULL;
1054 } else if (dev->hotplugged &&
1055 pci_get_function_0(pci_dev)) {
1056 error_setg(errp, "PCI: slot %d function 0 already occupied by %s,"
1057 " new func %s cannot be exposed to guest.",
1058 PCI_SLOT(pci_get_function_0(pci_dev)->devfn),
1059 pci_get_function_0(pci_dev)->name,
1060 name);
1061
1062 return NULL;
1063 }
1064
1065 pci_dev->devfn = devfn;
1066 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev);
1067 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
1068
1069 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
1070 "bus master container", UINT64_MAX);
1071 address_space_init(&pci_dev->bus_master_as,
1072 &pci_dev->bus_master_container_region, pci_dev->name);
1073
1074 if (phase_check(PHASE_MACHINE_READY)) {
1075 pci_init_bus_master(pci_dev);
1076 }
1077 pci_dev->irq_state = 0;
1078 pci_config_alloc(pci_dev);
1079
1080 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
1081 pci_config_set_device_id(pci_dev->config, pc->device_id);
1082 pci_config_set_revision(pci_dev->config, pc->revision);
1083 pci_config_set_class(pci_dev->config, pc->class_id);
1084
1085 if (!pc->is_bridge) {
1086 if (pc->subsystem_vendor_id || pc->subsystem_id) {
1087 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1088 pc->subsystem_vendor_id);
1089 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1090 pc->subsystem_id);
1091 } else {
1092 pci_set_default_subsystem_id(pci_dev);
1093 }
1094 } else {
1095
1096 assert(!pc->subsystem_vendor_id);
1097 assert(!pc->subsystem_id);
1098 }
1099 pci_init_cmask(pci_dev);
1100 pci_init_wmask(pci_dev);
1101 pci_init_w1cmask(pci_dev);
1102 if (pc->is_bridge) {
1103 pci_init_mask_bridge(pci_dev);
1104 }
1105 pci_init_multifunction(bus, pci_dev, &local_err);
1106 if (local_err) {
1107 error_propagate(errp, local_err);
1108 do_pci_unregister_device(pci_dev);
1109 return NULL;
1110 }
1111
1112 if (!config_read)
1113 config_read = pci_default_read_config;
1114 if (!config_write)
1115 config_write = pci_default_write_config;
1116 pci_dev->config_read = config_read;
1117 pci_dev->config_write = config_write;
1118 bus->devices[devfn] = pci_dev;
1119 pci_dev->version_id = 2;
1120 return pci_dev;
1121}
1122
1123static void pci_unregister_io_regions(PCIDevice *pci_dev)
1124{
1125 PCIIORegion *r;
1126 int i;
1127
1128 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1129 r = &pci_dev->io_regions[i];
1130 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
1131 continue;
1132 memory_region_del_subregion(r->address_space, r->memory);
1133 }
1134
1135 pci_unregister_vga(pci_dev);
1136}
1137
1138static void pci_qdev_unrealize(DeviceState *dev)
1139{
1140 PCIDevice *pci_dev = PCI_DEVICE(dev);
1141 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1142
1143 pci_unregister_io_regions(pci_dev);
1144 pci_del_option_rom(pci_dev);
1145
1146 if (pc->exit) {
1147 pc->exit(pci_dev);
1148 }
1149
1150 pci_device_deassert_intx(pci_dev);
1151 do_pci_unregister_device(pci_dev);
1152}
1153
1154void pci_register_bar(PCIDevice *pci_dev, int region_num,
1155 uint8_t type, MemoryRegion *memory)
1156{
1157 PCIIORegion *r;
1158 uint32_t addr;
1159 uint64_t wmask;
1160 pcibus_t size = memory_region_size(memory);
1161 uint8_t hdr_type;
1162
1163 assert(region_num >= 0);
1164 assert(region_num < PCI_NUM_REGIONS);
1165 assert(is_power_of_2(size));
1166
1167
1168 hdr_type =
1169 pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1170 assert(hdr_type != PCI_HEADER_TYPE_BRIDGE || region_num < 2);
1171
1172 r = &pci_dev->io_regions[region_num];
1173 r->addr = PCI_BAR_UNMAPPED;
1174 r->size = size;
1175 r->type = type;
1176 r->memory = memory;
1177 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO
1178 ? pci_get_bus(pci_dev)->address_space_io
1179 : pci_get_bus(pci_dev)->address_space_mem;
1180
1181 wmask = ~(size - 1);
1182 if (region_num == PCI_ROM_SLOT) {
1183
1184 wmask |= PCI_ROM_ADDRESS_ENABLE;
1185 }
1186
1187 addr = pci_bar(pci_dev, region_num);
1188 pci_set_long(pci_dev->config + addr, type);
1189
1190 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
1191 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1192 pci_set_quad(pci_dev->wmask + addr, wmask);
1193 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
1194 } else {
1195 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
1196 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
1197 }
1198}
1199
1200static void pci_update_vga(PCIDevice *pci_dev)
1201{
1202 uint16_t cmd;
1203
1204 if (!pci_dev->has_vga) {
1205 return;
1206 }
1207
1208 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
1209
1210 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
1211 cmd & PCI_COMMAND_MEMORY);
1212 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
1213 cmd & PCI_COMMAND_IO);
1214 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
1215 cmd & PCI_COMMAND_IO);
1216}
1217
1218void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
1219 MemoryRegion *io_lo, MemoryRegion *io_hi)
1220{
1221 PCIBus *bus = pci_get_bus(pci_dev);
1222
1223 assert(!pci_dev->has_vga);
1224
1225 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
1226 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
1227 memory_region_add_subregion_overlap(bus->address_space_mem,
1228 QEMU_PCI_VGA_MEM_BASE, mem, 1);
1229
1230 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
1231 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
1232 memory_region_add_subregion_overlap(bus->address_space_io,
1233 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
1234
1235 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
1236 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
1237 memory_region_add_subregion_overlap(bus->address_space_io,
1238 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
1239 pci_dev->has_vga = true;
1240
1241 pci_update_vga(pci_dev);
1242}
1243
1244void pci_unregister_vga(PCIDevice *pci_dev)
1245{
1246 PCIBus *bus = pci_get_bus(pci_dev);
1247
1248 if (!pci_dev->has_vga) {
1249 return;
1250 }
1251
1252 memory_region_del_subregion(bus->address_space_mem,
1253 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1254 memory_region_del_subregion(bus->address_space_io,
1255 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1256 memory_region_del_subregion(bus->address_space_io,
1257 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1258 pci_dev->has_vga = false;
1259}
1260
1261pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1262{
1263 return pci_dev->io_regions[region_num].addr;
1264}
1265
1266static pcibus_t pci_bar_address(PCIDevice *d,
1267 int reg, uint8_t type, pcibus_t size)
1268{
1269 pcibus_t new_addr, last_addr;
1270 int bar = pci_bar(d, reg);
1271 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1272 Object *machine = qdev_get_machine();
1273 ObjectClass *oc = object_get_class(machine);
1274 MachineClass *mc = MACHINE_CLASS(oc);
1275 bool allow_0_address = mc->pci_allow_0_address;
1276
1277 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1278 if (!(cmd & PCI_COMMAND_IO)) {
1279 return PCI_BAR_UNMAPPED;
1280 }
1281 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1282 last_addr = new_addr + size - 1;
1283
1284
1285
1286 if (last_addr <= new_addr || last_addr >= UINT32_MAX ||
1287 (!allow_0_address && new_addr == 0)) {
1288 return PCI_BAR_UNMAPPED;
1289 }
1290 return new_addr;
1291 }
1292
1293 if (!(cmd & PCI_COMMAND_MEMORY)) {
1294 return PCI_BAR_UNMAPPED;
1295 }
1296 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1297 new_addr = pci_get_quad(d->config + bar);
1298 } else {
1299 new_addr = pci_get_long(d->config + bar);
1300 }
1301
1302 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1303 return PCI_BAR_UNMAPPED;
1304 }
1305 new_addr &= ~(size - 1);
1306 last_addr = new_addr + size - 1;
1307
1308
1309
1310
1311 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED ||
1312 (!allow_0_address && new_addr == 0)) {
1313 return PCI_BAR_UNMAPPED;
1314 }
1315
1316
1317
1318
1319
1320
1321 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1322 return PCI_BAR_UNMAPPED;
1323 }
1324
1325
1326
1327
1328
1329
1330
1331 if (last_addr >= HWADDR_MAX) {
1332 return PCI_BAR_UNMAPPED;
1333 }
1334
1335 return new_addr;
1336}
1337
1338static void pci_update_mappings(PCIDevice *d)
1339{
1340 PCIIORegion *r;
1341 int i;
1342 pcibus_t new_addr;
1343
1344 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1345 r = &d->io_regions[i];
1346
1347
1348 if (!r->size)
1349 continue;
1350
1351 new_addr = pci_bar_address(d, i, r->type, r->size);
1352
1353
1354 if (new_addr == r->addr)
1355 continue;
1356
1357
1358 if (r->addr != PCI_BAR_UNMAPPED) {
1359 trace_pci_update_mappings_del(d, pci_dev_bus_num(d),
1360 PCI_SLOT(d->devfn),
1361 PCI_FUNC(d->devfn),
1362 i, r->addr, r->size);
1363 memory_region_del_subregion(r->address_space, r->memory);
1364 }
1365 r->addr = new_addr;
1366 if (r->addr != PCI_BAR_UNMAPPED) {
1367 trace_pci_update_mappings_add(d, pci_dev_bus_num(d),
1368 PCI_SLOT(d->devfn),
1369 PCI_FUNC(d->devfn),
1370 i, r->addr, r->size);
1371 memory_region_add_subregion_overlap(r->address_space,
1372 r->addr, r->memory, 1);
1373 }
1374 }
1375
1376 pci_update_vga(d);
1377}
1378
1379static inline int pci_irq_disabled(PCIDevice *d)
1380{
1381 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1382}
1383
1384
1385
1386
1387static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1388{
1389 int i, disabled = pci_irq_disabled(d);
1390 if (disabled == was_irq_disabled)
1391 return;
1392 for (i = 0; i < PCI_NUM_PINS; ++i) {
1393 int state = pci_irq_state(d, i);
1394 pci_change_irq_level(d, i, disabled ? -state : state);
1395 }
1396}
1397
1398uint32_t pci_default_read_config(PCIDevice *d,
1399 uint32_t address, int len)
1400{
1401 uint32_t val = 0;
1402
1403 assert(address + len <= pci_config_size(d));
1404
1405 if (pci_is_express_downstream_port(d) &&
1406 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) {
1407 pcie_sync_bridge_lnk(d);
1408 }
1409 memcpy(&val, d->config + address, len);
1410 return le32_to_cpu(val);
1411}
1412
1413void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
1414{
1415 int i, was_irq_disabled = pci_irq_disabled(d);
1416 uint32_t val = val_in;
1417
1418 assert(addr + l <= pci_config_size(d));
1419
1420 for (i = 0; i < l; val >>= 8, ++i) {
1421 uint8_t wmask = d->wmask[addr + i];
1422 uint8_t w1cmask = d->w1cmask[addr + i];
1423 assert(!(wmask & w1cmask));
1424 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1425 d->config[addr + i] &= ~(val & w1cmask);
1426 }
1427 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1428 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1429 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1430 range_covers_byte(addr, l, PCI_COMMAND))
1431 pci_update_mappings(d);
1432
1433 if (range_covers_byte(addr, l, PCI_COMMAND)) {
1434 pci_update_irq_disabled(d, was_irq_disabled);
1435 memory_region_set_enabled(&d->bus_master_enable_region,
1436 pci_get_word(d->config + PCI_COMMAND)
1437 & PCI_COMMAND_MASTER);
1438 }
1439
1440 msi_write_config(d, addr, val_in, l);
1441 msix_write_config(d, addr, val_in, l);
1442}
1443
1444
1445
1446
1447
1448static void pci_irq_handler(void *opaque, int irq_num, int level)
1449{
1450 PCIDevice *pci_dev = opaque;
1451 int change;
1452
1453 assert(0 <= irq_num && irq_num < PCI_NUM_PINS);
1454 assert(level == 0 || level == 1);
1455 change = level - pci_irq_state(pci_dev, irq_num);
1456 if (!change)
1457 return;
1458
1459 pci_set_irq_state(pci_dev, irq_num, level);
1460 pci_update_irq_status(pci_dev);
1461 if (pci_irq_disabled(pci_dev))
1462 return;
1463 pci_change_irq_level(pci_dev, irq_num, change);
1464}
1465
1466static inline int pci_intx(PCIDevice *pci_dev)
1467{
1468 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1469}
1470
1471qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1472{
1473 int intx = pci_intx(pci_dev);
1474 assert(0 <= intx && intx < PCI_NUM_PINS);
1475
1476 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1477}
1478
1479void pci_set_irq(PCIDevice *pci_dev, int level)
1480{
1481 int intx = pci_intx(pci_dev);
1482 pci_irq_handler(pci_dev, intx, level);
1483}
1484
1485
1486void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1487{
1488 assert(pci_bus_is_root(bus));
1489 bus->route_intx_to_irq = route_intx_to_irq;
1490}
1491
1492PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1493{
1494 PCIBus *bus;
1495
1496 do {
1497 bus = pci_get_bus(dev);
1498 pin = bus->map_irq(dev, pin);
1499 dev = bus->parent_dev;
1500 } while (dev);
1501
1502 if (!bus->route_intx_to_irq) {
1503 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1504 object_get_typename(OBJECT(bus->qbus.parent)));
1505 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1506 }
1507
1508 return bus->route_intx_to_irq(bus->irq_opaque, pin);
1509}
1510
1511bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1512{
1513 return old->mode != new->mode || old->irq != new->irq;
1514}
1515
1516void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1517{
1518 PCIDevice *dev;
1519 PCIBus *sec;
1520 int i;
1521
1522 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1523 dev = bus->devices[i];
1524 if (dev && dev->intx_routing_notifier) {
1525 dev->intx_routing_notifier(dev);
1526 }
1527 }
1528
1529 QLIST_FOREACH(sec, &bus->child, sibling) {
1530 pci_bus_fire_intx_routing_notifier(sec);
1531 }
1532}
1533
1534void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1535 PCIINTxRoutingNotifier notifier)
1536{
1537 dev->intx_routing_notifier = notifier;
1538}
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1554{
1555 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin);
1556}
1557
1558
1559
1560
1561typedef struct {
1562 uint16_t class;
1563 const char *desc;
1564 const char *fw_name;
1565 uint16_t fw_ign_bits;
1566} pci_class_desc;
1567
1568static const pci_class_desc pci_class_descriptions[] =
1569{
1570 { 0x0001, "VGA controller", "display"},
1571 { 0x0100, "SCSI controller", "scsi"},
1572 { 0x0101, "IDE controller", "ide"},
1573 { 0x0102, "Floppy controller", "fdc"},
1574 { 0x0103, "IPI controller", "ipi"},
1575 { 0x0104, "RAID controller", "raid"},
1576 { 0x0106, "SATA controller"},
1577 { 0x0107, "SAS controller"},
1578 { 0x0180, "Storage controller"},
1579 { 0x0200, "Ethernet controller", "ethernet"},
1580 { 0x0201, "Token Ring controller", "token-ring"},
1581 { 0x0202, "FDDI controller", "fddi"},
1582 { 0x0203, "ATM controller", "atm"},
1583 { 0x0280, "Network controller"},
1584 { 0x0300, "VGA controller", "display", 0x00ff},
1585 { 0x0301, "XGA controller"},
1586 { 0x0302, "3D controller"},
1587 { 0x0380, "Display controller"},
1588 { 0x0400, "Video controller", "video"},
1589 { 0x0401, "Audio controller", "sound"},
1590 { 0x0402, "Phone"},
1591 { 0x0403, "Audio controller", "sound"},
1592 { 0x0480, "Multimedia controller"},
1593 { 0x0500, "RAM controller", "memory"},
1594 { 0x0501, "Flash controller", "flash"},
1595 { 0x0580, "Memory controller"},
1596 { 0x0600, "Host bridge", "host"},
1597 { 0x0601, "ISA bridge", "isa"},
1598 { 0x0602, "EISA bridge", "eisa"},
1599 { 0x0603, "MC bridge", "mca"},
1600 { 0x0604, "PCI bridge", "pci-bridge"},
1601 { 0x0605, "PCMCIA bridge", "pcmcia"},
1602 { 0x0606, "NUBUS bridge", "nubus"},
1603 { 0x0607, "CARDBUS bridge", "cardbus"},
1604 { 0x0608, "RACEWAY bridge"},
1605 { 0x0680, "Bridge"},
1606 { 0x0700, "Serial port", "serial"},
1607 { 0x0701, "Parallel port", "parallel"},
1608 { 0x0800, "Interrupt controller", "interrupt-controller"},
1609 { 0x0801, "DMA controller", "dma-controller"},
1610 { 0x0802, "Timer", "timer"},
1611 { 0x0803, "RTC", "rtc"},
1612 { 0x0900, "Keyboard", "keyboard"},
1613 { 0x0901, "Pen", "pen"},
1614 { 0x0902, "Mouse", "mouse"},
1615 { 0x0A00, "Dock station", "dock", 0x00ff},
1616 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1617 { 0x0c00, "Fireware contorller", "fireware"},
1618 { 0x0c01, "Access bus controller", "access-bus"},
1619 { 0x0c02, "SSA controller", "ssa"},
1620 { 0x0c03, "USB controller", "usb"},
1621 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1622 { 0x0c05, "SMBus"},
1623 { 0, NULL}
1624};
1625
1626static void pci_for_each_device_under_bus_reverse(PCIBus *bus,
1627 void (*fn)(PCIBus *b,
1628 PCIDevice *d,
1629 void *opaque),
1630 void *opaque)
1631{
1632 PCIDevice *d;
1633 int devfn;
1634
1635 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1636 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn];
1637 if (d) {
1638 fn(bus, d, opaque);
1639 }
1640 }
1641}
1642
1643void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
1644 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1645 void *opaque)
1646{
1647 bus = pci_find_bus_nr(bus, bus_num);
1648
1649 if (bus) {
1650 pci_for_each_device_under_bus_reverse(bus, fn, opaque);
1651 }
1652}
1653
1654static void pci_for_each_device_under_bus(PCIBus *bus,
1655 void (*fn)(PCIBus *b, PCIDevice *d,
1656 void *opaque),
1657 void *opaque)
1658{
1659 PCIDevice *d;
1660 int devfn;
1661
1662 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1663 d = bus->devices[devfn];
1664 if (d) {
1665 fn(bus, d, opaque);
1666 }
1667 }
1668}
1669
1670void pci_for_each_device(PCIBus *bus, int bus_num,
1671 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1672 void *opaque)
1673{
1674 bus = pci_find_bus_nr(bus, bus_num);
1675
1676 if (bus) {
1677 pci_for_each_device_under_bus(bus, fn, opaque);
1678 }
1679}
1680
1681static const pci_class_desc *get_class_desc(int class)
1682{
1683 const pci_class_desc *desc;
1684
1685 desc = pci_class_descriptions;
1686 while (desc->desc && class != desc->class) {
1687 desc++;
1688 }
1689
1690 return desc;
1691}
1692
1693static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1694
1695static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1696{
1697 PciMemoryRegionList *head = NULL, **tail = &head;
1698 int i;
1699
1700 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1701 const PCIIORegion *r = &dev->io_regions[i];
1702 PciMemoryRegion *region;
1703
1704 if (!r->size) {
1705 continue;
1706 }
1707
1708 region = g_malloc0(sizeof(*region));
1709
1710 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1711 region->type = g_strdup("io");
1712 } else {
1713 region->type = g_strdup("memory");
1714 region->has_prefetch = true;
1715 region->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1716 region->has_mem_type_64 = true;
1717 region->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1718 }
1719
1720 region->bar = i;
1721 region->address = r->addr;
1722 region->size = r->size;
1723
1724 QAPI_LIST_APPEND(tail, region);
1725 }
1726
1727 return head;
1728}
1729
1730static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1731 int bus_num)
1732{
1733 PciBridgeInfo *info;
1734 PciMemoryRange *range;
1735
1736 info = g_new0(PciBridgeInfo, 1);
1737
1738 info->bus = g_new0(PciBusInfo, 1);
1739 info->bus->number = dev->config[PCI_PRIMARY_BUS];
1740 info->bus->secondary = dev->config[PCI_SECONDARY_BUS];
1741 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS];
1742
1743 range = info->bus->io_range = g_new0(PciMemoryRange, 1);
1744 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1745 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1746
1747 range = info->bus->memory_range = g_new0(PciMemoryRange, 1);
1748 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1749 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1750
1751 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1);
1752 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1753 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1754
1755 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1756 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
1757 if (child_bus) {
1758 info->has_devices = true;
1759 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1760 }
1761 }
1762
1763 return info;
1764}
1765
1766static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1767 int bus_num)
1768{
1769 const pci_class_desc *desc;
1770 PciDeviceInfo *info;
1771 uint8_t type;
1772 int class;
1773
1774 info = g_new0(PciDeviceInfo, 1);
1775 info->bus = bus_num;
1776 info->slot = PCI_SLOT(dev->devfn);
1777 info->function = PCI_FUNC(dev->devfn);
1778
1779 info->class_info = g_new0(PciDeviceClass, 1);
1780 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1781 info->class_info->q_class = class;
1782 desc = get_class_desc(class);
1783 if (desc->desc) {
1784 info->class_info->has_desc = true;
1785 info->class_info->desc = g_strdup(desc->desc);
1786 }
1787
1788 info->id = g_new0(PciDeviceId, 1);
1789 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1790 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID);
1791 info->regions = qmp_query_pci_regions(dev);
1792 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1793
1794 info->irq_pin = dev->config[PCI_INTERRUPT_PIN];
1795 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1796 info->has_irq = true;
1797 info->irq = dev->config[PCI_INTERRUPT_LINE];
1798 }
1799
1800 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1801 if (type == PCI_HEADER_TYPE_BRIDGE) {
1802 info->has_pci_bridge = true;
1803 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1804 } else if (type == PCI_HEADER_TYPE_NORMAL) {
1805 info->id->has_subsystem = info->id->has_subsystem_vendor = true;
1806 info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID);
1807 info->id->subsystem_vendor =
1808 pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID);
1809 } else if (type == PCI_HEADER_TYPE_CARDBUS) {
1810 info->id->has_subsystem = info->id->has_subsystem_vendor = true;
1811 info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID);
1812 info->id->subsystem_vendor =
1813 pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID);
1814 }
1815
1816 return info;
1817}
1818
1819static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1820{
1821 PciDeviceInfoList *head = NULL, **tail = &head;
1822 PCIDevice *dev;
1823 int devfn;
1824
1825 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1826 dev = bus->devices[devfn];
1827 if (dev) {
1828 QAPI_LIST_APPEND(tail, qmp_query_pci_device(dev, bus, bus_num));
1829 }
1830 }
1831
1832 return head;
1833}
1834
1835static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1836{
1837 PciInfo *info = NULL;
1838
1839 bus = pci_find_bus_nr(bus, bus_num);
1840 if (bus) {
1841 info = g_malloc0(sizeof(*info));
1842 info->bus = bus_num;
1843 info->devices = qmp_query_pci_devices(bus, bus_num);
1844 }
1845
1846 return info;
1847}
1848
1849PciInfoList *qmp_query_pci(Error **errp)
1850{
1851 PciInfoList *head = NULL, **tail = &head;
1852 PCIHostState *host_bridge;
1853
1854 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
1855 QAPI_LIST_APPEND(tail,
1856 qmp_query_pci_bus(host_bridge->bus,
1857 pci_bus_num(host_bridge->bus)));
1858 }
1859
1860 return head;
1861}
1862
1863
1864PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
1865 const char *default_model,
1866 const char *default_devaddr)
1867{
1868 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1869 GSList *list;
1870 GPtrArray *pci_nic_models;
1871 PCIBus *bus;
1872 PCIDevice *pci_dev;
1873 DeviceState *dev;
1874 int devfn;
1875 int i;
1876 int dom, busnr;
1877 unsigned slot;
1878
1879 if (nd->model && !strcmp(nd->model, "virtio")) {
1880 g_free(nd->model);
1881 nd->model = g_strdup("virtio-net-pci");
1882 }
1883
1884 list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false);
1885 pci_nic_models = g_ptr_array_new();
1886 while (list) {
1887 DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data,
1888 TYPE_DEVICE);
1889 GSList *next;
1890 if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) &&
1891 dc->user_creatable) {
1892 const char *name = object_class_get_name(list->data);
1893
1894
1895
1896
1897
1898
1899
1900 Object *obj = object_new_with_class(OBJECT_CLASS(dc));
1901 if (object_property_find(obj, "netdev")) {
1902 g_ptr_array_add(pci_nic_models, (gpointer)name);
1903 }
1904 object_unref(obj);
1905 }
1906 next = list->next;
1907 g_slist_free_1(list);
1908 list = next;
1909 }
1910 g_ptr_array_add(pci_nic_models, NULL);
1911
1912 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) {
1913 exit(0);
1914 }
1915
1916 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata,
1917 default_model);
1918 if (i < 0) {
1919 exit(1);
1920 }
1921
1922 if (!rootbus) {
1923 error_report("No primary PCI bus");
1924 exit(1);
1925 }
1926
1927 assert(!rootbus->parent_dev);
1928
1929 if (!devaddr) {
1930 devfn = -1;
1931 busnr = 0;
1932 } else {
1933 if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) {
1934 error_report("Invalid PCI device address %s for device %s",
1935 devaddr, nd->model);
1936 exit(1);
1937 }
1938
1939 if (dom != 0) {
1940 error_report("No support for non-zero PCI domains");
1941 exit(1);
1942 }
1943
1944 devfn = PCI_DEVFN(slot, 0);
1945 }
1946
1947 bus = pci_find_bus_nr(rootbus, busnr);
1948 if (!bus) {
1949 error_report("Invalid PCI device address %s for device %s",
1950 devaddr, nd->model);
1951 exit(1);
1952 }
1953
1954 pci_dev = pci_new(devfn, nd->model);
1955 dev = &pci_dev->qdev;
1956 qdev_set_nic_properties(dev, nd);
1957 pci_realize_and_unref(pci_dev, bus, &error_fatal);
1958 g_ptr_array_free(pci_nic_models, true);
1959 return pci_dev;
1960}
1961
1962PCIDevice *pci_vga_init(PCIBus *bus)
1963{
1964 switch (vga_interface_type) {
1965 case VGA_CIRRUS:
1966 return pci_create_simple(bus, -1, "cirrus-vga");
1967 case VGA_QXL:
1968 return pci_create_simple(bus, -1, "qxl-vga");
1969 case VGA_STD:
1970 return pci_create_simple(bus, -1, "VGA");
1971 case VGA_VMWARE:
1972 return pci_create_simple(bus, -1, "vmware-svga");
1973 case VGA_VIRTIO:
1974 return pci_create_simple(bus, -1, "virtio-vga");
1975 case VGA_NONE:
1976 default:
1977
1978 return NULL;
1979 }
1980}
1981
1982
1983
1984static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1985{
1986 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1987 PCI_BRIDGE_CTL_BUS_RESET) &&
1988 dev->config[PCI_SECONDARY_BUS] <= bus_num &&
1989 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1990}
1991
1992
1993static bool pci_root_bus_in_range(PCIBus *bus, int bus_num)
1994{
1995 int i;
1996
1997 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1998 PCIDevice *dev = bus->devices[i];
1999
2000 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) {
2001 if (pci_secondary_bus_in_range(dev, bus_num)) {
2002 return true;
2003 }
2004 }
2005 }
2006
2007 return false;
2008}
2009
2010static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
2011{
2012 PCIBus *sec;
2013
2014 if (!bus) {
2015 return NULL;
2016 }
2017
2018 if (pci_bus_num(bus) == bus_num) {
2019 return bus;
2020 }
2021
2022
2023 if (!pci_bus_is_root(bus) &&
2024 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
2025 return NULL;
2026 }
2027
2028
2029 for (; bus; bus = sec) {
2030 QLIST_FOREACH(sec, &bus->child, sibling) {
2031 if (pci_bus_num(sec) == bus_num) {
2032 return sec;
2033 }
2034
2035 if (pci_bus_is_root(sec)) {
2036 if (pci_root_bus_in_range(sec, bus_num)) {
2037 break;
2038 }
2039 } else {
2040 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
2041 break;
2042 }
2043 }
2044 }
2045 }
2046
2047 return NULL;
2048}
2049
2050void pci_for_each_bus_depth_first(PCIBus *bus,
2051 void *(*begin)(PCIBus *bus, void *parent_state),
2052 void (*end)(PCIBus *bus, void *state),
2053 void *parent_state)
2054{
2055 PCIBus *sec;
2056 void *state;
2057
2058 if (!bus) {
2059 return;
2060 }
2061
2062 if (begin) {
2063 state = begin(bus, parent_state);
2064 } else {
2065 state = parent_state;
2066 }
2067
2068 QLIST_FOREACH(sec, &bus->child, sibling) {
2069 pci_for_each_bus_depth_first(sec, begin, end, state);
2070 }
2071
2072 if (end) {
2073 end(bus, state);
2074 }
2075}
2076
2077
2078PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
2079{
2080 bus = pci_find_bus_nr(bus, bus_num);
2081
2082 if (!bus)
2083 return NULL;
2084
2085 return bus->devices[devfn];
2086}
2087
2088static void pci_qdev_realize(DeviceState *qdev, Error **errp)
2089{
2090 PCIDevice *pci_dev = (PCIDevice *)qdev;
2091 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
2092 ObjectClass *klass = OBJECT_CLASS(pc);
2093 Error *local_err = NULL;
2094 bool is_default_rom;
2095 uint16_t class_id;
2096
2097 if (pci_dev->romsize != -1 && !is_power_of_2(pci_dev->romsize)) {
2098 error_setg(errp, "ROM size %u is not a power of two", pci_dev->romsize);
2099 return;
2100 }
2101
2102
2103
2104
2105 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) &&
2106 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) {
2107 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2108 }
2109
2110 pci_dev = do_pci_register_device(pci_dev,
2111 object_get_typename(OBJECT(qdev)),
2112 pci_dev->devfn, errp);
2113 if (pci_dev == NULL)
2114 return;
2115
2116 if (pc->realize) {
2117 pc->realize(pci_dev, &local_err);
2118 if (local_err) {
2119 error_propagate(errp, local_err);
2120 do_pci_unregister_device(pci_dev);
2121 return;
2122 }
2123 }
2124
2125 if (pci_dev->failover_pair_id) {
2126 if (!pci_bus_is_express(pci_get_bus(pci_dev))) {
2127 error_setg(errp, "failover primary device must be on "
2128 "PCIExpress bus");
2129 pci_qdev_unrealize(DEVICE(pci_dev));
2130 return;
2131 }
2132 class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE);
2133 if (class_id != PCI_CLASS_NETWORK_ETHERNET) {
2134 error_setg(errp, "failover primary device is not an "
2135 "Ethernet device");
2136 pci_qdev_unrealize(DEVICE(pci_dev));
2137 return;
2138 }
2139 if ((pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)
2140 || (PCI_FUNC(pci_dev->devfn) != 0)) {
2141 error_setg(errp, "failover: primary device must be in its own "
2142 "PCI slot");
2143 pci_qdev_unrealize(DEVICE(pci_dev));
2144 return;
2145 }
2146 qdev->allow_unplug_during_migration = true;
2147 }
2148
2149
2150 is_default_rom = false;
2151 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
2152 pci_dev->romfile = g_strdup(pc->romfile);
2153 is_default_rom = true;
2154 }
2155
2156 pci_add_option_rom(pci_dev, is_default_rom, &local_err);
2157 if (local_err) {
2158 error_propagate(errp, local_err);
2159 pci_qdev_unrealize(DEVICE(pci_dev));
2160 return;
2161 }
2162}
2163
2164PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
2165 const char *name)
2166{
2167 DeviceState *dev;
2168
2169 dev = qdev_new(name);
2170 qdev_prop_set_int32(dev, "addr", devfn);
2171 qdev_prop_set_bit(dev, "multifunction", multifunction);
2172 return PCI_DEVICE(dev);
2173}
2174
2175PCIDevice *pci_new(int devfn, const char *name)
2176{
2177 return pci_new_multifunction(devfn, false, name);
2178}
2179
2180bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp)
2181{
2182 return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp);
2183}
2184
2185PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
2186 bool multifunction,
2187 const char *name)
2188{
2189 PCIDevice *dev = pci_new_multifunction(devfn, multifunction, name);
2190 pci_realize_and_unref(dev, bus, &error_fatal);
2191 return dev;
2192}
2193
2194PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
2195{
2196 return pci_create_simple_multifunction(bus, devfn, false, name);
2197}
2198
2199static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
2200{
2201 int offset = PCI_CONFIG_HEADER_SIZE;
2202 int i;
2203 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
2204 if (pdev->used[i])
2205 offset = i + 1;
2206 else if (i - offset + 1 == size)
2207 return offset;
2208 }
2209 return 0;
2210}
2211
2212static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
2213 uint8_t *prev_p)
2214{
2215 uint8_t next, prev;
2216
2217 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
2218 return 0;
2219
2220 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2221 prev = next + PCI_CAP_LIST_NEXT)
2222 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
2223 break;
2224
2225 if (prev_p)
2226 *prev_p = prev;
2227 return next;
2228}
2229
2230static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
2231{
2232 uint8_t next, prev, found = 0;
2233
2234 if (!(pdev->used[offset])) {
2235 return 0;
2236 }
2237
2238 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
2239
2240 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2241 prev = next + PCI_CAP_LIST_NEXT) {
2242 if (next <= offset && next > found) {
2243 found = next;
2244 }
2245 }
2246 return found;
2247}
2248
2249
2250
2251static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, uint32_t size)
2252{
2253 uint16_t vendor_id;
2254 uint16_t device_id;
2255 uint16_t rom_vendor_id;
2256 uint16_t rom_device_id;
2257 uint16_t rom_magic;
2258 uint16_t pcir_offset;
2259 uint8_t checksum;
2260
2261
2262
2263
2264
2265 rom_magic = pci_get_word(ptr);
2266 if (rom_magic != 0xaa55) {
2267 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
2268 return;
2269 }
2270 pcir_offset = pci_get_word(ptr + 0x18);
2271 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
2272 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
2273 return;
2274 }
2275
2276 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
2277 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
2278 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
2279 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
2280
2281 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
2282 vendor_id, device_id, rom_vendor_id, rom_device_id);
2283
2284 checksum = ptr[6];
2285
2286 if (vendor_id != rom_vendor_id) {
2287
2288 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
2289 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
2290 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2291 ptr[6] = checksum;
2292 pci_set_word(ptr + pcir_offset + 4, vendor_id);
2293 }
2294
2295 if (device_id != rom_device_id) {
2296
2297 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
2298 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
2299 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2300 ptr[6] = checksum;
2301 pci_set_word(ptr + pcir_offset + 6, device_id);
2302 }
2303}
2304
2305
2306static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
2307 Error **errp)
2308{
2309 int64_t size;
2310 char *path;
2311 void *ptr;
2312 char name[32];
2313 const VMStateDescription *vmsd;
2314
2315 if (!pdev->romfile)
2316 return;
2317 if (strlen(pdev->romfile) == 0)
2318 return;
2319
2320 if (!pdev->rom_bar) {
2321
2322
2323
2324
2325 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
2326
2327
2328
2329
2330
2331 if (DEVICE(pdev)->hotplugged) {
2332 error_setg(errp, "Hot-plugged device without ROM bar"
2333 " can't have an option ROM");
2334 return;
2335 }
2336
2337 if (class == 0x0300) {
2338 rom_add_vga(pdev->romfile);
2339 } else {
2340 rom_add_option(pdev->romfile, -1);
2341 }
2342 return;
2343 }
2344
2345 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
2346 if (path == NULL) {
2347 path = g_strdup(pdev->romfile);
2348 }
2349
2350 size = get_image_size(path);
2351 if (size < 0) {
2352 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile);
2353 g_free(path);
2354 return;
2355 } else if (size == 0) {
2356 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
2357 g_free(path);
2358 return;
2359 } else if (size > 2 * GiB) {
2360 error_setg(errp, "romfile \"%s\" too large (size cannot exceed 2 GiB)",
2361 pdev->romfile);
2362 g_free(path);
2363 return;
2364 }
2365 if (pdev->romsize != -1) {
2366 if (size > pdev->romsize) {
2367 error_setg(errp, "romfile \"%s\" (%u bytes) is too large for ROM size %u",
2368 pdev->romfile, (uint32_t)size, pdev->romsize);
2369 g_free(path);
2370 return;
2371 }
2372 } else {
2373 pdev->romsize = pow2ceil(size);
2374 }
2375
2376 vmsd = qdev_get_vmsd(DEVICE(pdev));
2377
2378 if (vmsd) {
2379 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
2380 } else {
2381 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
2382 }
2383 pdev->has_rom = true;
2384 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, pdev->romsize, &error_fatal);
2385 ptr = memory_region_get_ram_ptr(&pdev->rom);
2386 if (load_image_size(path, ptr, size) < 0) {
2387 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile);
2388 g_free(path);
2389 return;
2390 }
2391 g_free(path);
2392
2393 if (is_default_rom) {
2394
2395 pci_patch_ids(pdev, ptr, size);
2396 }
2397
2398 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
2399}
2400
2401static void pci_del_option_rom(PCIDevice *pdev)
2402{
2403 if (!pdev->has_rom)
2404 return;
2405
2406 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
2407 pdev->has_rom = false;
2408}
2409
2410
2411
2412
2413
2414
2415
2416int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
2417 uint8_t offset, uint8_t size,
2418 Error **errp)
2419{
2420 uint8_t *config;
2421 int i, overlapping_cap;
2422
2423 if (!offset) {
2424 offset = pci_find_space(pdev, size);
2425
2426 assert(offset);
2427 } else {
2428
2429
2430
2431
2432 for (i = offset; i < offset + size; i++) {
2433 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2434 if (overlapping_cap) {
2435 error_setg(errp, "%s:%02x:%02x.%x "
2436 "Attempt to add PCI capability %x at offset "
2437 "%x overlaps existing capability %x at offset %x",
2438 pci_root_bus_path(pdev), pci_dev_bus_num(pdev),
2439 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2440 cap_id, offset, overlapping_cap, i);
2441 return -EINVAL;
2442 }
2443 }
2444 }
2445
2446 config = pdev->config + offset;
2447 config[PCI_CAP_LIST_ID] = cap_id;
2448 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2449 pdev->config[PCI_CAPABILITY_LIST] = offset;
2450 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2451 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
2452
2453 memset(pdev->wmask + offset, 0, size);
2454
2455 memset(pdev->cmask + offset, 0xFF, size);
2456 return offset;
2457}
2458
2459
2460void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2461{
2462 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2463 if (!offset)
2464 return;
2465 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
2466
2467 memset(pdev->wmask + offset, 0xff, size);
2468 memset(pdev->w1cmask + offset, 0, size);
2469
2470 memset(pdev->cmask + offset, 0, size);
2471 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
2472
2473 if (!pdev->config[PCI_CAPABILITY_LIST])
2474 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2475}
2476
2477uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2478{
2479 return pci_find_capability_list(pdev, cap_id, NULL);
2480}
2481
2482static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2483{
2484 PCIDevice *d = (PCIDevice *)dev;
2485 const pci_class_desc *desc;
2486 char ctxt[64];
2487 PCIIORegion *r;
2488 int i, class;
2489
2490 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2491 desc = pci_class_descriptions;
2492 while (desc->desc && class != desc->class)
2493 desc++;
2494 if (desc->desc) {
2495 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2496 } else {
2497 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2498 }
2499
2500 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2501 "pci id %04x:%04x (sub %04x:%04x)\n",
2502 indent, "", ctxt, pci_dev_bus_num(d),
2503 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2504 pci_get_word(d->config + PCI_VENDOR_ID),
2505 pci_get_word(d->config + PCI_DEVICE_ID),
2506 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2507 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2508 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2509 r = &d->io_regions[i];
2510 if (!r->size)
2511 continue;
2512 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2513 " [0x%"FMT_PCIBUS"]\n",
2514 indent, "",
2515 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2516 r->addr, r->addr + r->size - 1);
2517 }
2518}
2519
2520static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2521{
2522 PCIDevice *d = (PCIDevice *)dev;
2523 const char *name = NULL;
2524 const pci_class_desc *desc = pci_class_descriptions;
2525 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2526
2527 while (desc->desc &&
2528 (class & ~desc->fw_ign_bits) !=
2529 (desc->class & ~desc->fw_ign_bits)) {
2530 desc++;
2531 }
2532
2533 if (desc->desc) {
2534 name = desc->fw_name;
2535 }
2536
2537 if (name) {
2538 pstrcpy(buf, len, name);
2539 } else {
2540 snprintf(buf, len, "pci%04x,%04x",
2541 pci_get_word(d->config + PCI_VENDOR_ID),
2542 pci_get_word(d->config + PCI_DEVICE_ID));
2543 }
2544
2545 return buf;
2546}
2547
2548static char *pcibus_get_fw_dev_path(DeviceState *dev)
2549{
2550 PCIDevice *d = (PCIDevice *)dev;
2551 char path[50], name[33];
2552 int off;
2553
2554 off = snprintf(path, sizeof(path), "%s@%x",
2555 pci_dev_fw_name(dev, name, sizeof name),
2556 PCI_SLOT(d->devfn));
2557 if (PCI_FUNC(d->devfn))
2558 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2559 return g_strdup(path);
2560}
2561
2562static char *pcibus_get_dev_path(DeviceState *dev)
2563{
2564 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2565 PCIDevice *t;
2566 int slot_depth;
2567
2568
2569
2570
2571
2572 const char *root_bus_path;
2573 int root_bus_len;
2574 char slot[] = ":SS.F";
2575 int slot_len = sizeof slot - 1 ;
2576 int path_len;
2577 char *path, *p;
2578 int s;
2579
2580 root_bus_path = pci_root_bus_path(d);
2581 root_bus_len = strlen(root_bus_path);
2582
2583 ;
2584 slot_depth = 0;
2585 for (t = d; t; t = pci_get_bus(t)->parent_dev) {
2586 ++slot_depth;
2587 }
2588
2589 path_len = root_bus_len + slot_len * slot_depth;
2590
2591
2592 path = g_malloc(path_len + 1 );
2593 path[path_len] = '\0';
2594
2595 memcpy(path, root_bus_path, root_bus_len);
2596
2597
2598
2599 p = path + path_len;
2600 for (t = d; t; t = pci_get_bus(t)->parent_dev) {
2601 p -= slot_len;
2602 s = snprintf(slot, sizeof slot, ":%02x.%x",
2603 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2604 assert(s == slot_len);
2605 memcpy(p, slot, slot_len);
2606 }
2607
2608 return path;
2609}
2610
2611static int pci_qdev_find_recursive(PCIBus *bus,
2612 const char *id, PCIDevice **pdev)
2613{
2614 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2615 if (!qdev) {
2616 return -ENODEV;
2617 }
2618
2619
2620 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
2621 *pdev = PCI_DEVICE(qdev);
2622 return 0;
2623 }
2624 return -EINVAL;
2625}
2626
2627int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2628{
2629 PCIHostState *host_bridge;
2630 int rc = -ENODEV;
2631
2632 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2633 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
2634 if (!tmp) {
2635 rc = 0;
2636 break;
2637 }
2638 if (tmp != -ENODEV) {
2639 rc = tmp;
2640 }
2641 }
2642
2643 return rc;
2644}
2645
2646MemoryRegion *pci_address_space(PCIDevice *dev)
2647{
2648 return pci_get_bus(dev)->address_space_mem;
2649}
2650
2651MemoryRegion *pci_address_space_io(PCIDevice *dev)
2652{
2653 return pci_get_bus(dev)->address_space_io;
2654}
2655
2656static void pci_device_class_init(ObjectClass *klass, void *data)
2657{
2658 DeviceClass *k = DEVICE_CLASS(klass);
2659
2660 k->realize = pci_qdev_realize;
2661 k->unrealize = pci_qdev_unrealize;
2662 k->bus_type = TYPE_PCI_BUS;
2663 device_class_set_props(k, pci_props);
2664}
2665
2666static void pci_device_class_base_init(ObjectClass *klass, void *data)
2667{
2668 if (!object_class_is_abstract(klass)) {
2669 ObjectClass *conventional =
2670 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE);
2671 ObjectClass *pcie =
2672 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE);
2673 assert(conventional || pcie);
2674 }
2675}
2676
2677AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2678{
2679 PCIBus *bus = pci_get_bus(dev);
2680 PCIBus *iommu_bus = bus;
2681 uint8_t devfn = dev->devfn;
2682
2683 while (iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) {
2684 PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev);
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707 if (!pci_bus_is_express(iommu_bus)) {
2708 PCIDevice *parent = iommu_bus->parent_dev;
2709
2710 if (pci_is_express(parent) &&
2711 pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
2712 devfn = PCI_DEVFN(0, 0);
2713 bus = iommu_bus;
2714 } else {
2715 devfn = parent->devfn;
2716 bus = parent_bus;
2717 }
2718 }
2719
2720 iommu_bus = parent_bus;
2721 }
2722 if (iommu_bus && iommu_bus->iommu_fn) {
2723 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn);
2724 }
2725 return &address_space_memory;
2726}
2727
2728void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
2729{
2730 bus->iommu_fn = fn;
2731 bus->iommu_opaque = opaque;
2732}
2733
2734static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2735{
2736 Range *range = opaque;
2737 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2738 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
2739 int i;
2740
2741 if (!(cmd & PCI_COMMAND_MEMORY)) {
2742 return;
2743 }
2744
2745 if (pc->is_bridge) {
2746 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2747 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2748
2749 base = MAX(base, 0x1ULL << 32);
2750
2751 if (limit >= base) {
2752 Range pref_range;
2753 range_set_bounds(&pref_range, base, limit);
2754 range_extend(range, &pref_range);
2755 }
2756 }
2757 for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2758 PCIIORegion *r = &dev->io_regions[i];
2759 pcibus_t lob, upb;
2760 Range region_range;
2761
2762 if (!r->size ||
2763 (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2764 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2765 continue;
2766 }
2767
2768 lob = pci_bar_address(dev, i, r->type, r->size);
2769 upb = lob + r->size - 1;
2770 if (lob == PCI_BAR_UNMAPPED) {
2771 continue;
2772 }
2773
2774 lob = MAX(lob, 0x1ULL << 32);
2775
2776 if (upb >= lob) {
2777 range_set_bounds(®ion_range, lob, upb);
2778 range_extend(range, ®ion_range);
2779 }
2780 }
2781}
2782
2783void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2784{
2785 range_make_empty(range);
2786 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2787}
2788
2789static bool pcie_has_upstream_port(PCIDevice *dev)
2790{
2791 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev));
2792
2793
2794
2795
2796
2797
2798 return parent_dev &&
2799 pci_is_express(parent_dev) &&
2800 parent_dev->exp.exp_cap &&
2801 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT ||
2802 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM);
2803}
2804
2805PCIDevice *pci_get_function_0(PCIDevice *pci_dev)
2806{
2807 PCIBus *bus = pci_get_bus(pci_dev);
2808
2809 if(pcie_has_upstream_port(pci_dev)) {
2810
2811 return bus->devices[0];
2812 } else {
2813
2814 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)];
2815 }
2816}
2817
2818MSIMessage pci_get_msi_message(PCIDevice *dev, int vector)
2819{
2820 MSIMessage msg;
2821 if (msix_enabled(dev)) {
2822 msg = msix_get_message(dev, vector);
2823 } else if (msi_enabled(dev)) {
2824 msg = msi_get_message(dev, vector);
2825 } else {
2826
2827 error_report("%s: unknown interrupt type", __func__);
2828 abort();
2829 }
2830 return msg;
2831}
2832
2833static const TypeInfo pci_device_type_info = {
2834 .name = TYPE_PCI_DEVICE,
2835 .parent = TYPE_DEVICE,
2836 .instance_size = sizeof(PCIDevice),
2837 .abstract = true,
2838 .class_size = sizeof(PCIDeviceClass),
2839 .class_init = pci_device_class_init,
2840 .class_base_init = pci_device_class_base_init,
2841};
2842
2843static void pci_register_types(void)
2844{
2845 type_register_static(&pci_bus_info);
2846 type_register_static(&pcie_bus_info);
2847 type_register_static(&conventional_pci_interface_info);
2848 type_register_static(&pcie_interface_info);
2849 type_register_static(&pci_device_type_info);
2850}
2851
2852type_init(pci_register_types)
2853