1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25#include "qemu/osdep.h"
26#include "qemu/units.h"
27#include "qapi/error.h"
28#include "qemu-common.h"
29#include "qemu/datadir.h"
30#include "cpu.h"
31#include "hw/ppc/ppc.h"
32#include "hw/qdev-properties.h"
33#include "hw/sysbus.h"
34#include "ppc405.h"
35#include "hw/rtc/m48t59.h"
36#include "hw/block/flash.h"
37#include "sysemu/sysemu.h"
38#include "sysemu/qtest.h"
39#include "sysemu/reset.h"
40#include "sysemu/block-backend.h"
41#include "hw/boards.h"
42#include "qemu/log.h"
43#include "qemu/error-report.h"
44#include "hw/loader.h"
45#include "exec/address-spaces.h"
46#include "qemu/cutils.h"
47
48#define BIOS_FILENAME "ppc405_rom.bin"
49#define BIOS_SIZE (2 * MiB)
50
51#define KERNEL_LOAD_ADDR 0x00000000
52#define INITRD_LOAD_ADDR 0x01800000
53
54#define USE_FLASH_BIOS
55
56
57
58
59
60
61
62
63
64
65
66typedef struct ref405ep_fpga_t ref405ep_fpga_t;
67struct ref405ep_fpga_t {
68 uint8_t reg0;
69 uint8_t reg1;
70};
71
72static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
73{
74 ref405ep_fpga_t *fpga;
75 uint32_t ret;
76
77 fpga = opaque;
78 switch (addr) {
79 case 0x0:
80 ret = fpga->reg0;
81 break;
82 case 0x1:
83 ret = fpga->reg1;
84 break;
85 default:
86 ret = 0;
87 break;
88 }
89
90 return ret;
91}
92
93static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
94 unsigned size)
95{
96 ref405ep_fpga_t *fpga;
97
98 fpga = opaque;
99 switch (addr) {
100 case 0x0:
101
102 break;
103 case 0x1:
104 fpga->reg1 = value;
105 break;
106 default:
107 break;
108 }
109}
110
111static const MemoryRegionOps ref405ep_fpga_ops = {
112 .read = ref405ep_fpga_readb,
113 .write = ref405ep_fpga_writeb,
114 .impl.min_access_size = 1,
115 .impl.max_access_size = 1,
116 .valid.min_access_size = 1,
117 .valid.max_access_size = 4,
118 .endianness = DEVICE_BIG_ENDIAN,
119};
120
121static void ref405ep_fpga_reset (void *opaque)
122{
123 ref405ep_fpga_t *fpga;
124
125 fpga = opaque;
126 fpga->reg0 = 0x00;
127 fpga->reg1 = 0x0F;
128}
129
130static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
131{
132 ref405ep_fpga_t *fpga;
133 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
134
135 fpga = g_malloc0(sizeof(ref405ep_fpga_t));
136 memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
137 "fpga", 0x00000100);
138 memory_region_add_subregion(sysmem, base, fpga_memory);
139 qemu_register_reset(&ref405ep_fpga_reset, fpga);
140}
141
142static void ref405ep_init(MachineState *machine)
143{
144 MachineClass *mc = MACHINE_GET_CLASS(machine);
145 const char *bios_name = machine->firmware ?: BIOS_FILENAME;
146 const char *kernel_filename = machine->kernel_filename;
147 const char *kernel_cmdline = machine->kernel_cmdline;
148 const char *initrd_filename = machine->initrd_filename;
149 char *filename;
150 ppc4xx_bd_info_t bd;
151 CPUPPCState *env;
152 DeviceState *dev;
153 SysBusDevice *s;
154 MemoryRegion *bios;
155 MemoryRegion *sram = g_new(MemoryRegion, 1);
156 ram_addr_t bdloc;
157 MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
158 hwaddr ram_bases[2], ram_sizes[2];
159 target_ulong sram_size;
160 long bios_size;
161
162
163 target_ulong kernel_base, initrd_base;
164 long kernel_size, initrd_size;
165 int linux_boot;
166 int len;
167 DriveInfo *dinfo;
168 MemoryRegion *sysmem = get_system_memory();
169 DeviceState *uicdev;
170
171 if (machine->ram_size != mc->default_ram_size) {
172 char *sz = size_to_str(mc->default_ram_size);
173 error_report("Invalid RAM size, should be %s", sz);
174 g_free(sz);
175 exit(EXIT_FAILURE);
176 }
177
178
179 memory_region_init_alias(&ram_memories[0], NULL, "ef405ep.ram.alias",
180 machine->ram, 0, machine->ram_size);
181 ram_bases[0] = 0;
182 ram_sizes[0] = machine->ram_size;
183 memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
184 ram_bases[1] = 0x00000000;
185 ram_sizes[1] = 0x00000000;
186 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
187 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
188
189 sram_size = 512 * KiB;
190 memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
191 &error_fatal);
192 memory_region_add_subregion(sysmem, 0xFFF00000, sram);
193
194#ifdef USE_FLASH_BIOS
195 dinfo = drive_get(IF_PFLASH, 0, 0);
196 if (dinfo) {
197 bios_size = 8 * MiB;
198 pflash_cfi02_register((uint32_t)(-bios_size),
199 "ef405ep.bios", bios_size,
200 blk_by_legacy_dinfo(dinfo),
201 64 * KiB, 1,
202 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
203 1);
204 } else
205#endif
206 {
207 bios = g_new(MemoryRegion, 1);
208 memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
209 &error_fatal);
210
211 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
212 if (filename) {
213 bios_size = load_image_size(filename,
214 memory_region_get_ram_ptr(bios),
215 BIOS_SIZE);
216 g_free(filename);
217 if (bios_size < 0) {
218 error_report("Could not load PowerPC BIOS '%s'", bios_name);
219 exit(1);
220 }
221 bios_size = (bios_size + 0xfff) & ~0xfff;
222 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
223 } else if (!qtest_enabled() || kernel_filename != NULL) {
224 error_report("Could not load PowerPC BIOS '%s'", bios_name);
225 exit(1);
226 } else {
227
228 bios_size = -1;
229 }
230 }
231
232 ref405ep_fpga_init(sysmem, 0xF0300000);
233
234 dev = qdev_new("sysbus-m48t08");
235 qdev_prop_set_int32(dev, "base-year", 1968);
236 s = SYS_BUS_DEVICE(dev);
237 sysbus_realize_and_unref(s, &error_fatal);
238 sysbus_mmio_map(s, 0, 0xF0000000);
239
240 linux_boot = (kernel_filename != NULL);
241 if (linux_boot) {
242 memset(&bd, 0, sizeof(bd));
243 bd.bi_memstart = 0x00000000;
244 bd.bi_memsize = machine->ram_size;
245 bd.bi_flashstart = -bios_size;
246 bd.bi_flashsize = -bios_size;
247 bd.bi_flashoffset = 0;
248 bd.bi_sramstart = 0xFFF00000;
249 bd.bi_sramsize = sram_size;
250 bd.bi_bootflags = 0;
251 bd.bi_intfreq = 133333333;
252 bd.bi_busfreq = 33333333;
253 bd.bi_baudrate = 115200;
254 bd.bi_s_version[0] = 'Q';
255 bd.bi_s_version[1] = 'M';
256 bd.bi_s_version[2] = 'U';
257 bd.bi_s_version[3] = '\0';
258 bd.bi_r_version[0] = 'Q';
259 bd.bi_r_version[1] = 'E';
260 bd.bi_r_version[2] = 'M';
261 bd.bi_r_version[3] = 'U';
262 bd.bi_r_version[4] = '\0';
263 bd.bi_procfreq = 133333333;
264 bd.bi_plb_busfreq = 33333333;
265 bd.bi_pci_busfreq = 33333333;
266 bd.bi_opbfreq = 33333333;
267 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
268 env->gpr[3] = bdloc;
269 kernel_base = KERNEL_LOAD_ADDR;
270
271 kernel_size = load_image_targphys(kernel_filename, kernel_base,
272 machine->ram_size - kernel_base);
273 if (kernel_size < 0) {
274 error_report("could not load kernel '%s'", kernel_filename);
275 exit(1);
276 }
277 printf("Load kernel size %ld at " TARGET_FMT_lx,
278 kernel_size, kernel_base);
279
280 if (initrd_filename) {
281 initrd_base = INITRD_LOAD_ADDR;
282 initrd_size = load_image_targphys(initrd_filename, initrd_base,
283 machine->ram_size - initrd_base);
284 if (initrd_size < 0) {
285 error_report("could not load initial ram disk '%s'",
286 initrd_filename);
287 exit(1);
288 }
289 } else {
290 initrd_base = 0;
291 initrd_size = 0;
292 }
293 env->gpr[4] = initrd_base;
294 env->gpr[5] = initrd_size;
295 if (kernel_cmdline != NULL) {
296 len = strlen(kernel_cmdline);
297 bdloc -= ((len + 255) & ~255);
298 cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
299 env->gpr[6] = bdloc;
300 env->gpr[7] = bdloc + len;
301 } else {
302 env->gpr[6] = 0;
303 env->gpr[7] = 0;
304 }
305 env->nip = KERNEL_LOAD_ADDR;
306 } else {
307 kernel_base = 0;
308 kernel_size = 0;
309 initrd_base = 0;
310 initrd_size = 0;
311 bdloc = 0;
312 }
313}
314
315static void ref405ep_class_init(ObjectClass *oc, void *data)
316{
317 MachineClass *mc = MACHINE_CLASS(oc);
318
319 mc->desc = "ref405ep";
320 mc->init = ref405ep_init;
321 mc->default_ram_size = 0x08000000;
322 mc->default_ram_id = "ef405ep.ram";
323}
324
325static const TypeInfo ref405ep_type = {
326 .name = MACHINE_TYPE_NAME("ref405ep"),
327 .parent = TYPE_MACHINE,
328 .class_init = ref405ep_class_init,
329};
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350typedef struct taihu_cpld_t taihu_cpld_t;
351struct taihu_cpld_t {
352 uint8_t reg0;
353 uint8_t reg1;
354};
355
356static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size)
357{
358 taihu_cpld_t *cpld;
359 uint32_t ret;
360
361 cpld = opaque;
362 switch (addr) {
363 case 0x0:
364 ret = cpld->reg0;
365 break;
366 case 0x1:
367 ret = cpld->reg1;
368 break;
369 default:
370 ret = 0;
371 break;
372 }
373
374 return ret;
375}
376
377static void taihu_cpld_write(void *opaque, hwaddr addr,
378 uint64_t value, unsigned size)
379{
380 taihu_cpld_t *cpld;
381
382 cpld = opaque;
383 switch (addr) {
384 case 0x0:
385
386 break;
387 case 0x1:
388 cpld->reg1 = value;
389 break;
390 default:
391 break;
392 }
393}
394
395static const MemoryRegionOps taihu_cpld_ops = {
396 .read = taihu_cpld_read,
397 .write = taihu_cpld_write,
398 .impl = {
399 .min_access_size = 1,
400 .max_access_size = 1,
401 },
402 .endianness = DEVICE_NATIVE_ENDIAN,
403};
404
405static void taihu_cpld_reset (void *opaque)
406{
407 taihu_cpld_t *cpld;
408
409 cpld = opaque;
410 cpld->reg0 = 0x01;
411 cpld->reg1 = 0x80;
412}
413
414static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
415{
416 taihu_cpld_t *cpld;
417 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
418
419 cpld = g_malloc0(sizeof(taihu_cpld_t));
420 memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100);
421 memory_region_add_subregion(sysmem, base, cpld_memory);
422 qemu_register_reset(&taihu_cpld_reset, cpld);
423}
424
425static void taihu_405ep_init(MachineState *machine)
426{
427 MachineClass *mc = MACHINE_GET_CLASS(machine);
428 const char *bios_name = machine->firmware ?: BIOS_FILENAME;
429 const char *kernel_filename = machine->kernel_filename;
430 const char *initrd_filename = machine->initrd_filename;
431 char *filename;
432 MemoryRegion *sysmem = get_system_memory();
433 MemoryRegion *bios;
434 MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
435 hwaddr ram_bases[2], ram_sizes[2];
436 long bios_size;
437 target_ulong kernel_base, initrd_base;
438 long kernel_size, initrd_size;
439 int linux_boot;
440 int fl_idx;
441 DriveInfo *dinfo;
442 DeviceState *uicdev;
443
444 if (machine->ram_size != mc->default_ram_size) {
445 char *sz = size_to_str(mc->default_ram_size);
446 error_report("Invalid RAM size, should be %s", sz);
447 g_free(sz);
448 exit(EXIT_FAILURE);
449 }
450
451 ram_bases[0] = 0;
452 ram_sizes[0] = 0x04000000;
453 memory_region_init_alias(&ram_memories[0], NULL,
454 "taihu_405ep.ram-0", machine->ram, ram_bases[0],
455 ram_sizes[0]);
456 ram_bases[1] = 0x04000000;
457 ram_sizes[1] = 0x04000000;
458 memory_region_init_alias(&ram_memories[1], NULL,
459 "taihu_405ep.ram-1", machine->ram, ram_bases[1],
460 ram_sizes[1]);
461 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
462 33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
463
464 fl_idx = 0;
465#if defined(USE_FLASH_BIOS)
466 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
467 if (dinfo) {
468 bios_size = 2 * MiB;
469 pflash_cfi02_register(0xFFE00000,
470 "taihu_405ep.bios", bios_size,
471 blk_by_legacy_dinfo(dinfo),
472 64 * KiB, 1,
473 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
474 1);
475 fl_idx++;
476 } else
477#endif
478 {
479 bios = g_new(MemoryRegion, 1);
480 memory_region_init_rom(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
481 &error_fatal);
482 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
483 if (filename) {
484 bios_size = load_image_size(filename,
485 memory_region_get_ram_ptr(bios),
486 BIOS_SIZE);
487 g_free(filename);
488 if (bios_size < 0) {
489 error_report("Could not load PowerPC BIOS '%s'", bios_name);
490 exit(1);
491 }
492 bios_size = (bios_size + 0xfff) & ~0xfff;
493 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
494 } else if (!qtest_enabled()) {
495 error_report("Could not load PowerPC BIOS '%s'", bios_name);
496 exit(1);
497 }
498 }
499
500 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
501 if (dinfo) {
502 bios_size = 32 * MiB;
503 pflash_cfi02_register(0xfc000000, "taihu_405ep.flash", bios_size,
504 blk_by_legacy_dinfo(dinfo),
505 64 * KiB, 1,
506 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
507 1);
508 fl_idx++;
509 }
510
511 taihu_cpld_init(sysmem, 0x50100000);
512
513 linux_boot = (kernel_filename != NULL);
514 if (linux_boot) {
515 kernel_base = KERNEL_LOAD_ADDR;
516
517 kernel_size = load_image_targphys(kernel_filename, kernel_base,
518 machine->ram_size - kernel_base);
519 if (kernel_size < 0) {
520 error_report("could not load kernel '%s'", kernel_filename);
521 exit(1);
522 }
523
524 if (initrd_filename) {
525 initrd_base = INITRD_LOAD_ADDR;
526 initrd_size = load_image_targphys(initrd_filename, initrd_base,
527 machine->ram_size - initrd_base);
528 if (initrd_size < 0) {
529 error_report("could not load initial ram disk '%s'",
530 initrd_filename);
531 exit(1);
532 }
533 } else {
534 initrd_base = 0;
535 initrd_size = 0;
536 }
537 } else {
538 kernel_base = 0;
539 kernel_size = 0;
540 initrd_base = 0;
541 initrd_size = 0;
542 }
543}
544
545static void taihu_class_init(ObjectClass *oc, void *data)
546{
547 MachineClass *mc = MACHINE_CLASS(oc);
548
549 mc->desc = "taihu";
550 mc->init = taihu_405ep_init;
551 mc->default_ram_size = 0x08000000;
552 mc->default_ram_id = "taihu_405ep.ram";
553}
554
555static const TypeInfo taihu_type = {
556 .name = MACHINE_TYPE_NAME("taihu"),
557 .parent = TYPE_MACHINE,
558 .class_init = taihu_class_init,
559};
560
561static void ppc405_machine_init(void)
562{
563 type_register_static(&ref405ep_type);
564 type_register_static(&taihu_type);
565}
566
567type_init(ppc405_machine_init)
568
