qemu/hw/riscv/opentitan.c
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   1/*
   2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
   3 *
   4 * Copyright (c) 2020 Western Digital
   5 *
   6 * Provides a board compatible with the OpenTitan FPGA platform:
   7 *
   8 * This program is free software; you can redistribute it and/or modify it
   9 * under the terms and conditions of the GNU General Public License,
  10 * version 2 or later, as published by the Free Software Foundation.
  11 *
  12 * This program is distributed in the hope it will be useful, but WITHOUT
  13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15 * more details.
  16 *
  17 * You should have received a copy of the GNU General Public License along with
  18 * this program.  If not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "hw/riscv/opentitan.h"
  23#include "qapi/error.h"
  24#include "hw/boards.h"
  25#include "hw/misc/unimp.h"
  26#include "hw/riscv/boot.h"
  27#include "exec/address-spaces.h"
  28#include "qemu/units.h"
  29#include "sysemu/sysemu.h"
  30
  31static const MemMapEntry ibex_memmap[] = {
  32    [IBEX_DEV_ROM] =            {  0x00008000, 16 * KiB },
  33    [IBEX_DEV_RAM] =            {  0x10000000,  0x10000 },
  34    [IBEX_DEV_FLASH] =          {  0x20000000,  0x80000 },
  35    [IBEX_DEV_UART] =           {  0x40000000,  0x1000  },
  36    [IBEX_DEV_GPIO] =           {  0x40040000,  0x1000  },
  37    [IBEX_DEV_SPI] =            {  0x40050000,  0x1000  },
  38    [IBEX_DEV_I2C] =            {  0x40080000,  0x1000  },
  39    [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x1000  },
  40    [IBEX_DEV_RV_TIMER] =       {  0x40100000,  0x1000  },
  41    [IBEX_DEV_SENSOR_CTRL] =    {  0x40110000,  0x1000  },
  42    [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
  43    [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x1000  },
  44    [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x1000  },
  45    [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x1000  },
  46    [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000  },
  47    [IBEX_DEV_PADCTRL] =        {  0x40470000,  0x1000  },
  48    [IBEX_DEV_USBDEV] =         {  0x40500000,  0x1000  },
  49    [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x1000  },
  50    [IBEX_DEV_PLIC] =           {  0x41010000,  0x1000  },
  51    [IBEX_DEV_AES] =            {  0x41100000,  0x1000  },
  52    [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000  },
  53    [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000  },
  54    [IBEX_DEV_KEYMGR] =         {  0x41130000,  0x1000  },
  55    [IBEX_DEV_CSRNG] =          {  0x41150000,  0x1000  },
  56    [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x1000  },
  57    [IBEX_DEV_EDNO] =           {  0x41170000,  0x1000  },
  58    [IBEX_DEV_EDN1] =           {  0x41180000,  0x1000  },
  59    [IBEX_DEV_ALERT_HANDLER] =  {  0x411b0000,  0x1000  },
  60    [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
  61    [IBEX_DEV_OTBN] =           {  0x411d0000,  0x10000 },
  62};
  63
  64static void opentitan_board_init(MachineState *machine)
  65{
  66    const MemMapEntry *memmap = ibex_memmap;
  67    OpenTitanState *s = g_new0(OpenTitanState, 1);
  68    MemoryRegion *sys_mem = get_system_memory();
  69    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
  70
  71    /* Initialize SoC */
  72    object_initialize_child(OBJECT(machine), "soc", &s->soc,
  73                            TYPE_RISCV_IBEX_SOC);
  74    qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
  75
  76    memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
  77        memmap[IBEX_DEV_RAM].size, &error_fatal);
  78    memory_region_add_subregion(sys_mem,
  79        memmap[IBEX_DEV_RAM].base, main_mem);
  80
  81    if (machine->firmware) {
  82        riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
  83    }
  84
  85    if (machine->kernel_filename) {
  86        riscv_load_kernel(machine->kernel_filename,
  87                          memmap[IBEX_DEV_RAM].base, NULL);
  88    }
  89}
  90
  91static void opentitan_machine_init(MachineClass *mc)
  92{
  93    mc->desc = "RISC-V Board compatible with OpenTitan";
  94    mc->init = opentitan_board_init;
  95    mc->max_cpus = 1;
  96    mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
  97}
  98
  99DEFINE_MACHINE("opentitan", opentitan_machine_init)
 100
 101static void lowrisc_ibex_soc_init(Object *obj)
 102{
 103    LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
 104
 105    object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
 106
 107    object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
 108
 109    object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
 110}
 111
 112static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
 113{
 114    const MemMapEntry *memmap = ibex_memmap;
 115    MachineState *ms = MACHINE(qdev_get_machine());
 116    LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
 117    MemoryRegion *sys_mem = get_system_memory();
 118
 119    object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
 120                            &error_abort);
 121    object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
 122                            &error_abort);
 123    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
 124    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
 125
 126    /* Boot ROM */
 127    memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
 128                           memmap[IBEX_DEV_ROM].size, &error_fatal);
 129    memory_region_add_subregion(sys_mem,
 130        memmap[IBEX_DEV_ROM].base, &s->rom);
 131
 132    /* Flash memory */
 133    memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
 134                           memmap[IBEX_DEV_FLASH].size, &error_fatal);
 135    memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
 136                                &s->flash_mem);
 137
 138    /* PLIC */
 139    if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
 140        return;
 141    }
 142    sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
 143
 144    /* UART */
 145    qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
 146    if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
 147        return;
 148    }
 149    sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
 150    sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
 151                       0, qdev_get_gpio_in(DEVICE(&s->plic),
 152                       IBEX_UART_TX_WATERMARK_IRQ));
 153    sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
 154                       1, qdev_get_gpio_in(DEVICE(&s->plic),
 155                       IBEX_UART_RX_WATERMARK_IRQ));
 156    sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
 157                       2, qdev_get_gpio_in(DEVICE(&s->plic),
 158                       IBEX_UART_TX_EMPTY_IRQ));
 159    sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
 160                       3, qdev_get_gpio_in(DEVICE(&s->plic),
 161                       IBEX_UART_RX_OVERFLOW_IRQ));
 162
 163    create_unimplemented_device("riscv.lowrisc.ibex.gpio",
 164        memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
 165    create_unimplemented_device("riscv.lowrisc.ibex.spi",
 166        memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
 167    create_unimplemented_device("riscv.lowrisc.ibex.i2c",
 168        memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
 169    create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
 170        memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
 171    create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
 172        memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size);
 173    create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
 174        memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
 175    create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
 176        memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
 177    create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
 178        memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
 179    create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
 180        memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
 181    create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
 182        memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
 183    create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
 184        memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
 185    create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
 186        memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
 187    create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
 188        memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
 189    create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
 190        memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
 191    create_unimplemented_device("riscv.lowrisc.ibex.aes",
 192        memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
 193    create_unimplemented_device("riscv.lowrisc.ibex.hmac",
 194        memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
 195    create_unimplemented_device("riscv.lowrisc.ibex.kmac",
 196        memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size);
 197    create_unimplemented_device("riscv.lowrisc.ibex.keymgr",
 198        memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size);
 199    create_unimplemented_device("riscv.lowrisc.ibex.csrng",
 200        memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size);
 201    create_unimplemented_device("riscv.lowrisc.ibex.entropy",
 202        memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size);
 203    create_unimplemented_device("riscv.lowrisc.ibex.edn0",
 204        memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size);
 205    create_unimplemented_device("riscv.lowrisc.ibex.edn1",
 206        memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
 207    create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
 208        memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
 209    create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
 210        memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
 211    create_unimplemented_device("riscv.lowrisc.ibex.otbn",
 212        memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
 213}
 214
 215static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
 216{
 217    DeviceClass *dc = DEVICE_CLASS(oc);
 218
 219    dc->realize = lowrisc_ibex_soc_realize;
 220    /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 221    dc->user_creatable = false;
 222}
 223
 224static const TypeInfo lowrisc_ibex_soc_type_info = {
 225    .name = TYPE_RISCV_IBEX_SOC,
 226    .parent = TYPE_DEVICE,
 227    .instance_size = sizeof(LowRISCIbexSoCState),
 228    .instance_init = lowrisc_ibex_soc_init,
 229    .class_init = lowrisc_ibex_soc_class_init,
 230};
 231
 232static void lowrisc_ibex_soc_register_types(void)
 233{
 234    type_register_static(&lowrisc_ibex_soc_type_info);
 235}
 236
 237type_init(lowrisc_ibex_soc_register_types)
 238
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.