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26#include "qemu/osdep.h"
27#include "cpu.h"
28#include "hw/boards.h"
29#include "hw/char/serial.h"
30#include "hw/sparc/sparc64.h"
31#include "qemu/timer.h"
32#include "sysemu/reset.h"
33#include "trace.h"
34
35
36#define TICK_MAX 0x7fffffffffffffffULL
37
38void cpu_check_irqs(CPUSPARCState *env)
39{
40 CPUState *cs;
41 uint32_t pil = env->pil_in |
42 (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
43
44
45 g_assert(qemu_mutex_iothread_locked());
46
47
48 if (env->ivec_status & 0x20) {
49 return;
50 }
51 cs = env_cpu(env);
52
53
54 if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
55 pil |= 1 << 14;
56 }
57
58
59
60 if (pil < (2 << env->psrpil)) {
61 if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
62 trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
63 env->interrupt_index = 0;
64 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
65 }
66 return;
67 }
68
69 if (cpu_interrupts_enabled(env)) {
70
71 unsigned int i;
72
73 for (i = 15; i > env->psrpil; i--) {
74 if (pil & (1 << i)) {
75 int old_interrupt = env->interrupt_index;
76 int new_interrupt = TT_EXTINT | i;
77
78 if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
79 && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
80 trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
81 cpu_tsptr(env)->tt,
82 new_interrupt);
83 } else if (old_interrupt != new_interrupt) {
84 env->interrupt_index = new_interrupt;
85 trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
86 new_interrupt);
87 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
88 }
89 break;
90 }
91 }
92 } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
93 trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
94 env->interrupt_index);
95 env->interrupt_index = 0;
96 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
97 }
98}
99
100static void cpu_kick_irq(SPARCCPU *cpu)
101{
102 CPUState *cs = CPU(cpu);
103 CPUSPARCState *env = &cpu->env;
104
105 cs->halted = 0;
106 cpu_check_irqs(env);
107 qemu_cpu_kick(cs);
108}
109
110void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level)
111{
112 SPARCCPU *cpu = opaque;
113 CPUSPARCState *env = &cpu->env;
114 CPUState *cs;
115
116 if (level) {
117 if (!(env->ivec_status & 0x20)) {
118 trace_sparc64_cpu_ivec_raise_irq(irq);
119 cs = CPU(cpu);
120 cs->halted = 0;
121 env->interrupt_index = TT_IVEC;
122 env->ivec_status |= 0x20;
123 env->ivec_data[0] = (0x1f << 6) | irq;
124 env->ivec_data[1] = 0;
125 env->ivec_data[2] = 0;
126 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
127 }
128 } else {
129 if (env->ivec_status & 0x20) {
130 trace_sparc64_cpu_ivec_lower_irq(irq);
131 cs = CPU(cpu);
132 env->ivec_status &= ~0x20;
133 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
134 }
135 }
136}
137
138typedef struct ResetData {
139 SPARCCPU *cpu;
140 uint64_t prom_addr;
141} ResetData;
142
143static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu,
144 QEMUBHFunc *cb, uint32_t frequency,
145 uint64_t disabled_mask, uint64_t npt_mask)
146{
147 CPUTimer *timer = g_malloc0(sizeof(CPUTimer));
148
149 timer->name = name;
150 timer->frequency = frequency;
151 timer->disabled_mask = disabled_mask;
152 timer->npt_mask = npt_mask;
153
154 timer->disabled = 1;
155 timer->npt = 1;
156 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
157
158 timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu);
159
160 return timer;
161}
162
163static void cpu_timer_reset(CPUTimer *timer)
164{
165 timer->disabled = 1;
166 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
167
168 timer_del(timer->qtimer);
169}
170
171static void main_cpu_reset(void *opaque)
172{
173 ResetData *s = (ResetData *)opaque;
174 CPUSPARCState *env = &s->cpu->env;
175 static unsigned int nr_resets;
176
177 cpu_reset(CPU(s->cpu));
178
179 cpu_timer_reset(env->tick);
180 cpu_timer_reset(env->stick);
181 cpu_timer_reset(env->hstick);
182
183 env->gregs[1] = 0;
184 env->gregs[2] = current_machine->ram_size;
185 env->gregs[3] = 0;
186 if (nr_resets++ == 0) {
187
188 env->pc = s->prom_addr + 0x20ULL;
189 } else {
190 env->pc = s->prom_addr + 0x40ULL;
191 }
192 env->npc = env->pc + 4;
193}
194
195static void tick_irq(void *opaque)
196{
197 SPARCCPU *cpu = opaque;
198 CPUSPARCState *env = &cpu->env;
199
200 CPUTimer *timer = env->tick;
201
202 if (timer->disabled) {
203 trace_sparc64_cpu_tick_irq_disabled();
204 return;
205 } else {
206 trace_sparc64_cpu_tick_irq_fire();
207 }
208
209 env->softint |= SOFTINT_TIMER;
210 cpu_kick_irq(cpu);
211}
212
213static void stick_irq(void *opaque)
214{
215 SPARCCPU *cpu = opaque;
216 CPUSPARCState *env = &cpu->env;
217
218 CPUTimer *timer = env->stick;
219
220 if (timer->disabled) {
221 trace_sparc64_cpu_stick_irq_disabled();
222 return;
223 } else {
224 trace_sparc64_cpu_stick_irq_fire();
225 }
226
227 env->softint |= SOFTINT_STIMER;
228 cpu_kick_irq(cpu);
229}
230
231static void hstick_irq(void *opaque)
232{
233 SPARCCPU *cpu = opaque;
234 CPUSPARCState *env = &cpu->env;
235
236 CPUTimer *timer = env->hstick;
237
238 if (timer->disabled) {
239 trace_sparc64_cpu_hstick_irq_disabled();
240 return;
241 } else {
242 trace_sparc64_cpu_hstick_irq_fire();
243 }
244
245 env->softint |= SOFTINT_STIMER;
246 cpu_kick_irq(cpu);
247}
248
249static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
250{
251 return muldiv64(cpu_ticks, NANOSECONDS_PER_SECOND, frequency);
252}
253
254static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
255{
256 return muldiv64(timer_ticks, frequency, NANOSECONDS_PER_SECOND);
257}
258
259void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
260{
261 uint64_t real_count = count & ~timer->npt_mask;
262 uint64_t npt_bit = count & timer->npt_mask;
263
264 int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
265 cpu_to_timer_ticks(real_count, timer->frequency);
266
267 trace_sparc64_cpu_tick_set_count(timer->name, real_count,
268 timer->npt ? "disabled" : "enabled",
269 timer);
270
271 timer->npt = npt_bit ? 1 : 0;
272 timer->clock_offset = vm_clock_offset;
273}
274
275uint64_t cpu_tick_get_count(CPUTimer *timer)
276{
277 uint64_t real_count = timer_to_cpu_ticks(
278 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset,
279 timer->frequency);
280
281 trace_sparc64_cpu_tick_get_count(timer->name, real_count,
282 timer->npt ? "disabled" : "enabled",
283 timer);
284
285 if (timer->npt) {
286 real_count |= timer->npt_mask;
287 }
288
289 return real_count;
290}
291
292void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
293{
294 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
295
296 uint64_t real_limit = limit & ~timer->disabled_mask;
297 timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
298
299 int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
300 timer->clock_offset;
301
302 if (expires < now) {
303 expires = now + 1;
304 }
305
306 trace_sparc64_cpu_tick_set_limit(timer->name, real_limit,
307 timer->disabled ? "disabled" : "enabled",
308 timer, limit,
309 timer_to_cpu_ticks(
310 now - timer->clock_offset,
311 timer->frequency
312 ),
313 timer_to_cpu_ticks(
314 expires - now, timer->frequency
315 ));
316
317 if (!real_limit) {
318 trace_sparc64_cpu_tick_set_limit_zero(timer->name);
319 timer_del(timer->qtimer);
320 } else if (timer->disabled) {
321 timer_del(timer->qtimer);
322 } else {
323 timer_mod(timer->qtimer, expires);
324 }
325}
326
327SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr)
328{
329 SPARCCPU *cpu;
330 CPUSPARCState *env;
331 ResetData *reset_info;
332
333 uint32_t tick_frequency = 100 * 1000000;
334 uint32_t stick_frequency = 100 * 1000000;
335 uint32_t hstick_frequency = 100 * 1000000;
336
337 cpu = SPARC_CPU(cpu_create(cpu_type));
338 qdev_init_gpio_in_named(DEVICE(cpu), sparc64_cpu_set_ivec_irq,
339 "ivec-irq", IVEC_MAX);
340 env = &cpu->env;
341
342 env->tick = cpu_timer_create("tick", cpu, tick_irq,
343 tick_frequency, TICK_INT_DIS,
344 TICK_NPT_MASK);
345
346 env->stick = cpu_timer_create("stick", cpu, stick_irq,
347 stick_frequency, TICK_INT_DIS,
348 TICK_NPT_MASK);
349
350 env->hstick = cpu_timer_create("hstick", cpu, hstick_irq,
351 hstick_frequency, TICK_INT_DIS,
352 TICK_NPT_MASK);
353
354 reset_info = g_malloc0(sizeof(ResetData));
355 reset_info->cpu = cpu;
356 reset_info->prom_addr = prom_addr;
357 qemu_register_reset(main_cpu_reset, reset_info);
358
359 return cpu;
360}
361
